A new bottom-gated poly-Si thin-film transistor

We have proposed and fabricated the new bottom-gated poly-Si TFT with a partial amorphous-Si (a-Si) region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the reverse leakage currents are decreased significantly in the new poly-Si TFT compared with conventional one. This reduction is due to the suppression of field emission currents by local a-Si region like that of a-Si TFTs while the ON currents are kept almost the same due to the considerable inducement of electron carriers in the short a-Si channel by the positive gate bias     

A novel gate-overlapped LDD poly-Si thin-film transistor

We fabricate a new polycrystalline silicon thin-film transistor (poly-Si TFT), called a gate-overlapped lightly doped drain (GO-LDD) TFT, which reduces the leakage current without sacrificing the ON current. A new GO-LDD TFT, of which the electrical characteristics are tolerable to the change of LDD doping concentration, can be easily fabricated by employing the buffer oxide without any additional LDD implantation. The change of ON current due to the misalignment of the LDD region may be eliminated. Experimental results show that the leakage current of the proposed TFT's is reduced by two orders of magnitude, compared with that of conventional nonoffset TFT, while the ON current is not decreased. It is observed that the ON/OFF current ratio is not changed significantly with LDD doping concentration and LDD length     

A new poly-Si thin-film transistor with poly-Si/a-Si double activelayer

A new poly-Si TFT employing a rather thick poly-Si (400 Å)/a-Si(4000 Å) double active layer is proposed and fabricated in order to improve the stability of poly-Si TFT without sacrificing the on/off current ratio. Due to the thick double layer the on-state drain current of the proposed TFT flows through a broad current path near the drain junction so that the current density in the drain depletion region where large electric field is applied is considerably reduced. Consequently, additional trap state generation attributed to large current flow and large electric field in poly-Si channel decreases and the electrical stability of the proposed device has been considerably improved     

Low temperature poly-Si thin-film transistor fabrication bymetal-induced lateral crystallization

A new low temperature crystallization method for poly-Si TFTs was developed: Metal-Induced Lateral Crystallization (MILC). The a-Si film in the channel area of a TFT was laterally crystallized from the source/drain area, on which an ultrathin nickel layer was deposited before annealing. The a-channel poly-Si TFTs fabricated at 500°C by MILC showed a mobility of 121 cm²/V·s, a threshold voltage of 1.2 V, and an on/off current ratio of higher than 10⁶ . These electrical properties are much better than TFTs fabricated by conventional crystallization at 600°C     

An adaptive thin-film transistor

A thin-film transistor (TFT) is described whose transfer characteristic can be reversibly adapted by a short duration voltage pulse applied to a high impedance gate electrode. The device is a four-terminal two-gate structure. A source, drain, and insulator gate contact form the basic TFT, while the amount and polarity of the polarization charge on the surface of the ferroelectric material of a second gate contact determines the pinchoff voltage of the TFT transfer characteristic. Measurements on experimental units demonstrate that the pinchoff voltage is adjustable over a sizable range, and that TFT transconductance changes in excess of 1000 to 1 can be obtained. The time required to change between different states of the TFT characteristic is limited by the switching time of the ferroelectric material which, in general, can be of the order of microseconds. Electrical instabilities in the transfer characteristics of the devices, however, may limit their practical circuit application. The instabilities are observed as a slow time variation of pinchoff voltage after a state has been established. Experimental units use triglycine sulfate for the ferroelectric material and tellurium-silicon monoxide thin film transistors.     

An analytical model for the epitaxial bipolar transistor

In the n⁺pn^?n⁺ transistor, high-current effects in the base and collector regions are linked within the current ranges of practical interest. To describe such effects, we have derived an analytical model that is based primarily on five assumptions: (1) the structure is approximately one-dimensional; (2) recombination is negligible in the base and collector quasi-neutral regions, and in the three space-charge regions; (3) high-current effects are negligible in the emitter and n⁺-substrate regions; (4) the Fletcher boundary conditions (or the Misawa boundary conditions) can be used for the three space-charge regions; and (5) the ambipolar approach can be used for the base and collector quasi-neutral regions. The primary findings predicted by the n⁺pn^?n⁺ transistor model are: In current ranges of practical interest (usable current gain), the electron concentration profile has a significant “vertical step” located at the collector-base metallurgical junction for all values of collector current. In the limit of extremely-high-current operation, this step tends to vanish. In the current range where the current gain begins to decline rapidly with increasing collector current, the electron concentration at the base boundary of the collector-base space-charge region goes approximately as the square of the hole concentration at the collector boundary of the same region. Because of this relationship, a charge-control calculation is more difficult than a straightforward calculation of carrier concentration for a given degree of accuracy. The n⁺pn^?n⁺ transistor model (which consists of twelve algebraic equations) is particularly useful for the practically important case of an epitaxial bipolar transistor having a very thin, heavily-doped base region.     

An analytical model for the low- emitter-impurity-concentration transistor

The epitaxial transistor model developed by Grung and Warner is adapted for predicting the characteristics of the low-emitter-impurity-concentration (LEC) transistor. The model predicts the following results for the low region (the lightly-doped emitter region): through a given cross section, the minority-carrier drift current is typically larger than the minority-carrier diffusion current. In other words, the model predicts that the conventional low-level minority-carrier diffusion equation is invalid for the low region, especially for typical bias levels. As a result, the effect of the electric field on minority carriers cannot be neglected in the low region of the LEC transistor and (by extension) in the corresponding low regions of such devices as the epitaxial diode and the integrated-injection-logic transistor.     

An analytical model for the power bipolar-MOS transistor

This paper presents an analytical model for the I–V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4–10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in V_F. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase V_F but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.     

An analytical DC model for the modulation-doped field-effect transistor

A novel analytical dc model for the MODFET device is introduced. The model is based on the approximate equations obtained for the 2DEG charge density under the equilibrium and current conduction conditions. The electron charge mobility and velocity-electric field characteristics in the device channel are modeled using semi-empirical expressions in order to obtain the current-voltage drain characteristics that are related directly to the physical parameters of the device structure and its ambient temperature. The calculated current-voltage characteristics using the developed model compare well with the experimental results obtained for a low-noise microwave MODFET at different temperatures. It is believed that due to the model simplicity, it is suitable for implementation in the existing microwave CAD packages.     

An analytical model for the above-threshold characteristics ofpolysilicon thin-film transistors

An analytical model for the above-threshold characteristics of long-channel, small-grain and thin channel polysilicon thin film transistors (TFT's) is presented. This model is constructed by considering the barrier potential and the carrier trapping effect at grain boundaries of the channel. A band tail state located at E_c -0.15 eV is taken into account to simulate the I-V characteristics. Based on the model, the theoretically simulated results show good agreement with experimental data of plasma-passivated and unpassivated TFT devices in a wide range of gate and drain biases and temperature. The correlation of transconductance to gate bias is also investigated. It is found that the decrease of grain-boundary barrier potential with gate voltage enhances the transconductance, while this enhancement effect becomes insignificant and causes a decrease of transconductance at high gate bias     

An integrated photodetector-amplifier using a-Si p-i-n photodiodesand poly-Si thin-film transistors

The authors propose a photodetector-amplifier circuit consisting of a bridge photodetector circuit and a CMOS differential amplifier, both monolithically integrated on a transparent substrate. A test circuit was fabricated using a-Si p-i-n photodiodes and poly-Si thin-film transistors on a quartz substrate. A clear effect of the differential amplifier was demonstrated in the test circuit. It is shown that the circuit performance can be controlled by changing the bias current of the differential amplifier. With a relatively low bias current on the order of 10^-11 A, the circuit works digitally with output voltages either close to 0 V or V_DD. The power consumption of the circuit is approximately 60 μW, which is low enough for use in two-dimensional arrays     

Charge sheet model of a polysilicon thin-film transistor

A simple analytical model for the current–voltage characteristics of a poly-Si thin-film transistor (TFT) using charge sheet analysis has been developed. An effective doping due to the presence of trap levels at grain boundaries and the effect of diffusion current is considered. The model also takes into account the charge sharing factor, necessary to explain the characteristics of a short channel device. The results so obtained for both long- and short-channel lengths were compared with the experimental data and good agreement was found. The transconductance and the drain conductance were also evaluated.     

A p-channel poly-Si/Si1-xGex/Si sandwichedconductivity modulated thin-film transistor

A p-channel poly-Si/Si_1-xGe_x/Si sandwiched conductivity modulated thin-film transistor (CMTFT) is proposed and demonstrated in this paper for the first time. This structure uses a poly-Si/Si_1-xGe_x/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si_1-xGe_x material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide high on-state current. Results show that this structure provides high on-state current as well as low leakage current as compared to that of conventional offset drain TFTs. The on-state current of the structure is 1.3-3 orders of magnitude higher than that of a conventional offset drain TFT at a gate voltage of -24 V and drain voltage ranging from -15 to -5 V while maintaining comparable leakage current     

An analytical and computer-aided model of the AlGaAs/GaAs high electron mobility transistor

An analytical model for the AlGaAs/GaAs high electron mobility transistor (HEMT) or MODFET has been developed. This model uses a Trofimenkoff-type relation [1] for the electron velocity and electrical field and assumes that the electron velocity saturation inside the two-dimensional electron gas channel cause current saturation. It also takes into account the parasitic conduction in the AlGaAs layer by including a MESFET operation. Based on this model, analytical current-voltage equations suitable for computer simulation have been derived. Calculated results for sub-half-micrometer HEMT's show excellent agreement with measured characteristics.     

An amorphous silicon thin-film transistor with fully self-alignedtop gate structure

We have developed a novel fully self-aligned top gate amorphous silicon thin-film transistor, which shows excellent transistor characteristics. Self-alignment is achieved by patterning the gate electrode and then etching the silicon nitride gate insulator, followed by silicidation and ion implantation of the exposed a-Si in the contact regions. We obtain a long channel saturated mobility of 0.9 cm² V^-1 s^-1, while for channel lengths of 6 μm, we obtain an effective mobility of 0.6 cm² V^-1 s^-1, in the saturated region and 0.5 cm² V ^-1 s^-1, in the linear region. This high level of performance, together with the negligible parasitic capacitance of the self-aligned structure, makes this transistor suitable for new demanding applications in active matrix liquid crystal displays and large area X-ray image sensors     

An analytical model to project MOS transistor lifetime improvement by deuterium passivation of interface traps

Based on the hydrogen/deuterium (H/D) isotope effect in interface trap generation and the power law that is widely used to describe the hot-carrier degradation of MOS transistors, a universal model is developed to project the hot-carrier lifetime improvement of MOS transistors by deuterium (D) passivation of interface traps. The validity of this model is verified by comparing its predication with the experimental measurements. The result indicates that the lifetime improvement increases more than exponentially as the D passivation fraction increases.     

An analytical dishing and step height reduction model for chemical mechanical planarization (CMP)

An analytical model for dishing and step height reduction in chemical mechanical planarization (CMP) is presented. The model is based on the assumption that at the feature scale, high areas on the wafer experience higher pressure than low areas. A Prestonian material removal model is assumed. The model delineates how dishing and step height reduction depend on slurry properties (selectivity and Preston's constants), pad characteristics (stiffness and bending ability), polishing conditions (pressure, relative velocity and overpolishing) and wafer surface geometry (linewidth, pitch and pattern density). Model predictions are in good agreement with existing experimental observations. The present model facilitates understanding of the CMP process at the feature scale. Based on the proposed model, design avenues for decreasing dishing and increasing the speed of step height reduction may be explored through modification of appropriate parameters for slurry, pad and polishing conditions. The proposed model may also be used as a design tool for pattern layout to optimize the performance of the CMP process.     

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

A fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large- and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ _inv is controlled by the voltage differenceV _P – V_ch, whereV _ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV _P is defined as the particular value ofV _ch such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV _P – V_S andV _P – V_D. Using the charge sheet model with the assumption of constant doping in the channel, the drain currentI _D is derived and expressed as the difference between a forward componentI _F and a reverse componentI _R. Each of these is proportional to a function ofV _P – V_S, respectivelyV _P – V_D, through a specific currentI _S. This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.     

Exact analytical model of single electron transistor for practical IC design

This paper presents a new exact analytical model for single electron transistor (SET) applicable for circuit simulation. It has been developed based on orthodox theory of single electronics using master equation where a scheme has been suggested to determine the most probable occupied electron states. The proposed model is more flexible and is valid for single or multi-gate, symmetric or asymmetric devices and can also consider the background charge effect. It can be used for large drain-source voltage range whatever the device is biased under symmetric or asymmetric bias conditions. SET characteristics produced by the proposed model have been verified against widely accepted single electron circuits Monte Carlo simulator SIMON and show a good agreement. Moreover, the model has been implemented in a widely used commercial circuit simulator SPICE to enable simulation with conventional electronic elements and a single electron inverter has been simulated and verified with SIMON results.     

An erase model in double poly-Si gate n-channel FAMOS devices

The existence of a poly-Si control gate in an n-channel FAMOS makes the erase characteristics due to ultraviolet light (UVL) illumination different from those of conventional p-channel FAMOS's without control gates. The difference in erasing times between these two types of FAMOS has been explained by the attenuation of UVL in the control gate. However, it was clarified experimentally and analytically in n-channel FAMOS that UVL is propagated horizontally in an optical guide formed between the control gate and substrate and is then absorbed by the floating poly-Si gate. The absorbed UVL intensity in the floating gate through the proposed optical guide is calculated to be 10⁹times stronger than that transmitted directly through the control gate whose thickness and absorption coefficient are assumed to be 3500 Å and 10⁶cm^-1, respectively. The proposed optical guide model is supported in experiments that erase time does not depend on the thickness of the control gate (2400- and 3600-Å devices are compared) and erase time in a device whose optical guides are open only on one side and the other side is covered by the control gate is about 2 times longer than that in a device which has two optical guides open on both sides.