Programmable Gm– C Filters Using Floating-Gate Operational Transconductance Amplifiers

We present programmable, fully differential G_m-C second-order sections (SOS) showing tunability over a wide range of frequencies. The SOSs use floating-gate operational transconductance amplifiers (FG-OTAs) to realize tunability. We present two FG programmable OTAs. The OTAs have a pFET input stage and employ current mirror topology. An FG common-mode feedback (CMFB) circuit as well as a conventional CMFB circuit is described for use with these OTAs. Their performance is compared. Expressions are derived for the differential and common-mode frequency response of the OTAs. Typical simulation and experimental results are shown for prototypes fabricated in a 0.5-mum CMOS process available through MOSIS. The prototypes operate from a single 3.3-V supply with typical bias currents in the 10-100-nA range. We present experimental results showing frequency-and Q-tuning for a low-pass SOS (LPSOS) and a bandpass SOS (BPSOS) designed using these FG-OTAs also fabricated in a 0.5-mum CMOS process. Measured 1-dB compression for LPSOS and BPSOS are -15 and -11 dBm, respectively     

A State-Space Approach to Intermodulation Distortion Estimation in Fully Balanced Bandpass Gm– C Filters With Weak Nonlinearities

A state-space approach to estimating intermodulation distortion in bandpass G_m-C filters with fully balanced, weakly nonlinear transconductors is introduced. It results in compact analytic expressions applicable to G_m-C filters of any order. For verifying the theory, two G_m-C filters with fully balanced weakly nonlinear transconductors have been designed using Cadence. They have been simulated in SpectreS as well as modeled and simulated in Simulink. Theory and simulation results are found in good agreement     

A Sub 1-V Constant Gm– C Switched-Capacitor Current Source

A switched-capacitor bias that provides a constant G_m-C characteristic over process and temperature variation is presented. The bias can be adapted for use with subthreshold circuits, or circuits in strong inversion. It uses eight transistors, five switches, and three capacitors, and performs with supply voltages less than 0.9 V. Theoretical output current is derived, and stability analysis is performed. Simulated results showing an op-amp with very consistent pulse response are presented     

A Low-Power Memory-Efficient Resampling Architecture for Particle Filters

In this paper, we propose a compact threshold-based resampling algorithm and architecture for efficient hardware implementation of particle filters (PFs). By using a simple threshold-based scheme, this resampling algorithm can reduce the complexity of hardware implementation and power consumption. Simulation results indicate that this algorithm has approximately equal performance with the traditional systematic resampling (SR) algorithm when the root-mean-square error (RMSE) and lost track are considered. Experimental comparison of the proposed hardware architecture with those based on the SR and the residual systematic resampling (RSR) algorithms was conducted on a Xilinx Virtex-II Pro field programmable gate array (FPGA) platform in the bearings-only tracking context, and the results establish the superiority of the proposed architecture in terms of high memory efficiency, low power consumption, and low latency.     

Fast State-Space Harmonic-Distortion Estimation in Weakly Nonlinear Gm−C Filters

A fast, one-pass harmonic-distortion estimation algorithm for G _m-C filters is introduced. It is derived using state-space modeling and can be applied directly to G_m-C filters, of any order, with MOS transconductors exhibiting any type of weak nonlinearity. The algorithm is formed out of a small number of explicit expressions involving the filter's structural matrices and the transconductors' nonlinearity. It can be easily implemented in MATLAB. For verification of the theoretical development, the algorithm was used to derive the harmonic distortion of a single-ended G_m-C filter with weakly nonlinear transconductors designed on a 0.5-mum technology. The results of the algorithm and CADENCE simulation were found to be in good agreement     

Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture

A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. By placing the regulator in the low-bandwidth coarse loop, the proposed PLL architecture allows us to maximize its bandwidth to suppress the oscillator phase noise with neither the power supply-noise rejection nor the power dissipation of the regulator being affected. A replica-based regulator introduces a low-frequency pole in its supply-noise transfer function and avoids degradation of supply-noise rejection beyond the regulator-loop's dominant pole frequency. The prototype PLL fabricated in a 0.18 $mu$m digital CMOS process operates from 0.5 to 2.5$~$GHz. At 1.5$~$GHz, the proposed PLL achieves 1.9$~$ ps long-term rms jitter and a worst case supply-noise sensitivity of ${-}$28$~$dB (0.5$~$rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.      

A Wide Tuning Range Gm –C Continuous-Time Analog Filter

A CMOS operational transconductance amplifier (OTA) for low-power and wide tuning range filter application is proposed in this paper. The OTA can work from the weak inversion region to the strong inversion region to maximize the transconductance tuning range. The transconductance can be tuned by changing its bias current. A fifth-order Elliptic low-pass filter implemented with the OTAs was integrated by TSMC 0.18-mum CMOS process. The filter can operate with the cutoff frequency of 250 Hz to 1 MHz. The wide tuning range filter would be suitable for multi-mode applications, especially under the consideration of saving chip areas. The third-order inter-modulation (IM3) of -40 dB was measured over the tuning range with two tone input signals. The power consumption is 0.8 mW at 1-MHz cutoff frequency and 1.8-V supply voltage with the active area less than 0.3 mm²     

一种宽频应用的自适应计时电路

针对传统自适应导通时间控制DC-DC变换器工作频率范围窄的问题,提出了一种宽频应用的自适应计时电路.在锁相环调制DC-DC变换器的基础上,采用全CMOS电流乘法器,将振荡器的电流引入计时电路,使计时电路的中心频率跟随振荡器的基准频率变化,从而使自适应导通时间控制DC-DC变换器工作在较宽频率范围.基于0.18 μm B...     

低压低功耗电流模CMOS带隙基准电路

提出了一种解决电流模带隙基准电路的第三简并态问题的处理方法,设计了一个完整的低压低功耗带隙电路.通过在电路启动时关断导致产生第三简并态的电流通道并监测电路关键节点电压的方法,控制电路的启动过程,使电路在启动时避开第三简并态,进入正常工作状态.HSPICE仿真结果显示,该电路的输出基准电压为793.6 mV,温度漂移系数可低达10 ppm/℃,电源电压大于1 V即可正常工作;在电源电压为1.5 V时,功耗小于5 μW.     

A Programmable 210-μV Offset Rail-to-Rail Gm –C Filter

Low input-referred offset performance and linearity in analog filters are critical design parameters, yet transistor mismatch limitations are a severe hindrance. Programmability is also a feature of growing significance because high performance state-of-the-art systems must adapt on-the-fly to various operating conditions, as is the case in battery-operated electronics where systems traverse through idle, alert, and high performance modes in an effort to conserve energy and extend battery life. This paper presents a continuous and programmable first-order G_m-C filter with sub-millivolt offset performance. Low offset is achieved by auto-zeroing and continuity by ping-ponging between two transconductors, all under the construct of a compact and bandwidth-efficient circuit topology. The proposed G_m-C circuit was fabricated with AMI's 0.5-mum CMOS process technology and achieved an input-referred offset of less than 210 muV, hand-over glitches of less than 40 mV, and 57 dB of linearity over the rail-to-rail input span for a lithium-ion battery supply range of 3 to 4.2 V. The bandwidth and gain of the filter were programmable from 1.1 to 6.5 kHz and 1.27 to 29.1 V/V, respectively, both with better than 3.2% resolution.     

Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture

Most of the coarse-grained reconfigurable architectures (CGRAs) are composed of reconfigurable ALU arrays and configuration cache (or context memory) to achieve high performance and flexibility. Specially, configuration cache is the main component in CGRA that provides distinct feature for dynamic reconfiguration in every cycle. However, frequent memory-read operations for dynamic reconfiguration cause much power consumption. Thus, reducing power in configuration cache has become critical for CGRA to be more competitive and reliable for its use in embedded systems. In this paper, we propose dynamically compressible context architecture for power saving in configuration cache. This power-efficient design of context architecture works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves up to 39.72% power in configuration cache with negligible area overhead (2.16%).      

LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs

Massive test data volume and excessive test power consumption have become two strict challenges for very large scale integrated circuit testing. In BIST architecture, the unspecified bits are randomly filled by LFSR reseeding-based test compression scheme, which produces enormous switching activities during circuit testing, thereby causing high test power consumption for scan design. To solve the above thorny problem, LFSR reseeding-oriented low-power test-compression architecture is developed, and an optimized encoding algorithm is involved in conjunction with any LFSR-reseeding scheme to effectively reduce test storage and power consumption, it includes test cube-based block processing, dividing into hold partition sets and updating hold partition sets. The main contributions is to decrease logic transitions in scan chains and reduce specified bit in test cubes generated via LFSR reseeding. Experimental results demonstrate that the proposed scheme achieves a high test compression efficiency than the existing methods while significantly reduces test power consumption with acceptable area overhead for most Benchmark circuits.     

A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing

This paper describes a low-power programmable DSP architecture that targets audio signal processing. The architecture can be characterized as a heterogeneous multiprocessor consisting of small instruction set processors called mini-cores as well as standard DSP and CPU cores that communicate using message passing. The mini-cores are tailored for different classes of filtering algorithms (FIR, IIR, N-LMS etc.), and in a typical system the communication among processors occur at the sampling rate only.The mini-cores are intended as soft-macros to be used in the implementation of system-on-chip solutions using a synthesis-based design flow targeting a standard-cell implementation. They are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs of the application. To give an impression of the size of a mini-core we mention that one of the FIR mini-cores in a prototype design has 16 instructions, a 32-word × 16-bit program memory, a 64-word × 16-bit data memory and a 25-word × 16-bit coefficient memory.Results obtained from the design of a prototype chip containing mini-cores for a hearing aid application, demonstrate a power consumption that is only 1.5–1.6 times larger than a hardwired ASIC and more than 6–21 times lower than current state of the art low-power DSP processors. This is due to: (1) the small size of the processors and (2) a smaller instruction count for a given task.     

A Practical Parallel Architecture for Stacks Filters

Stack filters belong to the class of non-linear filters and include the well-known median filter, weighted median filters, order statistic filters and weighted order statistic filters. Any stack filter can be implemented by using the parallel threshold decomposition architecture which allows implementing their non-linear processing by means of a collection of identical binary filters (Boolean logic circuits). Although it is conceptually simple and useful to study the filter properties, this architecture is not practical for direct hardware implementation because as many as (M – 1) binary filters are required for a M-valued input signal and M is large in many applications.In this paper we introduce a new parallel architecture for stack filter implementations. The complexity is now proportional to the window width L of the filter, instead of to M. In most applications L is much smaller than M which translates into efficient hardware implementations. The attractive characteristic of ease of design exhibited by the threshold decomposition architecture is kept. In fact, for a given stack filter both in the conventional implementation and in the proposed one, the same binary filter is required. The key concept supporting the new architecture is a modified decomposition scheme which generates L binary signals for a multi-valued input. As an application example, a complex WOS filter is designed and prototyped in an FPGA.     

Design Equations for a Class of Wide-Band Bandpass Filters (Short Papers)

Design equations and experimental data for a class of bandpass filters having up to two attenuation poles at finite frequencies in the stopband are presented. The new designs are obtained by a relatively simple modification of only the end sections of conventional interdigital and half-wave parallel coupled-line filters. Practical realizability constraints generally limit the design technique to wide-band flters.     

Algorithms Transformation Techniques for Low-Power Wireless VLSI Systems Design

This paper presents an overview of algorithmtransformation techniques and discusses their role inthe development of hardware-efficient and low-power VLSIalgorithms and architectures for communication systems. Algorithm transformation techniquessuch as retiming, look-ahead and relaxed pipelining,parallel processing, folding, unfolding, and strengthreduction are described. These techniques are applied statically (i.e., during the system designphase) and hence are referred to as static algorithmtransformations (SATs). SAT techniques alter thestructural and functional properties of a givenalgorithm so as to be able to jointly optimizeperformance measures in the algorithmic (signal-to-noiseratio [SNR] and bit error rate [BER]) and VLSI (powerdissipation, area and throughput) domains. Next, a new class of algorithm transformations referred toas dynamic algorithm transformations (DAT) is presented.These transformations exploit the nonstationarity in theinput signal environment to determine and assign minimum computational requirements foran algorithm in real time. Both SAT and DAT techniquesare poised to play a critical role in the development oflow-power wireless VLSI systems given the trend toward increasing digital signal processing inthese systems.     

A Compact and Low-Power CMOS Circuit for Fully Integrated NEMS Resonators

This brief presents a fully integrated nanoelectromechanical system (NEMS) resonator, operable at frequencies in the megahertz range, together with a compact built-in CMOS interfacing circuitry. The proposed low-power second-generation current conveyor circuit allows detailed read-out of the nanocantilever structure for either extraction of equivalent circuit models or comparative studies at different pressure and dc biasing conditions. In this sense, extensive experimental results are presented for a real mixed electromechanical system integrated through a combination of in-house standard CMOS technology and nanodevice post-processing by nanostencil lithography. The proposed read-out scheme can be easily adapted to operate the nanocantilever in closed loop operation as a stand-alone NEMS oscillator     

基于望远镜搜索的块匹配运动估值的低功耗VLSI结构

在一种基于望远镜搜索的块匹配运动估值的VLSI实现中,对用于加速搜索的传统心动阵列引擎进行了结构上的改进,从而能够显著地降低功耗.方法是使用一种新的块匹配误差计算的提早跳出技术,并通过在阵列处理单元中屏蔽操作数来避免不必要的计算操作.基于算法模拟结果的简单估计表明：使用新结构搜索引擎的运动估值,功耗可降低到原来的40％左右,而仍然保持着相同的处理速度和相似的视频解码图质量.     

一种低功耗低噪声相关双取样电路的研究

为了尽量在前级消除CMOS图像传感器读出电路中的主要噪声源，本文提出一种低功耗低噪声的相关双取样电路，开关晶体管采用PMOS晶体管代替传统的NMOS晶体管，避免了NMOS管的阈值损失，有效地降低功耗而不减小信号摆幅，降低了1/f噪声。与传统CDS电路相比较，所提出的CDS电路的输出采用对称列选通开关和源跟随晶体管，减少了两个电流源晶体管和一个偏置电源，有效地降低了功耗：同时，现有工艺能制造出性能匹配很好的对称晶体管，有效地消除器件本身由于阈值偏差带来的固定平面噪声。模拟结果表明，在电源电压为3．3V的情况下，像素单元响应动态范围(输出幅值接近电源电压)较宽，像素单元及CDS正常工作时消耗的能量是1．73μW。