Arrayed waveguide dynamic gain equalization filter with reducedinsertion loss and increased dynamic range

We present an arrayed waveguide dynamic gain equalization filter with less than 4.5-dB insertion loss and greater than 14-dB dynamic range over the C-band resulting from three improvements: a circulator and polarization splitter combined into one, used to make the device polarization insensitive; segmentation in the star coupler transition regions; and an exponential control wavelength distribution     

Signal-to-noise-ratio degradation caused by polarization-dependent loss and the effect of dynamic gain equalization

This paper describes a study of the effect of polarization-dependent loss (PDL) on the signal-to-noise ratio (SNR) in optical communications systems, taking into account the effect of dynamic gain equalization. The paper shows that the PDL-induced SNR penalty is caused by two distinct mechanisms related to the two polarization components of the amplified spontaneous emission noise generated in each amplifier. The noise components whose polarization is parallel to the signal at the various amplifier locations dominate the PDL-induced penalty in the absence of gain equalization. In the presence of even a moderate number of gain equalizers, the orthogonal noise components dominate the SNR degradation. Expressions are obtained relating the outage probability to the necessary performance margin that needs to be allocated for PDL.     

Planar lightwave circuit eight-channel CWDM multiplexer with <3.9-dB insertion loss

This paper describes the demonstration of an improved eight-channel coarse wavelength-division multiplexer. The fully packaged channel losses range from 2.3 to 3.9 dB, the 1-dB bandwidth is 16.3 nm, and the crosstalk is <-28dB. This silica-waveguide device could have very low cost.     

A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function

This paper describes a CMOS programmable gain amplifier (PGA) that maintains a 3-dB bandwidth greater than 110 MHz and can provide an 84-dB gain control range with 1-dB step resolution. The PGA can also be operated in a low-power mode with 3-dB bandwidth greater than 71 MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a /spl plusmn/0.7-dB logarithmic accuracy over an 80-dB dynamic range. It achieves -83-dBm sensitivity and consumes 13 mA from a single 3-V supply in the normal power mode. The chip area, including pads, occupies 1.5/spl times/1.5 mm/sup 2/.     

Dynamic gain equalisation filter based on integrated optical transversal filter with asymmetric combiner

A compact dynamic gain equalisation filter on a silica-based planar lightwave circuit has been fabricated. The filter is based on the authors' newly developed optical transversal filter that uses an asymmetric combiner. This device flattened the amplified spontaneous emission spectrum of an erbium-doped fibre amplifier to a ripple of /spl sim/1 dB over a wavelength range of 30 nm.     

A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply

A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98 dB with 2 dB gain steps and is controlled by 6-bit gain control bits for a 3 V power supply. It has been fabricated in a 0.5 /spl mu/m 15 GHz f/sub T/ Si BiCMOS process and draws 13 mA. The active die area taken up by the circuit is 400 /spl mu/m /spl times/ 1170 /spl mu/m. A noise figure (NF) of 4.9 dB was measured at the maximum gain setting. In addition, an analysis of the bias current generation to provide dB-linear gain control is presented.     

Micromachined V-band CMOS bandpass filter with 2 dB insertion loss

A low-insertion-loss V-band CMOS bandpass filter is demonstrated. The proposed filter architecture has the following features: the low-frequency transmission-zero (vz1) and the high-frequency transmission-zero (vz2) can be tuned by the series-feedback capacitor Cs and the parallelfeedback capacitor Cp, respectively. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, this filter achieved insertion loss (1/S21) lower than 3 dB over the frequency range 52.5?76.8 GHz. The minimum insertion loss was 2 dB at 63.5 GHz, the best results reported for a V-band CMOS bandpass filter in the literature.     

低损耗贴片式独块状介质滤波器的设计与制作

设计制作了一种低损耗、贴片式(SMD)独块状的八级介质滤波器。该滤波器采用切比雪夫响应的方法设计,利用εr为45的高Q值独块状微波陶瓷制作,谐振器之间使用电容和电容加载耦合。制备出了中心频率为897.5MHz、插入损耗小于2.5 dB的介质滤波器。测试结果表明,该滤波器满足800~1 500 MHz频率范围通讯基站要求。     

Epitaxially grown GaN thin-film SAW filter with high velocity andlow insertion loss

This study proposes GaN thin film as a piezoelectric material for SAW (surface acoustic wave) filters. Highly piezoelectric GaN film with a good surface morphology (RMS roughness =0.7 nm) was obtained on a 2-in (0001)-oriented sapphire substrate by MOCVD growth. The fabricated GaN SAW filter exhibited a very high velocity of 5803 m/s and relatively low insertion loss of -7.7 dB, The attenuation of the center frequency was about 22 dB smaller than those at the tops of the first sidelobes. When the wavelength of the IDT electrode was 60 μm (λ/4=15 μm), the center frequency was measured at 96.6 MHz, thereby facilitating a ~GHz operation when the IDT geometry is designed on a 1 μm scale. The calculated electromechanical coupling factor (K²) was about 4.3±0.3% which is larger than those obtained from other thin film piezoelectric materials and allows the realization of wider filter fractional bandwidths. TCF (temperature coefficient of frequency) was measured as low as -18.3 ppm/°C in the range from -25 to 50°C. These superior characteristics demonstrate that epitaxially grown GaN thin film can be successfully used for high performance SAW filters     

Comment on `Sallen and Key filter networks with amplifier gain larger than or equal to unity'

Refers to an article by G. S. Moschytz (see abstr. B6114 of 1968) that gives consideration to the realization of a second-order transfer function of specified form through utilization of RC elements plus a noninverting operational amplifier. Moschytz claims in the abstract that he has presented a suitable realization, a modified Sallen and Key network, that contains a noninverting amplifier having a gain that can always be made greater than or equal to unity. Such a gain then permits one to incorporate a noninverting operational amplifier into the design. This correspondence shows that there exists a subclass of second-order transfer functions that, when realized by Moschytz's realization procedure, results in a gain constant that is less than unity for all values of the available parameters. It is then not possible to incorporate a noninverting operational amplifier without altering the network structure. A simple modification of Moschytz's work is presented that assures the existence of a realization that includes a noninverting operational amplifier.     

A 0.6-V 1.6-mW transformer-based 2.5-GHz downconversion mixer with +5.4-dB gain and -2.8-dBm IIP3 in 0.13-/spl mu/m CMOS

On-chip transformers are best suited to lower the supply voltage in RF integrated circuits. A design method to achieve a high current gain with an on-chip transformer operating in resonance is presented. The proposed method will be proven analytically and has been applied to a downconversion mixer. Thereby part of the overall gain of the mixer has been shifted from the RF input stage to the transformer. Thus, the power consumption has been reduced and, in spite of the low supply voltage, moderate linearity has been achieved. Although the transformer has a bandpass behavior, a 3-dB bandwidth of 900 MHz at a center frequency of 2.5 GHz has been achieved. The downconversion mixer has been realized in 0.13-mum CMOS. It consumes 1.6 mW from a 0.6-V supply. A gain of +5.4 dB, a third-order intercept point of -2.8 dBm, an input 1-dB compression point of -9.2 dBm, and a single-sideband noise figure of 14.8 dB have been achieved     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

A circuit technology for a self-refresh 16 Mb DRAM with less than0.5 μA/MB data-retention current

A 16M self-refresh DRAM achieving less than 0.5 μA per megabyte data retention current has been developed. Several techniques to achieve low retention current, including a relaxed junction biasing (RTB) scheme, a plate-floating leakage-monitoring (PFM) system, and a V_BB pull-down word-line driver (PDWD) are described. An extension of data-retention time by three-fold and the refresh timer period by 30-fold over previously reported self-refresh DRAMs has been achieved. This results in a reduction of the ac refresh-current to less than 0.4 μA per megabyte. Furthermore, the addition of a gate-received V_BB detector (GRD) reduces dc retention current to less than 0.1 μA per megabyte. This allows a 20-megabyte RAM disk to retain data for 2.5 years when powered by a single button-shaped 190-mAh lithium battery     

Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time /spl Sigma//spl Delta/ ADC

This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-/spl mu/m BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (/spl Sigma//spl Delta/) ADC has 84-dB dynamic range over a total bandwidth of /spl plusmn/135 kHz for an active area of 0.4 mm/sup 2/. Hence, most of the channel filtering is realized in a CMOS IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm/sup 2/.     

Polymer solar cells based low bandgap A1-D-A2-D terpolymer based on fluorinated thiadiazoloquinoxaline and benzothiadiazole acceptors with energy loss less than 0.5 eV

We synthesized an ultra low bandgap terpolymer denoted as P containing fluorinated-fluorene attached thiadiazoloquinoxaline and benzothiadiazole acceptors and thiophene as donor in its backbone and investigated its optical and electrochemical properties. This terpolymer is used for as donor along with PC₇₁BM as electron acceptor in solution processed polymer solar cells (PSCs). The P showed a shows strong absorption band from 650 nm to 1100 nm with an optical bandgap of 1.12 eV and highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) energy levels of −5.25 eV and −3.87 eV, respectively. After the optimization of P to PC₇₁BM weight ratio, the optimized weight ratio 1:2 in chlorobenzene (CB) solution, the PSC showed overall power conversion efficiency of 4.10% (J_sc of 10.96 mA/cm², V_oc of 0.68 V and FF of 0.55). After the solvent additive (3 v% DIO) followed by subsequent thermal annealing (SA-TA) the PCE has been increased up to 7.54% with J_sc of 16.12 mA/cm², V_oc of 0.65 V and FF of 0.72. The increase in the PCE is related with the enhancement in the both J_sc and FF, attributed optimized nanoscale morphology of the active layer for both efficient exciton dissociation and charge transport towards the electrodes and balanced charge transport in the device, induced by the TSA treatment of the active layer. This is the highest PCE of PSCs with an energy loss about 0.47 eV with the low bandgap of 1.12 eV.