一种简易的智能数字芯片检测装置

针对实验教学过程中数字芯片型号识别和内部故障等问题,设计了一种基于MSP430系列单片机的低功耗智能数字芯片检测装置。利用布尔函数关系式建立了故障集,并对测试芯片生成测试向量,通过单片机编写待测芯片逻辑功能的测试程序,用单片机I/O对待测芯片的逻辑功能进行检测,并将检测结果与存储的芯片逻辑功能进行对比,判断待测芯片是否存在故障。实验结果表明,该装置能够实现对双列直插式数字芯片的快速检测,并显示数字芯片型号或故障,具有体积小、检测速度快,使用方便等优点。     

基于故障对布尔表的模拟电路测试性分析方法

为充分利用测试性验证试验的故障响应特征信息,提高测试性分析结果的准确性,基于故障物理注入技术,提出采用整数对布尔表对模拟电路进行测试性分析的方法。首先分析现有测试性分析方法存在的不足之处;然后根据实测数据构建故障对布尔表,并以此为基础提出预计故障检测率、故障隔离率和故障虚警率等指标的计算公式以及测试性分析步骤;最后结合串联稳压电路实例对文章所提方法进行验证。实验结果表明:与D矩阵模型方法和整数编码字典方法相比,该法都具有更高的故障分辨能力,能够为模拟电路的测试性分析提供更准确的评价指标。     

基于故障数据的设备运行可靠性分析与评估

基于故障数据,对设备运行可靠性进行了分析与评估。对某汽车制造企业的一台卧式加工中心的故障数据进行了统计与分析,形成观测样本,并拟合出了设备故障间隔时间的概率密度分布函数和累计分布函数曲线,从而推断得出其分布规律可能服从威布尔分布。然后通过对威布尔分布函数相关性进行检验,验证了该设备的故障间隔时间分布服从威布尔分布。最后根据统计结果计算得出了该设备的各项可靠性评估指标。     

集成电路多故障测试生成算法研究

对组合电路的测试生成算法进行研究,介绍具有约束条件的布尔差分算法,还对时序电路的测试生成算法进行研究,九值算法比D算法在做D驱赶时要减少很多次无用的计算,在对电路进行描述时充分考虑了故障对电路的重复影响作用,可以对D算法无法产生测试的故障产生测试矢量.     

基于KDE-FPBT的模拟电路测试性分析与故障诊断方法研究

针对传统测试性模型故障分辨率低的问题,提出一种基于故障对布尔表的模拟电路测试性分析与故障诊断方法。根据故障对布尔表的特点构建新的测试性模型,研究相应的故障检测率和隔离率预计方法。基于核密度估计实现实数域样本数据到故障对布尔表的转换,并采用"一对一"的投票策略完成对实测数据的故障诊断推理。以Sallen-Key带通滤波电路为例开展仿真实验,通过与经典的相关性模型以及整数编码字典进行比较,表明所提方法具有更加突出的故障检测与隔离能力。     

自动测试系统资源模型化设计

通过对通用自动测试系统设计方法的分析,提出了自动测试系统资源模型化的描述方法.该方法从数学的角度将系统的硬件资源纳入统一的逻辑表达范畴,按照硬件资源的功能设计了5大系统模型,并根据各个模型的特点设计了相应的数学函数,进而实现了系统资源的完备性描述,并实现了硬件资源与测试系统软件的交互.在实际工作中,将资源模型化设计纳入了适配器的设计过程中,取得了良好的效果.同时该工作为测试程序集的开发和仪器互换性设计奠定了基础.     

边界扫描测试生成的数学基础

本文以边界扫描测试的布尔矩阵描述模型为基础,证明了边界扫描测试生成的两个一般性定理。其中,定理一给出了能检测所有故障的测试矩阵的紧凑性条件,定理二给出了能隔离所有故障的测试矩阵的完备性条件。以定理为基础,提出了两种边界扫描测试生成的一般性策略,为进一步研究边界扫描测试生成优化算法奠定了理论基础。     

模糊支撑半径变量贝叶斯网络多态系统故障概率分析

针对现有隶属函数描述系统及部件故障状态的不足,构建了一种含模糊支撑半径变量的隶属函数来描述部件故障状态,提出了一种基于模糊支撑半径变量的贝叶斯网络多态系统故障概率计算方法。在隶属函数的构造中,用变量代替精确值描述隶属函数模糊支撑半径,建立了含模糊支撑半径变量的隶属函数;并将其引入贝叶斯网络,利用桶消元法对多态系统叶节点故障概率进行分析,得到叶节点故障概率变化曲线。将所提出的方法与文献中基于模糊支撑半径为定值的隶属函数贝叶斯网络方法相比较,验证了方法的有效性。最后,将该方法应用到数控机床主轴系统故障分析实例中,对叶节点故障概率进行计算。结果表明,该方法能够有效解决多态系统故障状态隶属函数选择中的主观性问题。     

数字电路可测性设计的一种故障定位方法

在逻辑函数ReedMuller模式的电路可测性设计方面，文章采用AND门阵列和XOR门树结构来设计电路，提出了一种设计方案，可实现任意逻辑函数的功能，而且所得电路具有通用测试集和完全可故障定位的特点。给出了进行故障定位的方法，并可把它应用于其他相关电路的可测性设计。     

基于故障属性的测试性验证试验样本分配方案

故障样本分配方案是测试性验证试验的关键技术之一.针对现有基于故障率的按比例分层抽样分配方案试验结果不可信的问题,提出基于故障属性的测试性验证试验样本分配方案.该方案在综合考虑故障率、故障后果和故障被检测难度等故障属性元素的基础上,建立了故障属性模型和故障属性值计算模型,并根据故障属性值相对比值的方法进行样本分配.案例应用结果表明:与基于故障率的按比例分层抽样分配方案相比,该方案更加合理,工程适用性更高.     

A method of majority logic reduction for quantum cellular automata

The basic Boolean primitive in quantum cellular automata (QCA) is the majority gate. In this paper, a method for reducing the number of majority gates required for computing three-variable Boolean functions is developed to facilitate the conversion of sum-of-products expression into QCA majority logic. Thirteen standard functions are introduced to represent all three-variable Boolean functions and the simplified majority expressions corresponding to these standard functions are presented. We describe a novel method for using these standard functions to convert the sum-of-products expression to majority logic. By applying this method, the hardware requirements for a QCA design can be reduced. As an example, a 1-bit QCA adder is constructed with only three majority gates and two inverters. The adder is designed and simulated using QCADesigner, a design and simulation tool for QCA. We will show that the proposed method is very efficient and fast in deriving the simplified majority expressions in QCA design.     

An analytic solution for a fault tree with circular logics in which the systems are linearly interrelated

A circular logic or a logical loop is defined as the infinite circulation of supporting relations due to their mutual dependencies among the systems in the fault tree analysis. While many methods to break the circular logic have been developed and used in the fault tree quantification codes, the general solution for a circular logic is not generally known as yet. This paper presents an analytic solution for circular logics in which the systems are linearly interrelated with each other. To formulate the analytic solution, the relations among systems in the fault tree structure are described by the Boolean equations. The solution is, then, obtained from the successive substitutions of the Boolean equations, which is equivalent to the attaching processes of interrelated system's fault tree to a given fault tree. The solution for three interrelated systems and their independent fault tree structures are given as an example.     

Reliability assessment of small sample based on multiple source information fusion and fuzzy fault tree

Aiming at the problems that was difficult to describe the relationship between events by the Boolean logic of conventional fault tree analysis (FTA), and the insufficient of getting reliability data in the practical application, a new polymorphic system reliability assessment method using small sample based on multiple source information fusion method and T-S fuzzy faulty tree was proposed. Based on T-S fuzzy fault tree, correlation multiple source information fusion method was applied to the confirmation of the basic event reliability. Meanwhile, in order to avoid the influence of unusable data, t-test was proposed to check the compatibility between prior information and sample information, which solved the problem that the reliability of the bottom event was difficult to be determined in the small sample system, and the prediction accuracy was improved. The proposed method was validated by using main hoisting mechanism of ladle crane. The results demonstrate that the proposed method can be applied to hoisting mechanism reliability assessment of ladle crane commendably, and the technique provides support and reference to improve the reliability of hoisting mechanism.     

The Minimum Cut Sets of System Fault Based on Oriented Matrix Analysis

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Self-checking logic design for FPGA implementation

Field programmable gate arrays (FPGAs) are being increasingly used in many systems including intelligent instrumentation. A synthesis algorithm for generating self-checking combinational logic for implementation on look-up table based FPGAs is presented. The algorithm maps Boolean functions into FPGAs such that self-checking features are automatically incorporated into designs, allowing on-line detection of faults in the combinational function block within any configurable logic block of an FPGA and on the interconnect lines that connect these blocks. This is accomplished by utilizing two types of cells, a functional cell and a checker cell, that generate complementary outputs during normal operation, and outputs of the same value in the presence of a fault. If a fault occurs in any intermediate functional cell, it is automatically propagated to the primary outputs. A checker cell is then used to verify the correctness of the final outputs, thus allowing self-checking.     

应用Petri网改进基于故障树的诊断方法

故障树是表示故障发生和故障传播关系的一种逻辑模型,基于故障树诊断方法的广泛应用由于实际故障树分析过程的ＮＰ困难问题而受到妨碍。而Ｐｅｔｉｒ网是一种特殊的有向网,适合于描述故障的传播关系。本文提出了两种基于Ｐｅｔｒｉ网的改进方法,与下行法相比,用该方法寻找最小割集和最小路集能有效地节省上计算时间,提高推理速度和效率;最后还应用Ｐｉｔｒｉ网的状态方程分析方法提出了基于Ｐｅｔｒｉ网的故障监测和诊断方法。     

Novel Quantum Algorithms to Minimize Switching Functions Based on Graph Partitions

After Google reported its realization of quantum supremacy, Solving the classical problems with quantum computing is becoming a valuable research topic. Switching function minimization is an important problem in Electronic Design Automation (EDA) and logic synthesis, most of the solutions are based on heuristic algorithms with a classical computer, it is a good practice to solve this problem with a quantum processer. In this paper, we introduce a new hybrid classic quantum algorithm using Grover’s algorithm and symmetric functions to minimize small Disjoint Sum of Product (DSOP) and Sum of Product (SOP) for Boolean switching functions. Our method is based on graph partitions for arbitrary graphs to regular graphs, which can be solved by a Grover-based quantum searching algorithm we proposed. The Oracle for this quantum algorithm is built from Boolean symmetric functions and implemented with Lattice diagrams. It is shown analytically and verified by simulations on a quantum simulator that our methods can find all solutions to these problems.     

The application of Petri nets to failure analysis

Unlike the technique of fault tree analysis that has been widely applied to system failure analysis in reliability engineering, this study presents a Petri net approach to failure analysis. It is essentially a graphical method for describing relations between conditions and events. The use of Petri nets in failure analysis enables to replace logic gate functions in fault trees, efficiently obtain minimal cut sets, and absorb models. It is demonstrated that for failure analysis Petri nets are more efficient than fault trees. In addition, this study devises an alternative; namely, a trapezoidal graph method in order to account for failure scenarios. Examples validate this novel method in dealing with failure analysis.     

Space-variant optical logic operations based on operation-dependent encoding method

We propose performing space-variant optical logic operations in a space-invariant optical system by selectively assigning encoding states that are operation dependent. With this method, encoders using liquid-crystal cells and liquid-crystal light valves to perform space-variant encoding for all 16 Boolean functions are designed. Multiple-instruction-multiple-data processing can then be realized in optical logic systems.