用线性和对数特性实现中频放大电路的设计

阐述中频放大器电路的组成原理、设计方法和测试方法。整个系统的组成包括线性通道、对数通道和稳压电源三部分。线性通道中,使用高性能低噪音宽带差分放大器AD8350进行线性放大,电路输入匹配于50Ω,具有"单端-差分"转换网络,增益为18 dB,输出功率范围宽达-90~+8 dBm(1dB压缩点)。功率分配网络用于线性输出和对数放大器的输入。对数通道中,采用高动态范围宽带对数放大器AD8309作为主要部件,对数放大器输出的电压信号与输入功率的dBm值呈线性关系。该信号用以检查线性通道是否正常,并可估计整机性能。在输入功率为-68~-8 dBm时,对数放大器输出电压范围为0.19~2.06 V。     

一种带有巴伦电路的24 GHz上混频器设计

设计了一个24 GHz上变频混频器,基于吉尔伯特结构全集成了3个片上巴伦电路。采用gm/I方法协调晶体管大小为了获得较好的转换增益、隔离度与电路耗散功率。电路实现采用厦门三安0.5μm PHEMT工艺,5 V电压供电,在本振LO为0 dBm时,转换增益为9 dBm。工作在24 GHz频段时,1 dB压缩点为-20 dBm,混频器的最大输出功率为-10 dBm,射频输出端口与本振的隔离度大于32 dB,整个电路直流功耗40 mW,芯片面积为1 mm×1.3 mm。     

3 GHz CMOS低噪声放大器的优化设计

基于0.18 μm CMOS工艺,采用共源共栅源极负反馈结构,设计了一种3 GHz低噪声放大器电路.从阻抗匹配及噪声优化的角度分析了电路的性能,提出了相应的优化设计方法.仿真结果表明,该放大器具有良好的性能指标,功率增益为23.4dB,反向传输系数为-25.9 dB,噪声系数为1.1 dB,1dB压缩点为-13.05 dBm.     

一种用于固态功率放大器的ALC电路

设计了一种用于X波段固态功放的ALC电路,根据输出信号功率控制可变衰减器的衰减量,对放大器的增益和输出功率进行调节。放大器工作频率范围为8.0 GHz～8.5 GHz。在室温条件下,当输入功率在-5 dBm～+5 dBm范围变化时,在ALC电路控制下放大器输出功率稳定在13.2 dBm～13.7 dBm之间,增益波动小于0.5 dB。     

一种高线性度宽带可编程增益放大器

设计了一种应用于超宽带无线接收机的高线性度宽带可编程增益放大器(PGA),该PGA采用线性度增强型源简并结构的放大器加电阻衰减网络的结构,增益的调节分两步完成,PGA Core实现6dB增益调节步长,电阻衰减网络实现1dB增益调节步长,PGA Core电路采用线性度增强型源简并结构放大器,提高PGA的线性度。PGA采用SMIC 0.18μm混合信号CMOS工艺,1.8 V电源电压供电,仿真结果表明,该PGA增益范围-4~28dB,1dB步进,3dB带宽大于280 MHz,最大增益时输出三阶交调点(OIP3)25.7dBm,噪声系数(NF)22.24dB,总体电路消耗10.4 m A电流,芯片有效面积0.2 mm~2。     

一种超宽带低噪声放大器

提出一个共源共栅结构的超宽带低噪声放大器。该电路基于台积电0.18μmCMOS工艺,工作在3GHz～5GHz频率下,用来实现超宽带无线电。仿真结果表明,该低噪声放大器有最大13.6dB的增益。整个频段噪声系数小于1.9dB。输入和输出反射损耗都小于-11dB。一阶压缩点在-15dBm左右。功耗为18.7mW。     

L波段5W InGaP/GaAsHBT功率放大器

InGaP/GaAs HBT具有功率密度大、线性好和阈值电压一致性好等而广泛应用于无线通信终端放大器,本文基于自主HBT工艺技术,借助GaAs MMIC和辅助PCB板外匹配架构,通过选择合适的器件尺寸和偏置条件以及匹配结构,实现高性能的终端放大器。在VCC=5 V,ICC=300 mA下,频率1 59-1 62 GHz范围内,小信号增益大于39dB,输出功率大于38 dBm,附加效率大于55%,1d B压缩功率大于37dBm,1 dB压缩功率下的效率大于50%;采用PI/4QPSK调制信号,频率间隔21 6kHz和滤波器滚降系数0.35,在调制输出功率为36dBm下,其EVM指标小于5%,第一临道抑制比小于-27dBc。该放大器可应用于通信等领域。     

一款RFID低噪声放大器的设计与仿真

电子标签的广泛应用对UHF RFID(超高频射频识别)阅读器的性能提出了更高的要求.低噪声放大器能降低系统的噪声和提高接收机灵敏度,是接收系统的关键部件.设计的LNA应用于UHF RFID阅读器前端,要求工作频率为900一930MHz,噪声系数小于1dB,带内增益大于15dB以及高线性度指标包括输出1dB压缩点大于15dBm和输出三阶互调点大于30dBm.结合相关设计理论,利用安捷伦科技的E-PHEMT(增强型伪高电子迁移率晶体管)ATF54143,完成了电路设计并通过ADS2006对直流偏置、输入输出匹配以及源极加负反馈进行优化等仿真,结果表明:电路的噪声系数可达到0.54dB,功率增益高达23.4dB,输入、输出匹配良好,各种线性度指标也完全符合设计要求.     

带自适应控制的直放站线性功率放大器

线性功率放大器是CDMA直放站的核心模块.本文设计的带自适应控制的线性功放,其功率增益G为48 0.8dB,1db压缩点输出功率≥37dBm,带内渡动≤0.8dB,互调失真IMD3≤-15dBm,IMD5≤-25dBm,输入输出端口驻波比VSWR≤1.3,增益步进衰减ATT范围为31dB,自动电平控制ALC范围为20dB,符合直放站的应用要求.     

采用新型电流舵结构的增益可调UWBLNA

基于TSMC 0.18μm CMOS工艺,设计了一款工作在3 GHz⁵ GHz频段的增益可调超宽带低噪声放大器(LNA)。LNA输入级采用局部反馈的共栅结构,实现了超宽带输入匹配和良好的噪声性能;放大电路级采用提出的新型电流舵结构,实现了放大器增益连续可调;输出级采用源极跟随器,获得了良好的输出匹配。利用ADS2009进行仿真验证,结果表明,在3 GHz5 GHz频段的增益可调超宽带低噪声放大器(LNA)。LNA输入级采用局部反馈的共栅结构,实现了超宽带输入匹配和良好的噪声性能;放大电路级采用提出的新型电流舵结构,实现了放大器增益连续可调;输出级采用源极跟随器,获得了良好的输出匹配。利用ADS2009进行仿真验证,结果表明,在3 GHz⁵ GHz工作频段内,LNA获得了25 dB的增益可调范围,最高增益达到24 dB,输入端口反射系数小于-11 dB,输出端口反射系数小于-14 dB,最小噪声系数为2.3 dB,三阶交调点(IIP3)为4 dBm,在1.2 V电压下,电路功耗仅为8.8 mW。     

A CMOS low noise amplifier based on common source technique for ISM band application

In this paper a 2.45 GHz narrowband low noise amplifier (LNA) for wireless communication system is enunciated. The proposed CMOS Low Noise amplifier has been verified through cadence spectre RF simulation in standard UMC 90 nm CMOS process. The proposed LNA is designed by cascoding of two transistors; that is the common source transistor drives a common gate transistor. To achieve better power gain along with low noise figure, cascoding of two transistor and source degeneration technique is used and for low power consumption, the MOS transistors are biased in subthreshold region. At 2.45 GHz frequency, it exhibits power gain 31.53 dB. The S11, S22 and S12 of the circuit is ?9.14, ?9.22 and ?38.03 dB respectively. The 1 dB compression point of the circuit is ?16.89 dBm and IIP3 is ?5.70 dBm. The noise figure is 2.34 dB, input/output match of ?9.14 dB/?9.22 dB and power consumption 8.5 mW at 1.2 V.     

Performance comparison of a single and multiband power amplifiers using IHP 0.25 μm SIGe HBT technology

In this work, a single‐band power amplifier (PA) with a fixed‐frequency/band output matching network and multiband PA with a switch‐tuned output matching network is designed, using IHP (Innovations for High Performance), 0.25 μm‐SiGe HBT process. The behavior of the amplifiers has been optimized for 2.4 GHz (WLAN), 3.6 GHz (UWB‐WiMAX), and 5.4 GHz (WLAN) frequency bands for a higher 1‐dB compression point and efficiency. Multiband characteristics of the amplifier were obtained by using a MOS‐based switching network. Two MOS switches were used for tuning the band of the output matching network. Postlayout simulations of the multiband‐PA provided the following performance parameters: 1‐dB compression point of 25.2 dBm, gain value of 36 dB, efficiency value of 12.8% operation and maximum output power of 26.8 dBm for the 2.4 GHz WLAN band, 1‐dB compression point of 25.5 dBm, gain value of 32 dB, efficiency value of 13.3% and maximum output power of 26.6 dBm for the 3.6 GHz UWB‐WiMAX band and 1‐dB compression point of 24.8 dBm, gain value of 23 dB, efficiency value of 12.5% and maximum output power of 26.3 dBm for the 5.4 GHz WLAN band. For the fixed‐band, at 3.6 GHz, the postlayout simulations resulted the following parameters: 1‐dB compression point of 25.5 dBm, gain value of 32 dB, efficiency value of 18% and maximum output power value of 26.8 dBm. Measurement results of the single‐band PA provided the following performance parameters: 1‐dB compression point of 20.5 dBm, gain value of 23 dB and efficiency value of 7% operation for the 2.4 GHz band; 1‐dB compression point of 25.5 dBm, gain value of 31.5 dB and efficiency value of 17.5% for the 3.6 GHz band; 1‐dB compression point of 22.4 dBm, gain value of 24.4 dB and efficiency value of 9.5% for the 5.4 GHz band. Measurement results show that using multistage topologies and implementing each parasitic as part of the matching network component has provided a wider‐band operation with higher output power levels, above 25 dBm, with SiGe:C process. These results proved that the PA, with switching/tunable output matching network, provides compatible performance parameters, when compared with the fixed‐band PA. The ability of being capable of operation in different frequency bands with compatible performance parameters, when compared with fixed‐band PA, multiband PA can be realized with additional less parasitics, area, and cost advantages. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

18‐31 GHz GaN wideband low noise amplifier (LNA) using a 0.1 μm T‐gate high electron mobility transistor (HEMT) process

GaN technology has attracted main attention towards its application to high‐power amplifier. Most recently, noise performance of GaN device has also won acceptance. Compared with GaAs low noise amplifier (LNA), GaN LNA has a unique superiority on power handling. In this work, we report a wideband Silicon‐substrate GaN MMIC LNA operating in 18‐31 GHz frequency range using a commercial 0.1 μm T‐Gate high electron mobility transistor process (OMMIC D01GH). The GaN MMIC LNA has an average noise figure of 1.43 dB over the band and a minimum value of 1.27 dB at 23.2 GHz, which can compete with GaAs and InP MMIC LNA. The small‐signal gain is between 22 and 25 dB across the band, the input and output return losses of the MMIC are less than ?10 dB. The P_1dB and OIP3 are at 17 dBm and 28 dBm level. The four‐stage MMIC is 2.3 × 1.0 mm² in area and consumes 280 mW DC power. Compared with GaAs and InP LNA, the GaN MMIC LNA in this work exhibits a comparative noise figure with higher linearity and power handling ability.     

采用噪声抵消技术的高增益CMOS宽带LNA设计

设计了一种面向多频段应用的CMOS宽带低噪声放大器。采用噪声抵消技术以及局部负反馈结构,引入栅极电感补偿高频的增益损失,电路具有高增益、低噪声的特点,并且具有平坦的通带增益。设计采用UMC 0.18μm工艺,后仿真显示:在1.8 V供电电压下,LNA的直流功耗约为9.45 mW,电路的最大增益约为23 dB,3 dB频带范围为0.1 GHz¹.35 GHz,3 dB带宽内的噪声约为1.7 dB1.35 GHz,3 dB带宽内的噪声约为1.7 dB⁵ dB;在1 V供电电压下,电路依然能够保持较高的性能。     

Analysis and design of a stacked power amplifier with 196% fractional bandwidth using equivalent circuit model

Stacked structure is a good solution to overcome the low output voltage swing provided by a single device. When several devices are stacked, the bandwidth and output power are multiple times higher. This article analyzes the small‐signal voltage gain of the stacked structure, deriving the gain expression of the high‐frequency model and simplified model. Based on the specific device parameter, the different small‐signal voltage gains between the two models are compared and the designed stacked structure is proved to obtain a flat gain at low frequencies below about 3 GHz. To our best knowledge, this is the first article to analyze the gain flatness of stacked structure with two equivalent circuit models. To verify the stacked theory, a pseudomorphic high‐electron‐mobility transistor（PHEMT） power amplifier (PA) is implemented using 0.25 μm Gallium arsenide (GaAs) technology. The PA achieves an ultra‐high bandwidth of 30 MHz to 3 GHz and a linear gain of 21 dB ± 1.5 dB. At a 16‐V drain bias voltage, a saturated output power of higher than 2 W and a peak power‐added efficiency (PAE) of 44.1% are attained.     

适用于WLAN接收机的高线性电流模式混频器设计

针对无线局域网接收机对低成本和线性度的定制化需求,设计了一款适用于IEEE 802.11 b/g/n/ax标准WLAN接收机的高线性度电流模式混频器;采用零中频接收机架构,电流模式混频器的电路结构主要包括跨导级放大器,混频开关级和跨阻放大器;通过跨导级两种工作状态的转换和跨阻放大器反馈电阻的两种取值变化实现了混频器的四档增益可调;混频开关级选用双平衡无源混频电路以提供良好的线性度;为了解决零中频接收机存在的直流失调问题,加入了一种电流注入式的直流失调校准电路,进一步提高了混频器的线性度;对跨阻放大器中的跨导运算放大器电路进行优化设计以提高其带宽,使跨阻放大器的输入阻抗足够小以保证混频器的线性度;基于180 nm RF CMOS工艺,借助Cadence软件对混频器进行仿真:当本振频率为2.4GHz时,四档增益分别为38dB、32dB、27dB和21dB,中频带宽可达20MHz;噪声系数在高增益的情况下为8.46dB,输入三阶交调点在低增益的情况下可达13.72dBm;仿真结果表明,在较宽的中频带宽下,电流模式混频器取得了良好的线性度性能,满足WLAN接收机的定制化需求。     

A miniature low‐power ultra‐wideband low noise amplifier in 0.18 μm CMOS

A 0.18‐μm CMOS low‐noise amplifier (LNA) operating over the entire ultra‐wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of ?8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from ?8 to ?1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm² without RF and DC pads. The design uses only two on‐chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

Survey on parameter optimization of mobile communication band low noise amplifier design

A comparative study on recent works on low noise amplifiers (LNAs) designed to be operated at mobile communication band is performed in this article. Here, specifications of different generations of mobile communication are listed, which are considered to classify recent works on LNAs. Even though gain and noise figure (NF) are the primary parameters of LNA; other parameters like power, linearity, bandwidth, and area also get importance. Due to this, optimization techniques handpicked for all those parameters are discussed. The inverse relation between gain and NF is exploited to achieve low noise and high gain together. While increasing the gain, power consumption is increased by drain current. Each LNA is found as good in terms of gain and other parameters to satisfy the requirements. The figure of merit is opted to find the performance of each LNA, and the comparison is performed. The best parameters reported in the comparison are 31.53 dB of gain, 0.7 dB of NF, 0.03 mw of power consumption, 18.14 dBm of third‐order input intercept point (IIP3), 24 GHz bandwidth and 0.0052 mm² of area at different frequencies and technology nodes. In this survey, as per the optimized FoM for mobile communication, cross‐coupled common gate differential LNA, which was designed to be operated at 0.3 to 2.96 GHz gives better results among CMOS LNAs.     

3GHz～5GHz CMOS超宽带低噪声放大器设计

提出了一个低噪声、高线性的超宽带低噪声放大器(UWB LNA).电路由窄带PCSNIM LNA拓扑结构和并联低Q负载结构组成,采用TSMC 0.18 μm RFCMOS工艺,并在其输入输出端引入了高阶带通滤波器.仿真结果表明,在1.8V直流电压下LNA的功耗约为10.6 mW.在3 GHz～5 GHz 的超宽带频段内,...