A Power Optimized Continuous-Time ∆Σ ADC for Audio Applications

We present design considerations for low-power continuous-time modulators. Circuit design details and measurement results for a 15 bit audio modulator are given. The converter, designed in a 0.18 mum CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 muW from a 1.8 V supply. It features a third-order active-RC loop filter, a very low-power 4-bit flash quantizer, and an efficient excess-delay compensation scheme to reduce power dissipation.     

A 375-mW Quadrature Bandpass ∆Σ ADC With 8.5-MHz BW and 90-dB DR at 44 MHz

A quadrature bandpass DeltaSigma ADC for a multistandard TV tuner achieves a total dynamic range of 90 dB over an 8.5-MHz passband centered on 44 MHz while consuming 375 mW. The fourth-order continuous-time ADC uses active-RC resonators configured in a modified feedforward architecture     

A 2.5-V 14-bit, 180-mW Cascaded Σ∆ ADC for ADSL2+ Application

This paper presents a sigma-delta (SigmaDelta) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application. The core of the ADC is a cascaded 2-1-1 SigmaDelta modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2-MHz signal bandwidth, the ADC achieves a dynamic range of 86 d 15 and a peak signal-to-noise and distortion ratio of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-mum CMOS technology, in a 2.8 mm² active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.     

A 2.7-mW 2-MHz Continuous-Time Σ∆ Modulator With a Hybrid Active–Passive Loop Filter

In this paper, passive continuous-time (CT) Sigma Delta modulators are briefly reviewed and compared with conventional active CT Sigma Delta modulators. A fifth-order CT Sigma Delta modulator with a hybrid active-passive loop filter is realized with only three active integrators. The hybrid CT Sigma Delta modulator is robust to the excess loop delay, clock jitter, and RC product variations. The prototype chip is designed in a 0.25- mum CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype Sigma Delta modulator achieves a 68-dB dynamic range and a - 75 dB IM3 over a 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.     

A Design-for-Digital-Testability Circuit Structure for Σ- ∆ Modulators

A design-for-digital-testability (DfDT) switched-capacitor circuit structure for testing Sigma-Delta modulators with digital stimuli is presented to reduce the overall testing cost. In the test mode, the DfDT circuits are reconfigured as a one-bit digital-to-charge converter to accept a repetitively applied Sigma-Delta modulated bit-stream as its stimulus. The single-bit characteristic ensures that the generated stimulus is nonlinearity free. In addition, the proposed DfDT structure reuses most of the analog components in the test mode and keeps the same loads for the operational amplifiers as if they were in the normal mode. It thereby achieves many advantages including lower cost, higher fault coverage, higher measurement accuracy, and the capability of performing at-speed tests. A second-order Sigma-Delta modulator was designed and fabricated to demonstrate the effectiveness of the DfDT structure. Our experimental results show that the digital test is able to measure a harmonic distortion lower than -106 dBFS. Meanwhile, the dynamic range measured with the digital stimulus is as high as 84.4 dB at an over-sampling ratio of 128. The proposed DfDT scheme can be easily applied to other types of Sigma-Delta modulators, making them also digitally testable.     

An IF-to-Baseband Σ∆ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range

A single-bit fifth-order complex continuous-time IF-to-baseband SigmaDelta modulator for AM/FM/IBOC receivers is presented. The input IF is 10.7 MHz and the sampling frequency is 41.7 MHz. The modulator achieves a dynamic range of 118dB in AM mode (3 kHz BW), 98dB in FM mode (200 kHz BW), and 86dB in IBOC mode (500 kHz BW). The modulator's high dynamic range enables the realization of an AM radio receiver without a VGA and without an AM channel-selection filter, thereby reducing system complexity and cost. The elimination of the VGA also improves the sensitivity and the overall noise figure of the receiver. The modulator's spurious free dynamic range is 88 dB in the bandwidth from 25 to 525 kHz. The IM2 distance is 92 dB, and the IM3 distance is 91 dB. The ADC was fabricated in a one-poly five-metal 0.18-mum CMOS process with an active area of 6.0mm². It consumes 210 mW from a 1.8-V supply     

A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

A 63 dB SNR, 75-mW Bandpass RF Σ∆ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-μm SiGe BiCMOS Technology

A fourth-order continuous-time LC bandpass sigma-delta ADC is designed using a new architecture with only non-return-to-zero feedback DACs to mitigate problems associated with clock jitter, along with individual control of coefficients in the noise transfer function. The ADC performs direct digitization of RF signals around 950-MHz center frequency with a 3.8-GHz clock. The operation of the proposed ADC architecture is examined in detail and extra design parameters are introduced to enhance the operating range and improve the stability of the ADC. Measurement results of the ADC, implemented in IBM 0.25-mum SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz, while consuming 75 mW of power from plusmn1.25-V supply     

A 14 mW 2.5 MS/s 14 bit Σ∆ Modulator Using Split-Path Pseudo-Differential Amplifiers

This paper presents the design and experimental results of a 1.25 MHz signal bandwidth 14 bit CMOS SigmaDelta modulator. With our proposed switched-capacitor split-path pseudo-differential amplifiers, this modulator achieves high power efficiency, high sampling frequency, and small die area. A new signal and reference front-end sampling network eliminates the input common-mode voltage and reduces power consumption and linearity requirement of the opamp. A prototype chip has been designed and fabricated in a 0.25 mum CMOS technology with a core area of 0.27 mm². Experimental results show that an 84 dB dynamic range is achieved over a 1.25 MHz signal bandwidth when clocked at 125 MHz. The power dissipation is 14 mW at 2.4 V including on-chip voltage reference buffers.     

A 2-GS/s 6-bit self-calibrated flash ADC

A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μm CMOS.The calibration method based on DAC trimming improves the linearity and dynamic performance further.The peak DNL and INL are measured as 0.34 and 0.22 LSB,respectively.The SNDR and SFDR have achieved 36.5 and 45.9 dB,respectively,with 1.22 MHz input signal and 2 GS/s.The proposed ADC,including on-chip track-and-hold amplifiers and clock buffers,consumes 570 mW from a single 1...     

2GS/s 6-bit 自校准快闪ADC

A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μ m CMOS. The calibration method based on DAC trimming improves the linearity and dynamic performance further. The peak DNL and INL are measured as 0.34 and 0.22 LSB, respectively. The SNDR and SFDR have achieved 36.5 and 45.9 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.     

A 56 mW Continuous-Time Quadrature Cascaded Σ∆ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

A quadrature cascaded modulator with continuous-time loop filters is presented for a digital multi-stream FM radio receiver. The ADC achieves a dynamic range of 77 dB and 20 MHz bandwidth centered on an intermediate frequency of 10.5 MHz and is sampling at 340 MHz. The cascaded modulator comprises programmable analog second-order quadrature filters and a digital quadrature noise cancellation filter. The 0.5 chip in 90 nm CMOS consumes 56 mW from a 1.2 V supply.     

Generalized Comb Decimation Filters for Σ∆ A/D Converters: Analysis and Design

This paper addresses the design of generalized comb decimation filters, proposing some novel decimation schemes tailored to SigmaDelta modulators. We present a mathematical framework to optimize the proposed decimation filters in such a way as to increase the SigmaDelta quantization noise (QN) rejection around the so called folding bands, frequency intervals whose QN gets folded down to baseband because of the decimation process. Comparisons are given in terms of passband drop and selectivity with respect to classic comb filters with orders ranging from 3 to 6. As far as the practical implementation of the proposed filters is concerned, we present two different architectures, namely a recursive and a nonrecursive implementation, the latter of which constitutes the basis for realizing multiplier-less generalized comb filter (GCF) realizations. We propose a mathematical framework for evaluating the sensitivity of GCFs to the approximation of the multipliers embedded in the filter architectures. The considerations deduced from the sensitivity analysis, pave the way to an optimization algorithm useful for approximating the multipliers with power-of-2 coefficients     

A 4-GS/s 4-bit Flash ADC in 0.18- μm CMOS

A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10^-11 at 4 GS/s.     

A Subsampling Quadrature Σ∆ Modulator Based on Distributed Resonators for Use in Radio Receiver

The receiver architecture proposed in this brief seizes the subsampling properties of continuous-time sigma-delta (SigmaDelta) modulators based on distributed resonators to construct a quadrature receiver. The proposed architecture is based on a low-pass SigmaDelta modulator that subsamples an intermediate frequency signal around the sampling frequency and does not require quadrature mixers. Instead, the quadrature mixing is replaced by suitably choosing the sampling instants inside the loop. Two practical circuit implementations are proposed. The first one uses separate circuitry for the I and Q paths. The second architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The proposed modulator may be feasible for the typical IF frequencies used in cellular base stations.     

用于DTMB接收机的10bit,40MS/s,72dB SFDR流水线模数转换器

介绍了一个应用于数字电视地面多媒体广播(DTMB)接收机的10-bit,40-MS/s流水线模数转换器(ADC),通过优化各级电容大小和运算放大器电流大小,在保证电路性能的同时降低了功耗.测试结果为:在40MHz采样率,4.9MHz输入信号下,可以获得9.14bit的有效位数(ENOB),72.3dB无杂散动态范围(SFDR).电路微分非线性(DNL)的最大值为0.38LSB,积分非线性(INL)的最大值为0.51LSB.电路采用0.18μm 1P6M CMOS工艺实现,电源电压为3.3V,核心面积为1mm2,功耗为78mW.     

用于DTMB接收机的10bit,40MS/s,72dB SFDR流水线模数转换器

介绍了一个应用于数字电视地面多媒体广播(DTMB)接收机的10-bit,40-MS/s流水线模数转换器(ADC),通过优化各级电容大小和运算放大器电流大小,在保证电路性能的同时降低了功耗.测试结果为:在40MHz采样率,4.9MHz输入信号下,可以获得9.14bit的有效位数(ENOB),72.3dB无杂散动态范围(SFDR).电路微分非线性(DNL)的最大值为0.38LSB,积分非线性(INL)的最大值为0.51LSB.电路采用0.18μm 1P6M CMOS工艺实现,电源电压为3.3V,核心面积为1mm2,功耗为78mW.     

A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

This paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm², including the TI ADC core and memory.     

Multibit Σ–∆ PWM Digital Controller IC for DC–DC Converters Operating at Switching Frequencies Beyond 10 MHz

An integrated digital controller for dc-dc switch-mode power supplies (SMPS) used in portable applications is introduced. The controller has very low power consumption, fast dynamic response, and can operate at programmable constant switching frequencies exceeding 10 MHz. To achieve these characteristics, three novel functional blocks, a digital pulse-width modulator based on second-order sigma-delta concept (Sigma-Delta DPWM), dual-clocking mode compensator, and nonlinear analog-to-digital converter are combined. In steady state, to minimize power consumption, the controller is clocked at a frequency lower than SMPS switching frequency. During transients the clock rate is increased to the switching frequency improving transient response. The controller integrated circuit (IC) is fabricated in a standard 0.18-mum process and tested with a 750-mW buck converter prototype. Experimental results show the controller current consumption of 55 muA/MHz and verify closed-loop operation at programmable switching frequencies up to 12.3 MHz. Simulation results indicating that this architecture can potentially support operation at switching frequencies beyond 100 MHz are also presented.     

A Fast, Sigma–Delta (Σ∆) Boost DC–DC Converter Tolerant to Wide LC Filter Variations

Power supplies in portable electronics must adapt to their highly integrated environments and, more intrinsically, respond quickly to fast load dumps. However, frequency compensation must cater to the worst case design LC combination, be it because of tolerance and/or variable design targets, limiting speed and regulation performance to the worst-case scenario, even under best case conditions. Sigma-delta (SigmaDelta) control, which addresses this issue in buck converters, has not been able to concurrently achieve both high speed and wide LC compliance in boost converters. This paper presents a dual-loop SigmaDelta boost converter whose prototype (5 plusmn5% V, 1A) was 20% faster and at least nine times more LC compliant than its leading current-mode PWM counterpart, and this without a compensation circuit. Light load efficiency, intrinsic for battery life, was also better (2% higher at 0.5 W, 600 kHz) because of lower switching losses. The tradeoffs for these benefits were higher output ripple voltage (5 V plusmn1.7%) and lower high load efficiency (less than 1.9% lower at 5 W, 300 kHz).