General-purpose 128/spl times/128 SIMD processor array with integrated image sensor

A CMOS image sensor/processor chip fabricated in a 0.35 /spl mu/m CMOS technology is presented. The chip contains a general purpose software-programmable SIMD array of 128/spl times/128 processing elements. It executes over 20 GOPS while dissipating 240 mW of power and achieves pixel-processor density of 410 cells/mm/sup 2/. Performance and accuracy measurement results are given.     

A fully integrated 0.13-/spl mu/m CMOS mixed-signal SoC for DVD player applications

This paper describes a fully integrated single-chip CMOS mixed-signal system on a chip (SoC) for DVD player applications. It integrates one digital signal processor (DSP), two 32-bit CPUs, three dedicated processing units, a partial response maximum likelihood (PRML) read channel with an analog front end (AFE), and many other subsystems on the same die. The AFE includes a fifth-order G/sub m/-C filter and attains over 66 dB C/N overall. PR(3,4,4,3) structure is employed in the PRML read channel. Owing to the PRML signal processing and the mixed-signal system level optimization in the PRML read channel, less than 10/sup -6/ of bit-error rate (BER) is obtained for the focus offset margins over /spl plusmn/0.5 /spl mu/m. This SoC is fabricated in 0.13-/spl mu/m one-poly six-Cu CMOS technology. It contains 24 million transistors in a 63.87 mm/sup 2/ die and consumes 1.5 W at 40 MSample/s data rate, which corresponds to DVD 1.5 times playback operation mode.     

A monolithic 14 bit/20 /spl mu/s dual channel A/D converter

A 14-bit monolithic coarse-fine integration A/D converter with 20-/spl mu/s conversion time is described. The IC has internal sample-and-integrate circuits and dual-channel A/D conversion capability. Overall performance, including sample-and-integrate circuits, is 0.01% distortion and 84-dB S/N ratio. All of the analog/digital circuits for dual-channel A/D conversion are integrated on a single chip by using an advanced nitride self-aligned (advanced-NSA) process.     

An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-/spl mu/m CMOS

This paper presents architecture, circuits, and test results for a single-ended, simultaneously bidirectional interface capable of a total throughput of 8 Gb/s per pin. The interface addresses noise reduction challenges by utilizing a pseudodifferential reference with noise immunity approaching that of a fully differential reference. The transmitter supports on-chip termination, predistortion, and low-skew near-end outgoing signal echo cancellation. The receiver's sense amplifier evaluates the average of two differential input signals without use of analog components and utilizes imbalanced charge injection to compensate for offset voltages. A test chip integrated in a 0.35-/spl mu/m digital CMOS technology uses the proposed techniques to implement an 8-bit wide single-ended voltage-mode simultaneous bidirectional interface and achieves a performance of 8 Gb/s per pin.     

An 8-kbit content-addressable and reentrant memory

A 256-word/spl times/32-bit associated memory, referred to as the Content Addressable and Reentrant Memory (CARM), with a 100-ns cycle time is described. The high bit density of the device is realized by a small-size associative memory cell (30/spl times/36 /spl mu/m/SUP 2/) with 2-/spl mu/m CMOS technology, while a double-layer metallization technique, new circuits for the control-signal propagation, and a hierarchical structure for the address encoder of the chip allow fast access. This device has reentrant mode operation, where the on-chip garbage collection or data storage is accomplished conditionally. One of the practical applications of this device, a high-speed matching unit for dataflow computers, is also discussed.     

A 1-/spl mu/m Bipolar VLSI Technology

A 1-/spl mu/m VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 /spl mu/m. Both nonisolated I/sup 2/L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a seated LSI, I/sup 2/L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 /spl mu/m. Scaled SPB0400's have been fabricated that operate at clock speeds 3X higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I/sup 2/L and STL device designs. Power-delay products of 14 fJ for I/sup 2/L and 30 fJ for STL have been measured.     

A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

A 36 mm/sup 2/ graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor,a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD)vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-/spl mu/m 6-metal standard CMOS logic process.     

A pipelined temporal difference imager

A 189/spl times/182 active pixel sensor (APS) for temporal difference computation is presented. The temporal difference imager (TDI), fabricated in 0.5-/spl mu/m CMOS process, contains in-pixel storage elements for a previous image frame. Difference double-sampling circuits are used to suppress the fixed pattern noise in both images and to compute the difference between the corrected images. The pixel area occupies 25 /spl mu/m by 25 /spl mu/m (using 0.7-/spl mu/m scalable rules), with fill factor of 30%. A novel pipelined readout technique is described, which is used to improve the accuracy of the temporal difference computation. With this pipelined readout architecture, >8-bit precision for the difference image and low spatial droop across the difference image is achieved. The chip consumes 30 mW at 50 fps from a 5-V power supply.     

A 32-bit VLSI CPU chip

A fully integrated 32-bit VLSI CPU chip utilizing 1 /spl mu/m features is described. It is fabricated in an n-channel silicon gate, self-aligned technology. The chip contains about 450000 transistors and executes microinstructions at approximately one per 55 ns clock cycle. It can execute a 32-bit binary integer add in 55 ns, a 32-bit binary integer multiply in 1.8 /spl mu/s, and a 64-bit floating point multiply in 10.4 /spl mu/s. The instruction set provides the functions of an advanced mainframe CPU. Because the implementation of such a complex device poses an organizational as well as a technical challenge, the design philosophy that was adopted is summarized briefly. Careful attention was paid to designer productivity, and design flexibility and testability.     

A 1.5 V CMOS 4-bit microcomputer needs only 100 /spl mu/W

Describes a new 4-bit microcomputer fabricated using a low-power silicon gate CMOS process and working from a supply voltage down to 1.2 V. The /spl mu/C can directly drive up to seven 3:1 multiplexed LCD digits, scan up 48 keys, and perform 4-bit handshaking data transfer with external devices. 16-bit, single-word instructions and eight stack levels permit efficient use of the 640-word ROM. Operating from a 4.19 MHz crystal, the device has an instruction cycle time of 15 /spl mu/s. An operating power of 100 /spl mu/W at 1.5 W makes the chip ideal for performing control and timing functions in battery operated applications.     

A 128K word/spl times/8 bit dynamic RAM

A 1-Mb DRAM with 128K/spl times/8 bit organization is described. In designing the circuit, half V/SUB cc/ bit line precharge with dummy reverse circuits was adopted for noise reduction. The noise is estimated using a three-dimensional capacitance calculation. In realizing the chip, a 1-/spl mu/m NMOS process with double-level aluminum wiring was used.     

A 65 mW 128K EB-ROM

A low power read-only memory (128K EB-ROM) has been developed using direct electron-beam data writing and 2 /spl mu/m VLSI fabrication technology. Programming of information in the ROM is accomplished by selective use of a field oxide in place of a thin gate oxide. The memory cell array is divided into eight current discharge (CD) units. Only one of the eight CD units, which contains a selected cell, is activated by the 3-bit extra decoder. The large capacitance enlarged by the Miller effect is markedly reduced. Moreover, the total capacitance to be precharged is also reduced. High performance output buffer circuitry is adopted, which has a high logic threshold voltage. As a result, the fabricated 128K EB-ROM is capable of 65 mW power dissipation under 400 ns cycle time and 5 V DC supply voltage conditions and 200 ns access time. Memory cell and chip dimensions are 8 /spl mu/m/spl times/7.75/spl mu/m and 3.75 mm/spl times/5.5 mm, respectively.     

A self-testing 2-/spl mu/m CMOS chip set for FFT applications

A chip set for high-speed radix-2 fast Fourier transform (FFT) applications up to 512 points is described. The chip set comprises a (16+16)/spl times/(12+12)-bit complex number multiplier, and a 16-bit butterfly chip for data reordering, twiddle factor generation, and butterfly arithmetic. The chips have been implemented using a standard cell design methodology on a 2-/spl mu/m bulk CMOS process. Three chips implement a complex FFT butterfly with a throughput of 10 MHz, and are cascadable up to 512 points. The chips feature an offline self-testing capability.     

An implantable wireless bidirectional communication microstimulator for neuromuscular stimulation

This paper presents the integrated circuit design for a wireless bidirectional transmission microstimulator. This implantable device is composed of an internal radio-frequency (RF) front-end circuit, a control circuit, a stimulator, and an on-chip transmitter. A 2-MHz amplitude-shift keying modulated signal, including the power and data necessary for the implantable device, is received, and a stable 3-V dc voltage and digital data will be extracted to further execute neuromuscular stimulation. The current-mode microstimulator can produce a bidirectional output current with 8-bit resolution for stimulation. The maximum stimulation current is 1 mA while the stimulation frequency is from 20 Hz to 2 kHz and the pulsewidth of stimulation current is from 150 to 500 /spl mu/s. Furthermore, the system can acquire the biological sensing signal by means of an on-chip transmitter. Most of the signal processing circuits have been designed with low-power schemes to reduce the power consumption, and the performance is also conformed to the requirements of the microstimulator. All of the circuits except for the RF link are combined in a single chip and implemented in TSMC 0.35-/spl mu/m 2P4M standard CMOS process.     

An interpolative PCM CODEC with multiplexed digital filters

An LSI CODEC, an LSI multiplexed digital filter, and an LSI compandor are developed for telephone PCM AD/DA conversion. The total chip count is 1.56 chips per channel. The single-chip interpolative CODEC operates at a 32 kHz sampling rate with a 12-bit linear code input/output, and is implemented in a phosphorus buried emitter IIL process without the need for component value trimming. The digital filter is four-channel multiplexed for both transmitting and receiving directions. It is compactly fabricated with a combinatorial configuration in a 5 /spl mu/m NMOS process. A new word length extension technique was devised to realize an 87 dB dynamic range with the digital filter. The compandor, also fabricated in 5 /spl mu/m NMOS, is 16-channel multiplexed for both directions. All measured characteristics meet CCITT recommendations with sufficient margins. They demonstrate the inherent stability and noise immunity that can be achieved with the interpolation technique of the CODEC and the digital signal processing of the digital filter.     

A 10000 frames/s CMOS digital pixel sensor

A 352×288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-μm CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4×9.4 μm with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 μV/e^-. At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization     

A 2-/spl mu/m CMOS 8-MIPS digital processor with parallel processing capability

A 2-/spl mu/m CMOS VLSI digital signal processor (DSP) family, the SP50, is described that is capable of eight million instructions per second and up to six concurrent operations in each instruction. Two DSPs, the PCB5010 and PCB5011, have been developed. Both are based on a common architecture which contains two 16-bit data buses, and a 16/spl times/16/spl rarr/40-bit multiplier accumulator and 16-bit ALU, both with multiprecision support in hardware. Also implemented are two static data RAMs (128/spl times/16 or 256/spl times/16), a data ROM (51/spl times/16), a 15-word three-port register file, three address computation units, and five serial and parallel I/O interfaces. The data path is controlled by an orthogonal instruction set, using 40-bit microcode words. The controller contains a five-level stack and an instruction repeat register, and can have either on-chip program memory (RAM: 32/spl times/40; ROM: 987/spl times/40) or off-chip program memory (up to 64K/spl times/40). Benchmarks show a two to sixfold improvement in overall performance over its predecessors.     

A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing

A 34-million transistor stream processor system-on-chip (SoC) for signal, image, and video processing contains 80 parallel integer ALUs organized into 16 data-parallel lanes with a 5-ALU VLIW per lane, two CPU cores, and I/Os. Implemented in a 0.13 mum CMOS technology, sixteen 800 MHz data-parallel lanes combine to deliver performance of 512 8-bit GOPS or 256 16-bit GOPS, or 128 billion 16-bit multiply-accumulates per second GMACs), with a power efficiency of 82 pJ/MAC.     

CMOS image sensor with mixed-signal processor array

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.     

A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications

A self-controllable voltage level (SVL) circuit which can supply a maximum dc voltage to an active-load circuit on request or can decrease the dc voltage supplied to a load circuit in standby mode was developed. This SVL circuit can drastically reduce standby leakage power of CMOS logic circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories and registers, because such circuits fitted with SVL circuits can retain data even in the standby mode. The standby power of an 8-bit 0.13-/spl mu/m CMOS ripple carry adder (RCA) with an on-chip SVL circuit is 8.2 nW, namely, 4.0% of that of an equivalent conventional adder, while the output signal delay is 786 ps, namely, only 2.3% longer than that of the equivalent conventional adder. Moreover, the standby power of a 512-bit memory cell array incorporating an SVL circuit for a 0.13-/spl mu/m 512-bit SRAM is 69.1 nW, which is 3.9% of that of an equivalent conventional memory-cell array. The read-access time of this 0.13-/spl mu/m SRAM is 285 ps, that is, only 2 ps slower than that of the equivalent SRAM.