A CMOS temperature sensor and auto-zeroing circuit with inaccuracy of −1/+0.7 °C between −30 to 150 °C

An energy efficient complementary metal-oxide-semiconductor (CMOS) temperature sensor and signal conditioning circuit with auto zeroing technique has been enunciated in this paper. In the present study, a novel CMOS temperature sensor based on sub-threshold MOS operation has been presented, which is designed for Aerospace applications. The proposed sensor does not use bipolar junction transistor (BJT) for sensing; instead it utilizes the temperature dependency of the threshold voltage of MOSFET. The proposed temperature sensor is designed to sense −30 to 150 °C and its sensitivity is 1.4 mV/°C while the power consumption is 60 nW. The accuracy of sensor is mainly limited by offset and flicker noise (1/f) noise, which is cancel by the autozeroing circuit with the help of switch capacitor circuit. The sensor circuit is designed with biasing sub circuit for controlling the curvature correction. The proposed temperature sensor and signal conditioning are simulated in a Cadence Analog Design Environment with UMC90 nm library. The simulation result shows an inaccuracy of −1/+0.7 °C.

     

Passive element free variation aware decision circuit for 40 Gb/s CDR application

The signal integrity metrics such as jitter, noise, peak-to-peak signal swing and power dissipation play a pivotal role in determining the quality of high data rate on-chip wireline communication and a decision circuit is the most vital section of it. This article explores an area efficient 40 Gb/s configuration of passive element free current mode decision module implemented in 90 nm CMOS technology. The simulation using Cadence Virtuoso platform is carried out at a power supply of 1.2 V along with a clock frequency of 40 GHz and pseudo random bit sequence data input of (2⁷ − 1) having 1 ns bit period. The device foot print of entire arrangement is (76 × 23) µm², which reads a power dissipation, delay, PDP, peak-to-peak jitter and RMS jitter of 7.02 mW, 198.1 ps, 1.391 pJ, 58.00 ps and 13.12 ps respectively. Monte Carlo runs with ‘no skew’ and 5% process skew are performed at different corners to prove the robustness of the design. The whole circuit is finally validated at lower technology node like 28 nm UMC.

     

Design of a power efficient,high slew rate and gain boosted improved recycling folded cascode amplifier with adaptive biasing technique

This paper presents an adaptive Improved Recycling Folded Cascode (IRFC) amplifier with improved gain, high slew rate, high phase margin and reduced power consumption. The proposed design is implemented using 180 nm technology with a supply voltage of 1.8 V and a capacitive load of 1 pF. The proposed design is compared with basic two stage op-amp, cascode amplifier and conventional recycling folded cascode amplifier (RFC). Analysis demonstrates that the flexible structure of IRFC with adaptive biasing shows an improvement in gain to 87.74 dB, approximately three times enhancement in slew rate to 53.8 V/µs when compared with the design specifications. The phase margin was observed to be 64.86°. The design also reports an increase in output swing. The gain increases to 109 dB when a cascode stage is added to the IRFC structure.

     

Development of a methodology for the extraction of BSIM3v3.2.2 parameters of Ge-channel MOSFETs and estimation of analog circuit performance

We have developed an algorithm which utilizes model equations for MOSFETs to extract BSIM3v3.2.2 MOSFET model parameters of Ge-channel transistors. The model represents the entire transfer characteristics from sub-threshold to strong inversion regions and the output characteristics from linear to saturation regions thus capturing all the operating bias conditions of gate to source voltage V_GS and drain to source voltage V_DS. For extraction of various BSIM parameters, the model equations are fitted with reported experimental characteristics, and some with TCAD simulation data of Ge MOSFETs for various geometrical dimensions over a wide range of bias conditions. The algorithm used for extracting BSIM3V3.2.2 parameters by fitting BSIM3v3.2.2 model equations with experimental or simulation data is written in MATLAB code. The extracted BSIM model parameters are employed in ADS circuit simulator to reproduce the transfer characteristics of Ge MOSFETs with the same channel length and channel width of 80 nm for both high and low body bias conditions. The characteristics obtained from ADS match well with those obtained from TCAD simulation using SILVACOATLAS thereby ensuring the accuracy of our extraction methodology. The extracted set of BSIM3V3.2.2 parameters is used to generate transfer and output characteristics of Ge channel pMOSFETs at channel length of 70 nm. The extracted value of threshold voltage, bulk mobility and saturation velocity are −0.2 V, 0.18 m²/V.s and 1.2 × 10⁶ m/s, respectively. Our study reveals that various device parameters such as transconductance, intrinsic voltage gain, and cut-off frequency show a maximum value of 677 μS/μm, 2.7, and 63 GHz, respectively.

     

Design of low power,high speed 4 bit binary to Gray converter with 8 × 4 barrel shifter using nano dimensional MOS transistor for arithmetical,logical and telecommunication circuit and system application

In this work the design of 4 bit binary to Gray code converter circuit with 8 × 4 barrel shifter has been carried out. The circuit has been designed using metal oxide semiconductor (MOS) transistor. The verification of the functionality of the circuits has been performed using Tanner-SPICE software. Power consumption and speed are the major design metrics for very large scale integrated circuit. In this work the average power consumption and gate delay analysis of 4 bit binary to Gray converter with 8 × 4 barrel shifter has been carried out using nano dimensional MOS transistor having channel length of 150 nm. Power consumption, delay analysis has been carried out for different set of supply voltage. It has been observed that power consumption of the 4 bit binary to Gray converter with 8 × 4 barrel shifter has been reduced by reducing the power supply voltage V_DD. The power consumption and delay offers by the circuit is very less. At 1 V V_DD, power consumption and delay are 0.15 μW and 52.7 ps respectively. Therefore the circuit is suited for low power and high speed application in the area of arithmetical, logical and telecommunication.

     

A low power fully differential RF receiver front-end for 2.4 GHz wireless sensor networks

In this paper, a novel merged LNA-mixer denoted as LNMA is proposed. The proposed LNMA consisting of a folded cascode LNA using improved derivative superposition technique and folded double-balanced subthreshold mixer using capacitor cross-coupled common-gate transconductor and it is integrated with on-chip LC voltage controlled oscillator (LC-VCO). In LNMA, a diode and power clamp based on-chip ESD protection circuit is used to tolerate ESD current of human-body-model specifications. To evaluate its performance, it is implemented in 0.18-µm MMRF CMOS process with 1-V supply, studied through post layout simulation and compared the results with other reported works. It achieves higher conversion gain of 27 dB, lower noise figure of 9.5 dB, lower input return loss (S11) of − 20 dB, higher third-order input intercept point (IIP₃) of – 16 dBm and higher IIP₂ of + 29.9 dBm compared to the works reported in the literature. The on-chip oscillator has the lower phase noise of – 114 dBc/Hz. The proposed LNMA and the LC-VCO achieves the power consumptions of 1.6 and 1.72 mW, respectively at 1-V power supply.

     

New simulation approach for tuneable trapezoidal and rectangular piezoelectric bimorph energy harvesters

Enhancing and optimizing the power and operating frequency range of energy harvesters (EH) are important objectives in designing an energy harvester generator. The application of trapezoidal shaped piezoelectric (PZT) cantilever is one way of increasing the harvested power of energy harvesters. Finite element software was used to simulate a tuneable trapezoidal and a rectangular PZT bimorph cantilevers with similar specifications. From the new simulation approach, an open circuit voltage obtained for different resonance frequencies for both generators. The simulation results are compared with the experimental and found to be in good agreement. The results have showed an increase in power over 19 % for the trapezoidal generator over the rectangular generator for a frequency range of 38–122 Hz. The trapezoidal harvester produced maximum power of 0.272 mW at resonance frequency of 34 Hz and acceleration of 2.5 m/s².

     

A novel high-density dual threshold GNRFET SRAM design with improved stability

We propose a novel single-ended static random access memory (SRAM) design with nine graphene nanoribbon FETs (9-GNRFET) in this paper. Single-ended has an impact on density, delays, static noise margin (SNM) and power consumption. The proposed model is implemented in HSPICE as a library for 16 nm GNRFET technology. This HSPICE-compatible compact model provides accuracy while maintain compactness, and make possible efficient circuit level simulations of futuristic GNRFET-based SRAM cells design. Simulations at low supply voltage of 0.325 V have shown that proposed cell provides power saving 4.8 × as compared to a supply voltage of 0.7 V. The half-select free technique provides bit interleaving architecture, consisting of error-free operations with V_DD down to 325 mV. The proposed architecture implemented in 16 nm low leakage GNRFET technology presents the scalability of these cells near threshed voltage region, which can significantly reduce power consumptions with 0.21µW. The proposed SRAM cell design is based on simulations and results are verified on GNRFET HSPICE-compact model. The proposed cell verified under process variation, and is demonstrated with write-assist, the impact of geometrical liability and adaptive supply voltage scaling.     

An efficient energy harvesting circuit for batteryless IoT devices

A new energy harvesting circuit for battery-less IoT beacon tags is developed herein to maximize power conversion efficiency as well as high throughput power with a wide input–output range. This design energy harvest (EH) circuit incorporates a charge pump (CP) with shoot-through current suppression, a body selector circuit, a maximum power point tracking circuit (MPPT), a timing control circuit, a hysteresis control circuit and a low dropout regulator. Also in this MPPT circuit is a gated clock tuned in a self-adaptive fashion to match the input impedance of the EH circuit to the output impedance of the photovoltaic (PV) panel, thus achieving successfully maximum power point. The circuit is implemented in an integrated chip in an area of 1.2 mm² via the TSMC 0.18 process. Experiments on the chip are conducted and the results show that the input voltage range is allowed from 0.55 to 1.7 V to effectively harvest the solar power from a flexible dye-sensitized solar cell. The achieved peak power conversion efficiency (PCE) is 77% at the input power of 52 μW. For a wide range of lighting luminance (300–1300 lx,) the achieved average PCE is more than 70%. The achieved wide input–output range and the maximum throughput power of 200 μW is much larger than others reported, while the 77% of PCE is close to that best power conversion efficiency reported.

     

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 × 1.076 mm² is fabricated in a TSMC 0.18 μm CMOS 1P6M technology process.     

A class-E power amplifier with high efficiency and high power-gain for wireless sensor network

In the literature, a number of two-stage class-E power amplifiers have been reported for wireless sensor network (WSN) applications. However, they suffer from the requirement of larger silicon area, inductors with high quality factor, large number of off-chip decoupling capacitors, high input power, voltage stress handling capability and efficiency degradation due to finite on-resistance and surplus capacitance of switching transistors. In order to overcome these limitations and to enhance the power added efficiency, two novel two-stage class-E power amplifiers denoted as PA1 and PA2 are proposed in this paper. Both the amplifiers use a driver amplifier with capacitive feedback and pi-matching at the input. PA1 uses a main amplifier with negative-capacitance cascode topology. PA2 uses a diode connected NMOS auxiliary transistor with RC source degeneration in the driver amplifier, negative-capacitance cascode configuration with a parallel LC-tuning circuit in the main amplifier. To evaluate the efficacy of these circuits, the proposed power amplifiers are implemented in UMC 0.18-µm standard RFCMOS process with the supply voltage of 3.0 V and the operating frequency of 2.45 GHz and studied through post-layout simulation using Cadence Virtuoso (IC616) Analog Design Environment. From this study, it is found that the proposed power amplifiers have the power added efficiency of (45.02 %, 54.87 %), the saturated output power at 1-dB compression point (P1-dB) of (21.52 dBm, 23.17 dBm), the power gain of (27.29 dB, 28.74 dB) and the output referred intercept point (OIP3) of (19.41 dBm, 22.67 dBm), respectively. Both of these power amplifiers have higher figure of merit (FoM) of (53.80, 57.98) when compared to other reported works. It is observed that the proposed power amplifiers are suitable to operate under low input power of -8 dBm and hence it meets the requirement of WSN applications.

     

An Ultra-Low Power Area Efficient Voltage Controlled Oscillator Based on Tunable Active Inductor for Wireless Applications.

This paper presents a tunable active inductor based ultra-low power, low area voltage-controlled oscillator (VCO) in 90 nm CMOS process. In the designed VCO, the modified topology of the active inductor is employed along with tuning capability. The layoutbased simulation has been performed deeming parasitic resistances and capacitances. The designed VCO yields an oscillation frequency ranging from 1.38 GHz to 3.16 GHz with a tuning range of 78.41%, where the tuning voltage is driven from 0.4 V to −0.2 V. The power dissipation varies from 0.062 mW to 0.177 mW, and the VCO provides a differential output power of 8.34 dBm to 3.94 dBm. The phase noise varies from −71 dBc/Hz to −65.4 dBc/Hz, and the Figure of Merit (FoM) has a value of −143.09 dBc/Hz @ 2.79 GHz frequency. The process corner analysis, temperature swept analysis, and Monte Carlo analysis of the proposed VCO had been carried out for the evaluation of its compatibility for diversified environments. Furthermore, the exclusion of the MOS varactor has condensed total silicon area consumption (10.3 μm × 8.5 μm). Finally, the designed VCO's performance parameters have been compared with mentioned designs where it is demonstrated that the designed VCO outdoes the others in most cases along with outstanding outcomes of low power and low silicon area consumption.     

A miniature in-plane piezoresistive MEMS accelerometer for detection of slider off-track motion in hard disk drives

A miniature in-plane pizoresistive MEMS accelerometer was designed, fabricated and characterized for detection of slider off-track motion in hard disk drives. The structure of the accelerometer consists of a central supporting beam and two stress-magnifying sensing beams. Under geometric constraints imposed by the trailing side of a pico slider, the accelerometer design was optimized to achieve approximately pure axial deformation in the sensing beams and a maximum sensitivity with a specified natural frequency of 300 kHz. Fabricated on a silicon-on-insulator (SOI) wafer, the accelerometer with a half Wheatstone bridge was wirebonded to external pads and interfaced with an amplifier circuit on a printed circuit board (PCB). The noise level, sensitivity, nonlinearity were characterized with vibration testing on a shaker. The miniature accelerometer (1 × 0.3 × 0.3 mm³) with a weight of only 0.2 mg offers a much higher resonant frequency with a comparable sensitivity compared with those in previous work.     

A new S-shaped MEMS PZT cantilever for energy harvesting from low frequency vibrations below 30 Hz

In this paper, a new S-shaped piezoelectric PZT cantilever is microfabricated for scavenging vibration energy at low frequencies (<30 Hz) and low accelerations (<0.4g). The maximum voltage and normalized power are 42 mV and 0.31 μW g ⁻², respectively, at input acceleration of 0.06g. For acceleration above 0.06g, the vibration of PZT cantilever changes from a linear oscillation to a nonlinear impact oscillation due to the displacement constraint introduced by a mechanical stopper. Based on theoretical modeling and experimental results, the frequency broadening effect of the PZT cantilever is studied with varying stop distances and input accelerations. The operation bandwidth of the piezoelectric PZT cantilever is able to extend from 3.4 to 11.1 Hz as the stop distance reduces from 1.7 to 0.7 mm for an acceleration of 0.3g, at the expense of the voltage and normalized power at resonance decreasing from 40 to 16 mV and from 17.8 to 2.8 nW g⁻², respectively.     

Designing and analyzing of a piezoelectric energy harvester with tunable system natural frequency for WSN and biosensing applications

A new structure for PEH with actuation piezoelectric layer for shifting natural frequency of the system is proposed. Beams are consisted to be Si and AlN piezoelectric which is deposited on fixed–fixed beams that produces high stress points and generates more power in comparison to the other cantilever beam PEHs. This PEH with ability of shifting system natural frequency is designed to the size of 0.25 cm² using optimum available space. Actuation piezoelectric layers added on both sides of the beams provides possibility of continues reducing systems natural frequency to less than 10 Hz. Accomplished simulation also confirms theoretical calculation done by PDE method to estimate natural frequency of the system. The natural frequency of the system without actuation voltage is 58 Hz that with 1 g acceleration generated 4.27 V and 71 µW electrical power which can be used in WSN and biosensing applications.

     

Robust low power DC-type shift register circuit capable of compensating threshold voltage shift of oxide TFTs

This paper proposes an oxide TFT DC-type shift register that consists of eleven TFTs and one bootstrapping capacitor. The proposed circuit connects drain nodes of large size pull-up TFTs of output drivers to positive supply voltage instead of alternating clock signals for low power consumption. In addition, a robust internal inverter capable of maintaining the high voltage level of the output over the large positive threshold voltage shift by bootstrapping is implemented. For a 120 Hz Full-HD display, the SPICE simulation estimates the clock power consumption of the proposed DC-type circuit as 0.56 mW at 32 shift registers and ensures the robust operation over the wide range of threshold voltage shift from −4 V to 10 V.     

A 0.6 V 117 nW high performance energy efficient system-on-chip (SoC) CMOS temperature sensor in 0.18 µm CMOS for aerospace applications

This research article presents and describes a novel design with improved performance low power consumption threshold voltage based CMOS thermal sensor for aerospace applications. The proposed temperature sensor utilizes the change in behavior of threshold voltage of MOSFET with variation in temperature. The challenge while designing the temperature sensor was to achieve the linearize output voltage with respect to change in temperature. Process corner analysis has been done to check the robustness of the circuit while performance analysis and sensitivity of the temperature sensor have been verified in the occurrence of parasitic. The proposed temperature sensor is featured with low power consumption, less power supply voltage utilization, high performance and sensitivity with inaccuracy as low as possible. The presented temperature sensor utilizes an active area of 18 µm × 9.85 µm with 117 nW power consumption. An improved linear performance with an inaccuracy of merely − 0.01 to + 0.47 °C over a wide temperature range of − 20 to + 120 °C is presented here. The sensitivity of proposed temperature sensor is found to be as high as 0.77 mV/°C. The proposed temperature sensor is realized and tested in Cadence virtuoso mixed signal design atmosphere using 0.18 µm CMOS technology and further investigated with support of tool from Mentor graphics. The engaged area of pad-limited chip is measured to be 0.96 mm².

     

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with g_m boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.     

Current-mode circuit-level technique to design variation-aware nanoscale summing circuit for ultra-low power applications

Prodigious demand for fast performance-ultra low power electronic devices has insinuated the discovery of circuit style that promises reduced propagation delay (t _p ), as well as low power dissipation (PWR). MOS current mode logic (MCML) style has emerged as a promising logic style that offers high speed of operation at the expense of acceptable power dissipation. This paper proposes a MCML full adder which employs a load controller circuit. It compares MCML full adder with hybrid-CMOS full adder in terms of various design metrics in superthreshold as well as subthreshold regions. MCML topology with load controller offers a high speed of operation and low power dissipation in superthreshold region. Same circuit arrangement, when operated in subthreshold region also delivers higher operating speed with ultralow power dissipation compared to its hybrid-CMOS counterpart. Power dissipation analysis established MCML based full adder more robust compared to its hybrid-CMOS counterpart. In particular, MCML full adder design achieves 3.77× (2.38×) improvement in propagation delay, 10.43× (3.45×) improvement in average power dissipation, 39.43× (8.21×) lower power-delay product (PDP) and 149.07× (19.55×) improvement in energy-delay product (EDP) in superthreshold (subthreshold) regions of operation at 16-nm technology node. The above results are also validated using TSMC’s industry standard 0.18-μm technology model parameters and a similar trend is observed in the design metrics of the MCML and hybrid-CMOS full adder circuits. In addition, noise performance of the above mentioned circuits is also carried out. It is observed that the noise induced by the hybrid-CMOS full adder is about 14× to that of the MCML full adder.

     

Emission of dispersed‐type inorganic EL devices with frequency‐variable high‐voltage oscillation circuit

Dispersed‐type inorganic electroluminescent (EL) devices composed of a transparent electrode, a phosphor, a dielectric, and a back electrode were prepared under various conditions using a zinc sulfide (ZnS)‐based phosphor. Additionally, a voltage/frequency variable circuit was designed. A compact high‐voltage/frequency variable circuit including three modules for boosting, frequency conversion, and voltage conversion was designed. A 140 V_pp voltage and a frequency in the range of 270 Hz to 2.4 kHz can be controlled by this circuit. The emission has begun to be observed at a voltage about 60 V_pp and a frequency of 400 Hz, at a voltage about 40 V_pp and a frequency of 1.4 kHz, 2.4 kHz, respectively. The emission intensity increased with an increase in frequency; emission with a wavelength of 450 nm was strongly influenced by the frequency. The luminescence and the electrical properties were affected by the preparation conditions including device structures, dispersion of ZnS:Cu, and Cl particles because of the current path generated by defects in the EL cell.