Non‐linear analog circuit fault diagnosis with large change sensitivity

Large change sensitivity has been proved efficient at, but restricted to, generating a linear circuit fault dictionary. This paper discusses the extension of large change sensitivity to non‐linear analog circuit fault diagnosis. The fault dictionary is divided into d.c. and a.c. sections. In the d.c. domain, non‐linear components are approximated with piecewise linear models. By relating the operating region of each piecewise linear model to the magnitude of a single fault in a procedure termed preconditioning, it is shown that large change sensitivity can efficiently compute the response of a faulty non‐linear circuit. Results presented of an analysis of computational complexity show a significant reduction in the cost of simulating single linear resistor faults in a non‐linear circuit using this method. In addition, after establishing that the resistive portion of the circuit is fault free, a fault dictionary is constructed for dynamic components using large change sensitivity in the small signal a.c. domain. Included with a discussion on the issues of large change sensitivity based simulation‐before‐test, a small non‐linear circuit is used to demonstrate the effectiveness of the proposed fault diagnosis algorithm. Copyright © 2000 John Wiley & Sons, Ltd.     

Speed‐up and performance evaluation of piecewise‐linear DC analysis

The good convergence properties of piecewise‐linear (PWL) DC analysis have been thoroughly discussed in many papers. This paper, in turn, concentrates on the speed of PWL DC analysis, where the boundary crossing of linear regions plays a crucial role. Fast methods are presented for performing the following boundary‐crossing computations: LU‐decomposition update, matrix‐equation solution, boundary‐crossing direction, and damping‐factor determination. Special attention is given to those PWL DC analysis methods that perform PWL modelling of the non‐linear components on the fly; an adaptive method is proposed for controlling the accuracy of PWL modelling and speeding up simulation. The computational efficiency of the accelerated PWL DC analysis is discussed and compared with that of conventional, Newton–Raphson iteration‐based, DC analysis. Finally, the performance evaluation is completed with realistic simulation examples: it is demonstrated that the speed of the accelerated PWL DC analysis is comparable with that of the conventional DC analysis. Copyright © 2006 John Wiley & Sons, Ltd.     

Piecewise linear second moment statistical simulation of ICs affected by non‐linear statistical effects

This paper presents a methodology for statistical simulation of non‐linear integrated circuits affected by device mismatch. This simulation technique is aimed at helping designers maximize yield, since it can be orders of magnitude faster than other readily available methods, e.g. Monte Carlo. Statistical analysis is performed by modeling the electrical effects of tolerances by means of stochastic current or voltage sources, which depend on both device geometry and position across the die. They alter the behavior of both linear and non‐linear components according to stochastic device models, which reflect the statistical properties of circuit devices up to the second order (i.e. covariance functions). DC, AC, and transient analyses are performed by means of the stochastic modified nodal analysis, using a piecewise linear stochastic technique with respect to the stochastic sources, around a few automatically selected points. Several experimental results on significant circuits, encompassing both the analog and the digital domains, prove the effectiveness of the proposed method. Copyright © 2009 John Wiley & Sons, Ltd.     

Bifurcation analysis of a piecewise smooth system with non‐linear characteristics

In previous works, there are no results about the bifurcation analysis for a piecewise smooth system with non‐linear characteristics. The main purpose of this study is to calculate the bifurcation sets for a piecewise smooth system with non‐linear characteristics. We first propose a new method to track the bifurcation sets in the system. This method derives the composite discrete mapping, Poincaré mapping. As a result, it is possible to obtain the local bifurcation values in the parameter plane. As an illustrated example, we then apply this general methodology to the Rayleigh‐type oscillator containing a state‐ period‐dependent switch. In the circuit, we can find many subharmonic bifurcation sets including global bifurcations. We also show the bifurcation sets for the border‐collision bifurcations. Some theoretical results are verified by laboratory experiments. Copyright © 2005 John Wiley & Sons, Ltd.     

An interval algorithm for finding all solutions of non‐linear resistive circuits

In this letter, an efficient algorithm is proposed for finding all solutions of non‐linear (not piecewise‐linear) resistive circuits. This algorithm is based on interval analysis, the dual simplex method, and the contraction methods. By numerical examples, it is shown that the proposed algorithm could find all solutions of systems of 500–700 non‐linear circuit equations in acceptable computation time. Copyright © 2004 John Wiley & Sons, Ltd.     

Towards analog implementations of PWL two‐dimensional non‐linear functions

This paper deals with the circuit implementation of non‐linear algebraic bivariate functions. The synthesis procedure is based on a piecewise‐linear approximation technique and on a corresponding circuit architecture, whose basic element is a circuit block with the input/output function y(x) = max(0; x). Some known CMOS circuit structures that can be used to obtain such a block are considered, and their main advantages and drawbacks are pointed out. The static and dynamic features of both the single circuit block and the overall architecture for two‐dimensional PWL functions are illustrated by way of examples. Copyright © 2005 John Wiley & Sons, Ltd.     

On simplex‐based piecewise‐linear approximations of non‐linear mappings

Simplex‐based piecewise‐linear (PWL) approximations of non‐linear mappings are needed when the robust PWL analysis is used to directly solve non‐linear equations. This paper proposes a straightforward technique for transforming the well‐known approximations into another form. This new form is computationally more efficient, since it preserves the sparse structure of the original Jacobian matrix. Furthermore, this new form of PWL approximation explicitly relates the simplex‐based PWL analysis to the conventional formulation of the Katzenelson algorithm. The proposed transform technique is also extended to treat groupwise‐separable mappings and, finally, non‐separable but sparse mappings that arise in real‐life simulation of large electronic circuits. In this paper, all these (transformed) simplex‐based PWL approximations are compared in terms of their generality and efficiency. The computational efficiency of the PWL approximation that utilizes sparsity is validated with realistic simulations. Copyright © 2005 John Wiley & Sons, Ltd.     

An efficient algorithm for finding all DC solutions of piecewise‐linear circuits

An efficient algorithm is proposed for finding all DC solutions of transistor circuits where characteristics of transistors are represented by piecewise‐linear (PWL) convex monotone functions. This algorithm is based on a simple test (termed the linear programming, LP, test) for non‐existence of a solution to a system of PWL equations in a given region. In the conventional LP test, the system of PWL equations is transformed into an LP problem by surrounding component PWL functions by rectangles. Then the dual simplex method is applied, by which the number of pivotings per region becomes very small. In this letter, we propose a new LP test using the dual simplex method and triangles. The proposed test is not only efficient but also more powerful than the conventional test using the simplex method or rectangles. Copyright © 2008 John Wiley & Sons, Ltd.     

A unified set‐theoretic approach to the analysis of PWL resistive circuits and composite N‐ports

We consider the search for all DC solutions of resistive piecewise‐linear (PWL) circuits and the analysis of the characteristics of resistive PWL composite N‐ports. These problems are unified from a theoretical and operating point of view by introducing the so‐called N‐augmented circuit, obtained from the N‐port by closing its ports with N norators. Set‐theoretic approach is used to describe the properties of the N‐augmented circuits leading to the formulation of a general DC analysis algorithm, based on linear programming techniques. The examples at the end of the paper show some practical and efficient application of the general DC analysis algorithm. Copyright © 2010 John Wiley & Sons, Ltd.     

A method for the approximate synthesis of cellular non‐linear networks—Part 2: Circuit reduction

In this paper, we face the problem of model reduction in piecewise‐linear (PWL) approximations of non‐linear functions. The reduction procedure presented here is based on the PWL approximation method proposed in a companion paper and resorts to a strategy that exploits the orthonormality of basis functions in terms of a proper inner product. Such a procedure can be favourably applied to the synthesis of the resistive parts of cellular non‐linear networks (CNNs) to reduce the complexity of the resulting circuits. As an example, the method is applied to a case study concerning a CNN for image processing. Copyright © 2003 John Wiley & Sons, Ltd.     

Current‐mode programmable piecewise‐linear neural synapses

Cellular Neural Networks with piecewise linear connection have been proposed by several authors as a generalization of the basic paradigm, which allows for more complex functionality. None of the prototypes realized to date, however, provides for such kind of synapses. As a feasibility study, a current‐mode subthreshold CMOS piecewise‐linear synapse circuit is developed in this paper. Copyright © 2003 John Wiley & Sons, Ltd.     

Fast and accurate analysis of one‐dimensional arrays of dynamic PWL cells

This paper describes a new method for the time‐domain analysis of one‐dimensional arrays of dynamic piecewise linear cells. The method exploits the local connectivity, typical of cellular arrays, and the piecewise linear behaviour of the v–i characteristic of the non‐linear elements to obtain a piecewise analytical expression of the solution. Examples demonstrate the accuracy and the efficiency, in terms of CPU‐time, of the proposed method with respect to standard simulation tools as SPICE and the numerical integration of a system of ordinary differential equations. Copyright © 2001 John Wiley & Sons, Ltd.     

Uniform approximation of time‐invariant non‐linear systems

An Erratum has been published for this article in International Journal of Circuit Theory and Applications 2004; 32(6):633. It is shown that the elements of a large class of time‐invariant non‐linear input–output maps can be uniformly approximated arbitrarily well, over infinite time intervals, using a certain structure that can be implemented in many ways using, for example, radial basis functions, polynomial functions, piecewise linear functions, sigmoids, or combinations of these functions. For the special case in which these functions are taken to be certain polynomial functions, the input–output map of our structure is a generalized finite Volterra series. Results are given for the case in which inputs and outputs are defined on ?. The case in which inputs and outputs are defined on the half‐line ?₊ is also addressed, and in both cases inputs need not be functions that are continuous. Copyright © 2004 John Wiley & Sons, Ltd.     

Synthesis of multiport resistors with piecewise‐linear characteristics: a mixed‐signal architecture

Non‐linear multiport resistors are the main ingredients in the synthesis of non‐linear circuits. Recently, a particular PWL representation has been proposed as a generic design platform (IEEE Trans. Circuits Syst.‐I 2002; 49 :1138–1149). In this paper, we present a mixed‐signal circuit architecture, based on standard modules, that allows the electronic integration of non‐linear multiport resistors using the mentioned PWL structure. The proposed architecture is fully programmable so that the unit can implement any user‐defined non‐linearity. Moreover, it is modular: an increment in the number of input variables can be accommodated through the addition of an equal number of input modules. Copyright © 2005 John Wiley & Sons, Ltd.     

A novel empirical study of the two‐dimensional non‐linear drain‐current behaviour in sub‐micrometre MOS transistors

This paper presents a simple, quasi‐static, non‐linear (saturated mode) NMOS drain‐current model for Volterra‐series analysis. The model is based on a linear transconductance, a linear drain‐source conductance and a purely non‐linear drain‐source current generator. The drain‐current dependency on both drain‐source and gate‐source voltages is included. Model parameters are then extracted from direct numerical differentiation of DC I/V measurements performed on a 160 × 0.25 µm NMOS device. This paper presents the Volterra analysis of this model, including algebraic expressions for intercept points and output spectrum. The model has been verified by comparing measured two‐tone iIP₂ and iIP₃ with the corresponding model predictions over a wide range of bias points. The correspondence between the modelled and measured response is good. Copyright © 2005 John Wiley & Sons, Ltd.     

A procedure for the computation of accurate PWL approximations of non‐linear dynamical systems

In this paper we propose a variational method to find out piecewise‐linear (PWL) approximations of non‐linear dynamical systems in view of their circuit implementations. The method is based on some significant trajectories of the dynamical system and provides reasonably accurate PWL approximations with a relatively low number of parameters. The effectiveness of the method is validated by applying it to the approximation of limit cycles (both stable and unstable) in the Bautin system. Copyright © 2006 John Wiley & Sons, Ltd.     

Non‐invasive chaos control of DC–DC converter and its optimization

The frequency‐domain‐based realization condition related to a novel non‐invasive chaos control is presented in this paper. According to the common piecewise‐linear characteristics of PWM‐controlled DC–DC converter system, a general expression for its Jacobian matrix is derived for optimizing the control parameters of the proposed non‐invasive chaos control. The relevant simulation and experiment results about the application of the chaos control to a voltage‐mode Buck converter are given, which confirm the feasibility of the parameter‐optimization method and the validity of the proposed non‐invasive chaos control. Copyright © 2010 John Wiley & Sons, Ltd.     

A combined approach for the identification of continuous non‐linear systems

The identification of a non‐linear continuous output‐only system from a time series is considered for the case that the functional form of the model is not known beforehand. To estimate both functions and parameters, a combination of non‐parametric modelling based on non‐linear regression and parametric modelling based on a multiple shooting algorithm is proposed. This strategy to determine non‐linear differential equations is exemplified on experimental data from a chaotic circuit where an accurate reconstruction of the observed attractor is obtained. Copyright © 2003 John Wiley & Sons, Ltd.     

Study of a DC voltage equalizing circuit and a zero‐sequence voltage control method for a diode‐clamped linear amplifier

2,3 This paper proposes a DC voltage equalizing circuit for a diode‐clamped linear amplifier (DCLA). The DCLA consists of series‐connected complementary MOSFETs and diode clamping circuits, with an experimental efficiency as high as 90% without switching operation. The DCLA requires a DC voltage equalizing circuit to divide the DC voltage into several levels. The proposed DC voltage equalizing circuit allows the use of a diode rectifier with a smoothing capacitor as a power supply for the DCLA. Zero‐sequence voltage control is proposed to improve the efficiency of the DCLA. As a result, a prototype 12‐series DCLA demonstrates an experimental efficiency as high as 94.7%. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 179(2): 55–63, 2012; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21131     

A systematic method for the development of a three‐phase transformer non‐linear model

In this work, a novel three‐phase transformer non‐linear model is developed. The proposed model takes into account the magnetic core topology and the windings connections. The non‐linear characteristic curve of the core material is introduced by its magnetization curve or by its hysteresis loop using the mathematical hysteresis model proposed by Tellinen or the macroscopic hysteresis model proposed by Jiles–Atherton. The eddy currents effects are included through non‐linear resistors using Bertotti's work. The proposed model presents several advantages. An incremental linear circuit, having the same topology with the magnetic circuit of the core, is used in order to directly write the differential equations of the magnetic part of the transformer. The matrix L _d that describes the coupling between the windings of the transformer is systematically derived. The electrical equations of the transformer can be easily written for any possible connection of the primary and secondary windings using the unconnected windings equations and transformation matrices. The proposed methods for the calculation of the coupling between the windings, the representation of the eddy currents and the inclusion of the core material characteristic curve can be used to develop a transformer model appropriate for the EMTP/ATP‐type programs. Copyright © 2009 John Wiley & Sons, Ltd.