A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators

A low-voltage fourth-order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled inductors, thus providing bandwidth tuning with small passband ripple. Each resonator is built using on-chip spiral inductors and accumulation-mode pMOS capacitors to provide center frequency tuning. The filter has been implemented in HP 0.5-/spl mu/m CMOS process and occupies an area of 0.15 mm/sup 2/. It consumes 16 mA from a single 2.7-V supply at a center frequency of 1.84 GHz and a bandwidth of 80 MHz while providing a passband gain of 9 dB and more than 30 dB of image attenuation for an IF frequency of 100 MHz. The measured output 1-dB compression point and output noise power spectral densities are -16 dBm and -137 dBm/Hz, respectively. This results in a 1-dB compression dynamic range of 42 dB. The filter minimum power supply voltage for proper operation is 2 V. The chip experimental results are in good agreement with theoretical results.     

A High Dynamic Range Programmable CMOS Front-End Filter with a Tuning Range from 1850 to 2400 MHz

This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, –25 dBm in-band 1-dB input compression point (ICP) and 0 dBm out-of-band ICP while drawing 26 mA from a 2.5 V supply.     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A 5-GHz highly integrated receiver front-end

In this paper a radio front-end for a IEEE 802.11a and HIPERLAN2 sliding-IF receiver is presented. The circuit, implemented in a low-cost 46-GHz-f _T silicon bipolar process, includes a variable-gain low noise amplifier and a double-balanced mixer. Thanks to monolithic LC filters and on-chip single-ended-to-differential conversion of the RF signal, the proposed solution does not require the expensive image rejection filter and an external input balun. The receiver front-end exhibits a 4.3-dB noise figure and a power gain of 21 dB, providing an image rejection ratio higher than 50 dB. By using a 1-bit gain control, it achieves an input 1-dB compression point of −11 dBm, while drawing only 22 mA from a 3-V supply voltage.     

The design of a 3-V 900-MHz CMOS bandpass amplifier

A new bandpass amplifier which performs both functions of low-noise amplifier (LNA) and bandpass filter (BPF) is proposed for the application of 900-MHz RF front-end in wireless receivers. In the proposed amplifier, the positive-feedback Q-enhancement technique is used to overcome the low-gain low-Q characteristics of the CMOS tuned amplifier. The Miller-capacitance tuning scheme is used to compensate for the process variations of center frequency. Using the high-Q bandpass amplifier in the receivers, the conventional bulky off-chip filter is not required. An experimental chip fabricated by 0.8-μm N-well double-poly-double-metal CMOS technology occupies 2.6×2.0 mm² chip area. Under a 3 V supply voltage, the measured quality factor is tunable between 2.2 and 44. When the quality factor is tuned at Q=30, the measured center frequency of the amplifier is tunable between 869-893 MHz with power gain 17 dB, noise figure 6.0 dB, output 1 dB compression point at -30 dBm, third-order input intercept point at -14 dBm, and power dissipation 78 mW     

A compact LTCC-based Ku-band transmitter module

Presents design, implementation, and measurement of a three-dimensional (3-D)-deployed RF front-end system-on-package (SOP) in a standard multi-layer low temperature co-fired ceramic (LTCC) technology. A compact 14 GHz GaAs MESFET-based transmitter module integrated with an embedded bandpass filter was built on LTCC 951AT tapes. The up-converter MMIC integrated with a voltage controlled oscillator (VCO) exhibits a measured up-conversion gain of 15 dB and an IIP3 of 15 dBm, while the power amplifier (PA) MMIC shows a measured gain of 31 dB and a 1-dB compression output power of 26 dBm at 14 GHz. Both MMICs were integrated on a compact LTCC module where an embedded front-end band pass filter (BPF) with a measured insertion loss of 3 dB at 14.25 GHz was integrated. The transmitter module is compact in size (400 /spl times/ 310 /spl times/ 35.2 mil/sup 3/), however it demonstrated an overall up-conversion gain of 41 dB, and available data rate of 32 Mbps with adjacent channel power ratio (ACPR) of 42 dB. These results suggest the feasibility of building highly SOP integrated RF front ends for microwave and millimeter wave applications.     

Low-power-consumption and high-gain CMOS distributed amplifiers using cascade of inductively coupled common-source gain cells for UWB systems

A distributed amplifier with new cascade inductively coupled common-source gain-cell configuration is presented. Compared with other existing gain-cell configurations, the proposed cascade common-source gain cell can provide much higher transconductance and, hence, gain. The new distributed amplifier using the proposed gain-cell configuration, fabricated via a TSMC 0.18-/spl mu/m CMOS process, achieves an average power gain of around 10 dB, input match of less than -20 dB, and noise figure of 3.3-6.1 dB with a power consumption of only 19.6 mW over the entire ultra-wideband (UWB) band of 3.1-10.6 GHz. This is the lowest power consumption ever reported for fabricated CMOS distributed amplifiers operating over the whole UWB band. In the high-gain operating mode that consumes 100 mW, the new CMOS distributed amplifier provides an unprecedented power gain of 16 dB with 3.2-6-dB noise figure over the UWB range.     

A BiCMOS Ultra-Wideband 3.1–10.6-GHz Front-End

This paper presents a direct-conversion receiver for FCC-compliant ultra-wideband (UWB) Gaussian-shaped pulses that are transmitted in one of fourteen 500-MHz-wide channels within the 3.1–10.6-GHz band. The receiver is fabricated in 0.18-$mu$m SiGe BiCMOS. The packaged chip consists of an unmatched wideband low-noise amplifier (LNA), filter, phase-splitter, 5-GHz ISM band switchable notch filter, 3.1–10.6-GHz local oscillator (LO) amplifiers, mixers, and baseband channel-select filters/buffers. The required quadrature single-ended LO signals are generated externally. The average conversion gain and input$P_1 dB$are 32 dB and$-$41 dBm, respectively. The unmatched LNA provides a system noise figure of 3.3 to 5 dB over the entire band. The chip draws 30 mA from 1.8 V. To verify the unmatched LNA's performance in a complete system, wireless testing of the front-end embedded in a full receiver at 100 Mbps reveals a$10^-3$bit-error rate (BER) at$-$80 dBm sensitivity. The notch filter suppresses out-of-band interferers and reduces the effects of intermodulation products that appear in the baseband. BER improvements of an order of magnitude and greater are demonstrated with the filter.     

A single-chip GaAs MMIC image-rejection front-end for digitalEuropean cordless telecommunications

An active image-rejection filter is presented in this paper, which applies actively coupled passive resonators. The filter has very low noise and high insertion gain, which may eliminate the use of a low-noise amplifier (LNA) in front-end applications. The GaAs monolithic-microwave integrated-circuit (MMIC) chip area is 3.3 mm² . The filter has 12-dB insertion gain, 45-dB image rejection, 6.2-dB noise figure, and dissipates 4.3 mA from a 3-V supply. An MMIC mixer is also presented. The mixer applies two single-gate MESFETs on a 2.2-mm² GaAs substrate. The mixer has 2.5-dB conversion gain and better than 8-dB single-sideband (SSB) noise figure with a current dissipation of 3.5 mA applying a single 5-V supply. The mixer exhibits very good local oscillator (LO)/RF and LO/IF isolation of better than 30 and 17 dB, respectively, Finally, the entire front-end, including the LNA, image rejection filter, and mixer functions is realized on a 5.7-mm ² GaAs substrate. The front-end has a conversion gain of 15 dB and an image rejection of more than 53 dB with 0-dBm LO power. The SSB noise figure is better than 6.4 dB, The total power dissipation of the front-end is 33 mW. The MMIC's are applicable as a single-block LNA and image-rejection filter, mixer, and single-block front-end in digital European cordless telecommunications. With minor modifications, the MMIC's can be applied in other wireless communication systems working around 2 GHz, e.g., GSM-1800 and GSM-1900     

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.     

An Active Recursive RF Filter in 0.35 μm BiCMOS

An active recursive filter approach is proposed for the implementaion of an inductorless, tuneable RF filter in BiCMOS. A test circuit was designed and manufactured in a 0.35 μm SiGe BiCMOS technology. In simulations, the feasibility of this type of filter was demonstrated and reasonably good performance was obtained. The simulations show a center frequency tuning range from 6 to 9.4 GHz and a noise figure of 8.8 to 10.4 dB depending on center frequency. Gain and Q-value are tunable in a wide range. Simulated IIP-3 and 1-dB compression point is ?26 and ?34 dBm respectively, simulated at the center frequency 8.5 GHz and with 15 dB gain. Measurements on the fabricated device shows a center frequency tuning range from 6.6 to 10 GHz, i.e. slightly higher center frequencies were measured than the simulated.     

具有带外抑制特性的Ka波段低功耗低噪声放大器

基于0.15μm GaAs赝配高电子迁移率晶体管(PHEMT)工艺,成功研制了一款30~34 GHz频带内具有带外抑制特性的低功耗低噪声放大器(LNA)微波单片集成电路(MMIC)。该MMIC集成了滤波器和LNA,其中滤波器采用陷波器结构,可实现较低的插入损耗和较好的带外抑制特性;LNA采用单电源和电流复用结构,实现较高的增益和较低的功耗。测试结果表明,该MMIC芯片在30~34 GHz频带内,增益大于28 dB,噪声系数小于2.8 dB,功耗小于60 mW,在17~19 GHz频带内带外抑制比小于-35 dBc。芯片尺寸为2.40 mm×1.00 mm。该LNA MMIC可应用于毫米波T/R系统中。     

A Novel 3–5 GHz Active Matched Filter for Impulse Radio Ultra-Wideband

In this letter, a novel active matched filter for UWB-IR lower band (3.1–4.85 GHz) is presented. The signal to noise ratio is improved at the output using a tapped delay line with a common source amplifier. An artificial transmission line is used for wideband impedance matching. The matched filter achieves a power gain of 9.8 dB at center frequency. Input matching is better than ${-}19$ dB and output matching is better than ${-}15$ dB. The averaged SNR improvement is 4.6 dB using peak detection. Input referred 1-dB compression point is 0.7 dBm at the center frequency. The matched filter is biased from a 1.5 V supply with a total power consumption of 38 mW.      

A fully integrated SOC for 802.11b in 0.18-/spl mu/m CMOS

A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-/spl mu/m CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range.     

A Ultra-Wideband Amplitude Modulation (AM) Detector Using Schottky Barrier Diodes Fabricated in Foundry CMOS Technology

Utility of Schottky diodes fabricated in foundry digital 130-nm CMOS technology is demonstrated by implementing an ultra-wideband (UWB) amplitude modulation detector consisting of a low-noise amplifier (LNA), a Schottky diode rectifier, and a low-pass filter. The input and output matching of the detector is better than -10 dB from 0-10.3 GHz and 0-1.7 GHz, respectively, and almost covers the entire UWB frequency band (3.1-10.6 GHz). The measured peak conversion gain is -2.2dB. The sensitivity over the band for amplitude modulation with the minimum E _b/N_o of 6 dB is between -53 and -56 dBm. The power consumption is only 8.5 mW     

应用于WiFi6的新型高线性度功率放大器设计

针对WiFi 6的设备需求,设计了一款工作在5.15 GHz～5.85 GHz的高线性度砷化镓异质结双极型晶体管射频功率放大器。为了保证大信号和高温下功率管静态工作点的稳定性,采用了一种新型有源自适应偏置电路。对射频功率检测电路进行了设计和改进,有效降低了射频系统的功耗。针对各次谐波分量产生的影响,对输出匹配网络进行了优化。仿真结果表明：该射频功率放大器芯片小信号增益达到了32.6 dB;在中心频率5.5 GHz时1 dB压缩点功率为30.4 dBm,功率附加效率超过27.9%;输出功率为26 dBm时,三阶交调失真低于-40 dBc。实测数据表明：小信号增益大于31.4 dB;5.5 GHz时1 dB压缩点功率为29.06 dBm;输出功率为26 dBm时,三阶交调失真低于-30 dBc。当输出功率为20 dBm时,二次三次谐波抑制到-30 dBc和-45 dBc。     

3．1～10．6GHz超宽带低噪声放大器的设计

基于SIMC0．18μmRFCMOS工艺技术,设计了可用于3．1—10．6GHzMB—OFDM超宽带接收机射频前端的CMOS低噪声放大器（LNA）。该LNA采用三级结构：第一级是共栅放大器,主要用来进行输入端的匹配;第二级是共源共栅放大器,用来在低频段提供较高的增益;第三级依然为共源共栅结构,用来在高频段提供较高的增益,从而补偿整个频带的增益使得增益平坦度更好。仿真结果表明：在电源电压为1．8v的条件下,所设计的LNA在3．1～10．6GHz的频带范围内增益（521）为20dB左右,具有很好的增益平坦性f±0．4dB）,回波损耗S11、S22均小于-10dB,噪声系数为4．5dB左右,IIP3为-5dBm,PIdB为0dBm。     

A 4-91-GHz traveling-wave amplifier in a standard 0.12-/spl mu/m SOI CMOS microprocessor technology

This paper presents five-stage and seven-stage traveling-wave amplifiers (TWA) in a 0.12-/spl mu/m SOI CMOS technology. The five-stage TWA has a 4-91-GHz bandpass frequency with a gain of 5 dB. The seven-stage TWA has a 5-86-GHz bandpass frequency with a gain of 9 dB. The seven-stage TWA has a measured 18-GHz noise figure, output 1-dB compression point, and output third-order intercept point of 5.5 dB, 10 dBm, and 15.5 dBm, respectively. The power consumption is 90 and 130 mW for the five-stage and seven-stage TWA, respectively, at a voltage power supply of 2.6 V. The chips occupy an area of less than 0.82 and 1 mm for the five-stage and seven-stage TWA, respectively.     

A 0.18μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier (LNA) is designed for the impulse radio uitra-wideband (IR-UWB) system. The gain-flatten technique is adopted in this UWB LNA. Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product (GBW). Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations. The prototype is fabricated in the SMIC 0.18 μm RF CMOS process. Measurement results show a 3-dB gain bandwidth of 2.4-5.5 GHz with a maximum power gain of 13.2 dB. The excellent gain flatness is achieved with ±0.45 dB gain fluctuations across 3-5 GHz and the minimum noise figure (NF) is 3.2 dB over 2.5-5 GHz. This circuit also shows an excellent input matching characteristic with the measured S11 below-13 dB over 2.9-5.4 GHz. The input-referred 1-dB compression point (IPldB) is -11.7 dBm at 5 GHz. The differential circuit consumes 9.6 mA current from a supply of 1.8 V.     

A silicon bipolar transmitter front-end for 802.11a and HIPERLAN2 wireless LANs

A 5-GHz transmitter front-end for 802.11a and HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-f/sub T/ silicon bipolar technology. The transmitter includes a digitally controlled linear-in-dB variable-gain up-converter and a three-stage linear power amplifier. At a 3-V supply voltage, the front-end exhibits a 23.5-dBm output 1-dB compression point, 35-dB maximum power gain, and 30-dB dynamic range. The dB-linear gain error is lower than /spl plusmn/0.8 dB. The transmitter is able to comply with the stringent error vector magnitude requirement of the standard up to a 19-dBm output power level.