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1.
The discrete Hartley transform (DHT) has proved to be a valuable tool in digital signal/image processing and communications and has also attracted research interests in many multidimensional applications. Although many fast algorithms have been developed for the calculation of one- and two-dimensional (1-D and 2-D) DHT, the development of multidimensional algorithms in three and more dimensions is still unexplored and has not been given similar attention; hence, the multidimensional Hartley transform is usually calculated through the row-column approach. However, proper multidimensional algorithms can be more efficient than the row-column method and need to be developed. Therefore, it is the aim of this paper to introduce the concept and derivation of the three-dimensional (3-D) radix-2 × 2 × 2 algorithm for fast calculation of the 3-D discrete Hartley transform. The proposed algorithm is based on the principles of the divide-and-conquer approach applied directly in 3-D. It has a simple butterfly structure and has been found to offer significant savings in arithmetic operations compared with the row-column approach based on similar algorithms  相似文献   

2.
In this paper, representations of the two-dimensional (2-D) signals are presented that reduce the computation of 2-D discrete hexagonal Fourier transforms (2-D DHFTs). The representations are based on the concept of the covering that reveals the mathematical structure of the transforms. Specifically, a set of unitary paired transforms is derived that splits the 2-D DHFT into a number of smaller one-dimensional (1-D) DFTs. Examples for the 8×4 and 16×8 hexagonal lattices are described in detail. The number of multiplications required for computing the 8×4- and 16×8-point DHFTs are equal 20 and 136, respectively. In the general N⩾8 case, the number of multiplications required to compute the 2N×N-point DHFT by the paired transforms equals N2 (log N-1)+N  相似文献   

3.
Image fiber-optic two-dimensional (2-D) parallel data links based upon optical space-code division multiple access (CDMA) is implemented and experimentally demonstrated for the first time to the authors' knowledge. In the experiment, each input 4×4 bit-plane is optically encoded by an 8×8 2-D optical orthogonal signature pattern. The encoded bit-planes are spatially multiplexed, and it is transmitted through a 16 m-long image fiber having 3×104 pixels. Each receiver can properly recover the intended input bit-plane in the optical decoding process. This result will encourage the application of optical space-CDMA to future high-throughput 2-D parallel data links  相似文献   

4.
An integrated 3-D guided-free-space four-stage optoelectronic fan-out (6×6, 2×6, 6×6: and 2×6) interconnect using wavelength division multiplexing (WDM) is proposed and then demonstrated together with 40 (2×4×5) 3-D optoelectronic fan-outs using space division demultiplexing (SDDM). This channel separation is one order of magnitude smaller than that using wavelength-selective detecting techniques in WDM. A signal to noise ratio of 57 dB is experimentally determined, with two channel 40 (2×4×5) fan-outs having a channel separation of 600 μm in SDDM. The interconnection scheme presented herein allows each pixel in a transmitting plane to communicate simultaneously and reconfigurably with many pixels in the subsequent planes in a truly 3-D feature. This system can utilize vertical cavity surface emitting laser diodes, photo detecting planes, and planar compact guided-free-space fan-out interconnects, allowing compact multistage integration. By using 2-D spatially separated or multiplexed hologram arrays on a thin light guiding plate, the interconnection capability is greatly enhanced as compared to other techniques. This novel optoelectronic interconnect technology may have widespread applications in microelectronic systems and fiber-optic communication networks  相似文献   

5.
The authors present an efficient algorithm for the computation of the 4×4 discrete cosine transform (DCT). The algorithm is based on the decomposition of the 4×4 DCT into four 4-point 1-D DCTs. Thus, only 1-D transformations and some additions are required. It is shown that the proposed algorithm requires only 16 multiplications, which is half the number needed for the conventional row-column method. Since the 2m×2m DCT can be computed using the 4×4 DCT recursively for any m, the proposed algorithm leads to a fast algorithm for the computation of the 2-D DCT  相似文献   

6.
A fully integrated 2-D linear filter including a line buffer for a 7×7 kernel is presented. To run the filter in real time at video clock frequencies, an array of pipelined carry-save adders was used as a very fast arithmetic unit. The filter chip contains 292451 transistors on a silicon area of 135 mm2. The maximum clock frequency under worst-case conditions for technology and temperature was simulated to be 20 MHz. The main blocks are designed as independent parameterizable modules. The line buffer and the arithmetic unit are available as macros in a standard cell library for semicustom design. With these macros a semicustom chip for image enhancement in a X-ray system was produced. This chip works with a system frequency of 13 MHz. The line buffer module is used in another full-custom image processing chip-a two-dimensional rank order filter with a kernel size of also 7×7. This chip contains more than 300000 transistors on a silicon area of 103 mm2. In this case the module containing the 1-D FIR (finite impulse response) filters is replaced by additional pixel delays and a sorter module. Simulations have shown that the chip could work with clock frequencies up to 20 MHz  相似文献   

7.
Two-dimensional (2-D) filters for video signal processing typically operate at high uniform sampling rates and require very large delay-line (DL) memory blocks. By employing 2-D multirate signal processing techniques to reduce the sampling rate, not only the DL memory blocks can be downsized to save silicon area, but also the memory access time can be increased to save power as well. This is demonstrated in this paper considering a 2-D switched-capacitor multirate image processor that realizes (2×2)nd-order recursive low-pass and high-pass filtering functions employing half of the storage cells that would be needed in a nonmultirate system. Only one type of operational transconductance amplifier with 1-mS transconductance and 120-MHz unity gain bandwidth is needed for both the vertical filter and associated DL memory blocks and the horizontal decimating filter. Fully differential circuit techniques are employed to increase immunity to charge feedthrough injection in the analog storage cells. The complete system has been implemented in a CMOS 1.0-μm double-poly technology. The core active area is only 2.5×3.0 mm2, and at 5-V supply and 18-MHz sampling it dissipates 85 mW  相似文献   

8.
A VLSI architecture for the on-chip realization of a first-order two-dimensional (2-D) or three-dimensional (3-D) infinte impulse response (IIR) fully multiplexed frequency-planar filter module (FMFPM) is proposed. Such filter modules may be used in 3-D video processing and 2-D/3-D plane-wave filtering using sensor arrays. The proposed FMFPM can potentially be used as a 2-D/3-D IIR building block circuit for the on-chip realization of second- (or higher) order frequency-planar filters, 3-D IIR beam filters, 2-D IIR fan filter banks and 3-D IIR cone filter banks.  相似文献   

9.
The singular value decomposition (SVD) of complex matrices is computed in a highly parallel fashion on a square array of processors using Kogbetliantz's analog of Jacobi's eigenvalue decomposition method. To gain further speed, new algorithms for the basic SVD operations are proposed and their implementation as specialized processors is presented. The algorithms are 3-D and 4-D extensions of the CORDIC algorithm for plane rotations. When these extensions are used in concert with an additive decomposition of 2×2 complex matrices, which enhances parallelism, and with low resolution rotations early on in the SVD process, which reduce operation count, a fivefold speedup can be achieved over the fastest alternative approach  相似文献   

10.
A two-dimensional (2-D) multiple invariance technique for computing signal subspaces for uniform rectangular arrays (URAs) of size M×N sensors is introduced. The method is based on a multiple maximum overlap configuration of the sensors in the array with m×n subarrays of (M-m+1)×(N-n+1) sensors each. We exploit the fact that the stacked subspace of the subarray sensor output signals admits a two-level equirotational stack parametrization. We introduce a TLS-type algorithm for estimating the parameters of this equirotational stack subspace model. Based on this method of equirotational stack subspace fitting, the overall array signal subspace can be estimated with a much higher accuracy than with conventional unstructured SVD and TLS techniques. Detailed experiments validate the theoretical results. We propose a variant of 2-D ESPRIT based on equirotational stack subspace fitting. This 2-D equirotational stack ESPRIT (2-D ES-ESPRIT) algorithm clearly outperforms conventional unstructured variants of 2-D ESPRIT. A detailed comparison with 2-D unitary ESPRIT is presented  相似文献   

11.
A new fast algorithm for the type-II two-dimensional (2-D) discrete cosine transform (DCT) is presented. It shows that the 2-D DCT can be decomposed into cosine-cosine, cosine-sine, sine-cosine, and sine-sine sequences that can be further decomposed into a number of similar sequences. Compared with other reported algorithms, the proposed one achieves savings on the number of arithmetic operations and has a recursive computational structure that leads to a simplification of the input/output indexing process. Furthermore, the new algorithm supports transform sizes (p1*2m1)×(p2*2 m2), where p1 and p2 are arbitrarily odd integers, which provides a wider range of choices on transform sizes for various applications  相似文献   

12.
The factorability of one-dimensional (1-D) FIR lossless transfer matrices [1] in terms of Givens rotations produces the parameters that can be used for an optimal design of filter banks with prespecified filtering characteristics. Two dimensional (2-D) FIR lossless systems behave quite differently, however. Venkataraman-Levy [2] and Basu-Choi-Chiang [3] have constructed 2-D FIR paraunitary matrices of McMillan degrees (2,2) that are not factorable. Because of the state-space realization used in the construction, they are floating-point approximations, and they do not produce explicit parametrizations that can be used for optimal design process. In this paper, we formulate the lossless condition and nonfactorability condition of a 2-D FIR paraunitary matrix using multivariate polynomials in the coefficients. The resulting polynomial system can be explicitly solved with Gröbner bases. By studying the polynomial system, we obtain a continuous one parameter family of 2-D 2×2 non-factorable paraunitary matrices. As an example, we get a closed-form expression for a 2-D 2×2 paraunitary matrix that is not factorable into rotations and delays.  相似文献   

13.
We present an analysis of a spatial smoothing scheme extended for the estimation of two-dimensional (2-D) directions of arrival (DOAs) of coherent signals using a uniform rectangular array. The uniform rectangular array is divided into overlapping rectangular subarrays by the extended scheme, which is referred to as the 2-D spatial smoothing scheme. The analysis shows that when the extended preprocessing scheme is used in conjunction with the eigenstructure technique, the size of the subarrays should be at least (K+1)×(K+1), and the number of the subarrays must be no less than K×K in order to guarantee the “decorrelation” of κ coherent signals for all possible scenarios. The minimum size of the total uniform rectangular array is thus shown to be 2K×2K. Instead of using a uniform rectangular array, a minimal subarray structure incorporated with a minimal subarray grouping is also devised for resolving the 2-D DOAs of K coherent signals. The number of sensor elements of the minimal total array is then (K2+4K-2) instead of 4K2  相似文献   

14.
We present a detailed analysis on 2-D (4 × 4 square-lattice) antiguided vertical-cavity surface-emitting laser (VCSEL) arrays based on the effective-index model. The calculation shows that the array can operate under 2-D resonant coupling, provided that the resonance condition in both the horizontal and vertical directions is satisfied. Consequently, the resonant-mode edge radiation loss is inversely proportional to the number of array elements along one direction for a N × N array. Low-edge-loss out-of-phase and adjacent array modes are found to compete with the in-phase resonant mode. While the 3-D gain overlap is not a significant factor in modal discrimination, the introduction of inter-element loss allows the in-phase mode to exhibit the lowest threshold gain for a wide range of inter-element width, s (Δ8 ≈ 0.5 μm for 980-nm wavelength devices). The 2-D antiguided array results from shifting the cavity resonance between the element and inter-element regions and is fabricated by selective chemical etching and two-step metalorganic chemical vapor deposition growth. Diffraction-limited in-phase and out-of-phase array mode operation is observed from top-emitting arrays, depending on the inter-element width. Substrate-emitting array structures are investigated as a means to lower heating and increase the coherent output power  相似文献   

15.
Heat transfer enhancement from glass ceramic plate to water or air by agitation of the coolant near the heated surface was investigated. The experimental arrangement consisted of a ceramic plate of dimensions of 47×35×0.26 mm3, attached to a brass vessel with inner dimensions of 34×30×4 mm3. The ceramic plate was provided with a 5×5 mm2 size printed heater on the opposite side from the vessel. The temperature field across the plate was recorded by an infra-red camera. The agitation of the coolant in the vessel (air or water) was performed by a vibrating piezoelectric beam of dimensions of 26.5×12×0.6 mm3, fixed at 1 mm distance from the heated plate, or alternatively by a magnetic rod of diameter of 2.2 mm and length of 15 mm. The vibration of the beam with amplitude of some tenths of mm peak to peak at frequencies of 200 to 400 Hz caused the sinking of the peak temperature of the heater from about 90°C to 45°C in case of water as the coolant and from about 110°C to 100°C in the air. The magnetic rod, rotating in water at speed of some rounds per second lowered the heater's peak temperature from 85°C to 50 to 60°C. The ambient temperature in all experiments was 22 to 25°C and the heating power 1-2 W. The power needed for agitation was about 50 mW in case of piezoelectric vibrator and about 1 W in case of the rotating agitator drived by a fan. Using numerical simulation by ANSYS, it was demonstrated, that the temperature distribution across the plate with heater can be satisfactorily simulated using a two-dimensional (2-D) model with appropriately enhanced heat conductivity of the plate and heat transfer coefficient from the plate. For the experimental arrangement used the equivalent heat conductivity of the ceramic plate in case of agitated liquid cooling was up to 150 W/m·K and heat transfer rate up to 300 W/m 2·K  相似文献   

16.
The singular-value decomposition (SVD) technique is investigated for the realization of a general two-dimensional (2-D) linear-phase FIR filter with an arbitrary magnitude response. A parallel realization structure consisting of a number of one-dimensional (1-D) FIR subfilters is obtained by applying the SVD to the impulse response of a 2-D filter. It is shown that by using the symmetry property of the 2-D impulse response and by developing an appropriate unitary transformation, an SVD yielding linear-phase constituent 1-D filters can always be obtained so that the efficient structures of the 1-D linear-phase filters can be exploited for 2-D realization. It is shown that when the 2-D filter to be realized has some specified symmetry in its magnitude response, the proposed SVD realization would yield a magnitude characteristic with the same symmetry. An analysis is carried out to obtain tight upper bounds for the errors in the impulse response as well as in the frequency response of the realized filter. It is shown that the number of parallel sections can be reduced significantly without introducing large errors, even in the case of 2-D filters with nonsymmetric magnitude response  相似文献   

17.
The method of total least squares (TLS) phased averaging for high-performance subspace fitting in the three-dimensional (3-D) case of spectral estimation with 3-D ESPRIT is introduced and applied to the joint azimuth elevation-carrier estimation problem with two-dimensional (2-D) uniform rectangular arrays. The method is highly efficient computationally and is suitable for large arrays. Detailed computer experiments and comparisons are provided. For a 16×16 array of sensors and heavy noise, TLS phased-averaging 3-D ESPRIT exceeds the 3-D TLS unitary ESPRIT estimator by 300% in RMSE performance  相似文献   

18.
In real-time ultrasonic 3-D imaging, in addition to difficulties in fabricating and interconnecting 2-D transducer arrays with hundreds of elements, there are also challenges in acquiring and processing data from a large number of ultrasound channels. The coarray (spatial convolution of the transmit and receive arrays) can be used to find efficient array designs that capture all of the spatial frequency content (a transmit–receive element combination corresponds to a spatial frequency) with a reduced number of active channels and firing events. Eliminating the redundancies in the transmit–receive element combinations and firing events reduces the overall system complexity and improves the frame rate. Here we explore four reduced redundancy 2-D array configurations for miniature 3-D ultrasonic imaging systems. Our approach is based on 1) coarray design with reduced redundancy using different subsets of linear arrays constituting the 2-D transducer array, and 2) 3-D scanning using fan-beams (narrow in one dimension and broad in the other dimension) generated by the transmit linear arrays. We form the overall array response through coherent summation of the individual responses of each transmit–receive array pairs. We present theoretical and simulated point spread functions of the array configurations along with quantitative comparison in terms of the front-end complexity and image quality.   相似文献   

19.
A free-space optical interconnection module for the sliding Banyan (SB) multistage interconnection network is experimentally evaluated. This three-dimensional (3-D) optical shuffle topology employs a macro-lens array in a reflective architecture. Interconnections for multiple stages are interleaved across a single two-dimensional (2-D) multichip array of “smart pixels”. The experimental module implements five interleaved stages of shuffle interconnections with approximately 10 μm resolution and 10 μm registration accuracy across a 10×10 cm, 256 node, simulated optoelectronic (OE) backplane. The experiments demonstrate the use of conventional refractive optical elements to implement the required shuffle interconnection pattern in a SB network. The results suggest that this reflective 3-D shuffle interconnected SB approach may lead to ATM switching fabrics with aggregate throughputs scaleable to >1 Tb/s. Such a system could be implemented with vertical cavity surface emitting laser (VCSEL) based smart pixel OE technology  相似文献   

20.
The reported CMOS microsystem is the key element for accurate angle measurements. In combination with a permanent magnet, it is used for various wear free angular positioning control systems for automotive and industrial applications covering the full 360° range. The integrated system includes a two-dimensional (2-D) magnetic microsensor (30×30 μm2 active area), offset compensation, and signal conditioning circuitry. A novel approach for the angle calculation is presented using an on-board incremental ADC. A bitstream representing the angular position of the applied permanent magnet is provided at the system output. The system achieves a 1° angular resolution with 9 mW power consumption and a permanent magnet of 100 mT. The chip is fabricated in a generic 2-μm, double-poly, double-metal CMOS process and covers an area of 2.6×4.1 mm2  相似文献   

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