高压LDMOS器件ESD初始失效问题及其优化方向研究

研究了LDMOS在ESD放电过程中的机理及二次触发的现象,通过对LDMOS器件关键尺寸的优化设计与结构的改进,结合器件计算机辅助设计技术(TCAD)仿真、传输线脉冲(TLP)测试以及失效分析(FA)等手段,改善了其初始失效问题。同时大幅提升了LDMOS的ESD泄放能力,并进一步总结了LDMOS器件的ESD性能的优化方向。     

Analysis of the impact of process variations on clock skew

In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as V_T and I_DSS, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network     

CADless laser assisted methodologies for failure analysis and device reliability

Failure analysis techniques had been proved to be efficient to localize defects allowing root cause analysis and corrective actions at design or manufacturing level. Unfortunately, end user’s component expertise laboratories have very rarely access to the device design (CAD) they are analysing and characterizing. Electronics components come like a black box so they have to find out the information by other means to be able to link an abnormal electronic behaviour to a specific internal structure. We have proven that Laser Stimulation (LS) is a valuable technique to overcome this issue. These techniques allow a very good correlation regarding the sensitive sites on the device and the electrical functions performed. We have embedded these techniques in a specific test flow to perform CADless accurate device failure analysis and characterization of margin evolutions in operating parameters for reliability study purposes.     

Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.     

Electro Optical Terahertz Pulse Reflectometry,a non destructive technique to localize defects on various type of package

Localizing defects (particularly, dead open and resistive open defects) at package level is becoming a critical challenge for Failure Analysis Laboratories due to package miniaturisation and increased complexity. One of the well-known approaches to address this set of problems within a Device Under Test (DUT) is Time Domain Reflectometry (TDR). The main limitation of this technique is the lack of distance-to-defect accuracy and sensitivity. Electro Optical Terahertz Pulse Reflectometry (EOTPR) overcomes these limitations by using photoconductive terahertz generation and detection technology, resulting in a system with: (i) high measurement bandwidth, (ii) extremely low time base jitter, and (iii) high time base accuracy and range with greater sensitivity. In this paper we present case studies in which EOTPR has been successfully applied to a series of different device types.     

Failure Analysis enhancement by evaluating the Photoelectric Laser Stimulation impact on mixed-mode ICs

The mixed-mode ICs (Integrated Circuits), by involving multiple functions (digital, analog, RF, power) inside one device, are becoming more compact and useful. At the same time, their developments and Failure Analysis (FA) are more and more complex: test, diagnostic and defect localization steps are harder and longer in time. Each step needs to be improved as far as defect localization is concerned. Several techniques based on emission microscopy, electron beam, direct probing or laser stimulation have been developed and introduced to follow these ICs evolutions. The most recent evolution in the laser stimulation field has been the introduction of several dynamic laser stimulation techniques aimed to localize defects or weakness regions inside functional but failing ICs (environmental marginalities related to temperature, frequency, voltage, etc.). This paper deals with the use of dynamic photoelectric laser stimulation techniques applied on mixed-mode ICs where the major difficulty is due to their considerable intrinsic sensitivity. Indeed, the analog circuitry is more sensitive than the digital circuitry since a slight change in an electrical parameter can trigger a functionality failure. This property limits the defect localization because of the complex interpretation of the results, the laser stimulation mapping. We propose to help the failure analyst by coupling the dynamic laser stimulation mapping with the photoelectric impact simulations run on a previously analyzed structure. The goal is to predict and interpret the laser sensitivity mapping so to isolate the defective areas in the analog devices.     

Mismatch Modeling and Simulation—A Comprehensive Approach

This article describes a comprehensive approach to mismatch simulation and modeling as needed for integrated circuit design. Local device mismatch as well as global process variations and parameter correlations are regarded. A method for mismatch modeling based on spatial frequencies is described, which enables to overcome insufficiencies of the first order models. Measurement results are presented to demonstrate the achieved modeling precision. All models and methods mentioned here are commercially available in the simulation tool GAME (General Analysis of Mismatch Effects) which is used in the semiconductor industry since 1998.     

Characterization and modelling of ageing failures on power MOSFET devices

A method based on the failure analysis of power MOSFET devices tested under extreme electrothermal fatigue is proposed. Failure modes are associated to several structural changes that have been investigated through acoustic, electron and ion microscopy. The main aging mode is related to the exponential increase in drain resistance due to delamination at the die attach. Earlier failures are observed when very local defects due to electrical over stresses (EOS) occur at the source metallization or at the wire bonding. Aging models were elaborated to account for the die attach delamination, but are still lacking to take in account the structural evolution of the Al metallization. This new methodology, based on accelerated tests and structural observations aims at designing a new generation of power components that will be more reliable.     

A Novel Approach to Link Process Parameters to BSIM Model Parameters

In this paper, we demonstrate a methodology to link process parameters to BSIM model parameters. Here, we have combined well-known statistical methods like principal component analysis (PCA), design of experiments (DOE), and response surface methodology (RSM) to bridge the missing link between process parameters and model parameters. The proposed methodology uses the concept of a correlation matrix, which transforms the process level information to the device and circuit level information through the BSIM model parameters. The proposed methodology has been successfully implemented on an advanced CMOS process. Our results show a strong linear correlation for the data obtained from two techniques namely TCAD technique and the standard HSPICE simulation technique. In both cases the process conditions were kept identical for comparison.      

先进成像技术在失效分析中的应用

失效分析是半导体集成电路制造和高可靠应用过程的重要组成部分。本文着重讨论了失效分析中能够快速定位芯片内故障的成像技术。     

Exploitation of Laser Voltage techniques for identification and complete characterization of a scan chain transition fail issue using the second harmonic approach

This work presents a Failure Analysis case study related to a scan chain integrity issue. By using Laser Voltage Imaging and Probing (LVx) approaches, we have been able to localize a defect that was inducing a transition failure, detected during scan chain integrity test flow.Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) techniques were applied with the aim of both identifying and characterizing the first failing flip-flop of the chain, in order to understand the failure mechanism.The relatively simple Design For Test (DFT) structure of the device, made of a single scan chain to address a large area of the digital logic, and the nature of the electrical behaviour did not allow the ATPG Scan Chain diagnostic to be accurate, leaving the failure identification task to the FA engineer with the help of classical optical techniques.In this work we specially focused on the application of the two fault isolation techniques, to first, identify the failing flip-flop through dichotomy approach, investigating the macro failure mode through a second harmonic LVI analysis and finally characterizing this failure using LVP.     

Polysilicon encapsulated local oxidation

Polysilicon encapsulated local oxidation (PELOX) is proposed as an effective isolation technique that satisfied advanced device requirements without any difficult-to-control structures or processes. Simple modifications to a standard local oxidation of silicon (LOCOS) process flow minimize encroachment without introducing defects. These modifications include an HF dip after nitride patterning to form a cavity self-aligned to the nitride edge, reoxidation of exposed silicon, and polysilicon deposition to fill the cavity. Physical (scanning electron micrographs) and electrical (gate oxide quality, diode integrity, and W_eff) data which indicate that cavity reoxidation is critical to obtaining significant bird's beak reduction without defect introduction are presented     

Characterisation and modeling of mismatch in MOS transistors for precision analog design

A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.     

An Integrated CAD Methodology for Yield Enhancement of VLSI CMOS Circuits Including Statistical Device Variations

In this paper a novel CAD methodology for yield enhancement of VLSI CMOS circuits including random device variations is presented. The methodology is based on a preliminary characterization of the technological process by means of specific test chips for accurate mismatch modeling. To this purpose, a very accurate position-dependent parameter mismatch model has been formulated and extracted. Finally a CAD tool implementing this model has been developed. The tool is fully integrated in an environment of existing commercial tools and it has been experimented in the STMicroelectronics Flash Memory CAD Group.As an example of application, a bandgap reference circuit has been considered and the results obtained from simulations have been compared with experimental data. Furthermore, the methodology has been applied to the read path of a complex Flash Memory produced by STMicroelectronics, consisting of about 16,000 MOSFETs. Measurements of electrical performances have confirmed the validity of the methodology, and the accuracy of both the mismatch model and the simulation flow.     

Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point

Application requirements along with the unceasing demand for ever-higher scale of device integration, has driven technology towards an aggressive downscaling of transistor dimensions. This development is confronted with variability challenges, mainly the growing susceptibility to time-zero and time-dependent variations. To model such threats and estimate their impact on a system's operation, the reliability community has focused largely on Monte Carlo-based simulations and methodologies. When assessing yield and failure probability metrics, an essential part of the process is to accurately capture the lower tail of a distribution. Nevertheless, the incapability of widely-used Monte Carlo techniques to achieve such a task has been identified and recently, state-of-the-art methodologies focusing on a Most Probable Failure Point (MPFP) approach have been presented. However, to strictly prove the correctness of such approaches and utilize them on large scale, an examination of the concavity of the space under study is essential. To this end, we develop an MPFP methodology to estimate the failure probability of a FinFET-based SRAM cell, studying the concavity of the Static Noise Margin (SNM) while comparing the results against a Monte Carlo methodology.     

High-performance Bluetooth transmitters using two-point delta-sigma modulation

An advanced but efficient design technique has been developed for applying two-point delta-sigma modulation (TPDSM) to Bluetooth transmitters. Various design parameters, including phase noise, quantisation noise, phase-locked loop stable time and mismatch between two modulation points, can be overall taken into account to achieve the excellent performance. Experimental results have further verified the proposed design methodology.     

Synthesis of a Wireless Communication Analog Back-End Based on a Mismatch-Aware Symbolic Approach

In this paper, a methodology to automate the synthesis of an industrial-purpose analog integrated circuit, namely the back-end of an I & Q transmit interface, is presented. A good matching between both I and Q channels is desirable to ensure the correct circuit functioning.The proposed methodology combines the use of symbolic expressions with numerical approaches. While the symbolic expressions allow a fast iterative evaluation of the circuit performance, the numerical capabilities ensure a rapid optimization of the results. Unlike other approaches, the methodology uses symbolic expressions explicitly considering device mismatch, which are evaluated performing a Monte-Carlo analysis. The expressions have been obtained using an error-control process guided by the mean and standard deviation values of the circuit performance characteristics. This provides two benefits. First, smaller expressions are obtained. Second, expression evaluation is faster: smaller number of operations—symbol products and term sums—are carried out since, at each Monte-Carlo run, only those symbols related to device mismatch are to be changed, while the rest remains constant.     

Signal noise perturbation on automotive mixed-mode semiconductor device generated by graded substrate defect

The semiconductor technologies evolution allows greatly reducing noise impact on products and many structures have been created to reduce its effect. However, this paper presents the apparition of a noise issue during the production of a mixed-mode device dedicated to automotive applications. The research investigations concerned the fact that failure was not detected at test level but at customer level; therefore, it was determinant to understand the root cause of this failure mode to drive corrective actions in order to secure customer. The challenge was to analyse noise in Failure Analysis (FA) without fault spatial localization results. Indeed, Light Emission Microscopy (EMMI) and Thermal Laser Stimulation (ex: Soft Defect Localization – SDL) were unable to provide any defective area in the product. The lack of failing device identification led us to combine electrical and design analyses in order to define hypothesis on the failure origin. It was then possible to drive physical investigations through different approaches, using physical cross-section, Secondary Ion Mass Spectrometry (SIMS) and Scanning Capacitance Microscopy (SCM) techniques. Finally, the obtained complementary results will be discussed and an explanation of the failure mechanism will be presented as the root cause issue, allowing defining the defective step in production process.     

FIB与PEM联用在半导体器件失效分析中的应用

在半导体器件的失效分析中,缺陷定位是必不可少的重要环节.光发射显微镜(PEM)是IC失效定位中最有效的工具之一.PEM利用了IC器件缺陷在一定条件下的发光现象,迅速定位缺陷.而聚焦等离子束(FIB)的定点切割和沉积技术在亚微米级半导体工艺失效分析中扮演着越来越重要的作用.介绍了一种联合使用FIB和PEM进行亚微米级缺陷定位的新方法,使得一些单独使用PEM无法完成缺陷定位的案例得以成功解决.     

乳品成分近红外光谱测量系统及其可靠性热设计

论述了基于声光可调谐滤光器(AOTF)的乳品成分近红外光谱测量方法，并针对测量系统进行了可靠性热设计。通过对测量系统进行故障树分析(FTA)，从结构材料的热平衡入手针对光源部件的故障隐患进行了结构热设计；同时，针对系统核心分光器件一声光可调谐滤光器AOTF晶体采用PID调节方式的单片机系统进行了恒温控制。通过对测量系统进行优化，部件可靠性及光谱稳定性相应提高，数据表明：系统测量光谱重复性变异系数C，值由0．5％降低到0．1％。