石墨烯基电子学研究进展

综述了石墨烯晶体的能带结构和独特的电子性质,如双极性电场效应、单双层石墨烯效应、衬底效应、石墨烯纳米带(GNR)带隙等特殊效应的研究现状。介绍了石墨剥落技术、外延生长和化学气相淀积(CVD)等石墨烯材料的制备以及表征方法。列举了石墨烯在电子、显示、太阳电池、传感器和氢存储等方面的应用,如在石墨烯场效应管、石墨烯纳米带场效应管(SET)、石墨烯单电子晶体管、石墨烯金属晶体管、石墨烯基纳米电子机械系统(NEMS)、石墨烯分子开关以及石墨烯基高电子迁移率晶体管(HEMT)制备方面的应用。人们已经研究出不同栅长的n/p型顶栅石墨烯场效应管(GFET),并采用标准的S参数直接表征器件的高频性能。理论和实验表明,所有石墨烯纳米带场效应管(GNRFET)在室温下工作的前提是GNR的带宽尺寸小于10nm,并具有半导体场效应管的性能。     

Crosstalk bandwidth and stability analysis in graphene nanoribbon interconnects

Based on transmission line modeling (TLM), and using the Nichols chart, we present a bandwidth and stability analysis, together with step time responses, for coupled multilayer graphene nanoribbon (MLGNR) interconnects that is inquired for the first time. In this analysis, the dependence of the degree of crosstalk relative stability for coupled MLGNR interconnects comprising of both capacitive and mutual-inductive couplings between adjacent MLGNR has been acquired. The obtained results show that with increasing the length or decreasing the width of the MLGNRs, the stability in near-end output increases. While, any increase in the length or width of MLGNRs, decrease the stability of far-end output. Also, by increasing capacitive coupling or decreasing inductive coupling, the near-end output becomes more stable, and the far-end output becomes less stable. Moreover, any increase in the length or capacitive coupling, decreases the bandwidth, whereas any increase in the width or inductive coupling, increases the bandwidth. Finally, transient simulations with Advanced Design System (ADS) show that the model has an excellent accuracy.     

边界扫描SRAM簇板级互连测试研究

由于边界扫描结构的复杂与费用的关系,在现代电子电路中广泛使用的静态随机存取存储器还很少包含边界扫描结构.本文提出了一种能完全实现SRAM簇互连测试的方法,该方法能检测SRAM簇控制线、数据线和地址线的板级互连故障,且测试长度较短.     

抗DPA攻击的功耗平衡SRAM设计

A power balance static random-access memory(SRAM) for resistance to differential power analysis(DPA) is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanced by discharging and pre-charging the key nodes of the output circuit and adding an additional shortcircuit current path. Thus, the power consumption is constant in every read cycle. As a result, the DPA-resistant ability of the SRAM is improved. In 65 nm CMOS technology, the power balance SRAM is fully custom designed with a layout area of 5863.6 μm~2.The post-simulation results show that the normalized energy deviation(NED) and normalized standard deviation(NSD) are 0.099% and 0.04%, respectively. Compared to existing power balance circuits, the power balance ability of the proposed SRAM has improved 53%.     

SRAM供电结构与SOC芯片供电网络设计优化

主要提出了一种优化SRAM供电结构的方案——裸露Metal4的SRAM供电网络。该方案可以在不增加使用绕线资源的条件下,显著地提升SRAM的供电以及整个芯片供电网络的性能。以一款数字电视解调芯片BTV2020为例,详细叙述了传统SRAM的供电结构,提出一种SRAM的供电结构及实现方法,以及对比了优化后的SRAM供电结构与传统SRAM供电结构,所构建的供电网络的最差电源电压降。最后通过流片结果证明本方案是有效可行的。     

FPGA中通用互连结构的设计与优化

介绍了一款基于SRAM技术的FPGA电路的通用互连结构.在对其通用互连线的延时模型进行分析的基础上,提出了一种改进的互连结构.基于CSMC 0.6 μm工艺下的SPICE仿真及流片结果表明,改进后的互连结构性能提高了约10%.     

A bilayer graphene nanoribbon field-effect transistor with a dual-material gate

This paper introduces dual-material gate (DMG) configuration on a bilayer graphene nanoribbon field-effect transistor (BLGNRFET). Its device characteristics based on nonequilibrium Green׳s function (NEGF) are explored and compared with a conventional single-material gate BLGNRFET. Results reveal that an on-off ratio of up to 10 is achievable as a consequence of both higher saturation and lower leakage currents. The advantages of our proposed DMG structure mainly lie in higher carrier transport efficiency by means of enhancing initial acceleration of incoming carriers in the channel region and the suppression of short channel effects. Drain-induced barrier lowering, subthreshold swing and hot electron effect as the key short channel parameters have been improved in the DMG-based BLGNRFET.     

用0.8μm工艺技术设计的65-kb BiCMOS SRAM

设计了一种65-kb BiCMOS静态随机存取存储器(SRAM)的存储单元及其外围电路,提出了采用先进的0.8mm BiCMOS工艺,制作所设计SRAM的一些技术要点。实验结果表明,所设计的BiCMOSSRAM,其电源电压可低于3V,它既保留了CMOS SRAM低功耗、高集成密度的长处,又获得了双极型(Bipolar)电路快速、大电流驱动能力的优点,因此,特别适用于高速缓冲静态存储系统和便携式数字电子设备中。     

GNRFET双极特性及工作区域研究

石墨烯器件作为下一代纳米电子器件的有力竞争者受到广泛关注,但对其器件工作机理的研究尚不透彻。对石墨烯纳米带场效应晶体管(graphene nanoribbon field effect transistor,GNRFET)的双极特性进行了研究,分析了偏置电压对GNRFET转移特性和输出特性的影响,发现除已被关注到的栅电压外,源漏电压对GNRFET的双极特性亦有作用,并将两者综合考虑才能全面反映GNRFET的工作状态。在此基础上,进一步提出了工作区域的概念,将GNR-FET的工作区域划分为空穴导电区、电子导电区、转变区和截止区,为GNRFET器件的应用和电路设计提供指导。     

SRAM版图布局方向对产品失效率的影响

静态随机存储器(SRAM)是集成电路中重要的存储结构单元。由于其制备工艺复杂、关键尺寸较小、对设计规则的要求最为严格,因此SRAM的质量是影响芯片良率的关键因素。针对一款微控制单元(MCU)芯片的SRAM失效问题,进行逻辑地址分析确认失效位点,通过离子聚焦束(FIB)切片及扫描电子显微镜(SEM)分析造成失效的异常物理结构,结合平台同类产品的设计布局对比及生产过程中光刻工艺制程的特点,确认失效的具体原因。对可能造成失效的工艺步骤或参数设计实验验证方案,根据验证结果制定相应的改善措施,通过良率测试及SEM照片确认改善结果,优化工艺窗口。当SRAM中多晶硅线布局方向与测试单元中一致时,工艺窗口最大,良率稳定;因此在芯片设计规则中明确SRAM结构布局方向,对于保证产品的良率具有重要意义。     

A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications

In this work, a 9T subthreshold SRAM cell is proposed with the reduced leakage power and improved stability against the PVT variations. The proposed cell employs the read decoupling to improve the read stability, and the partial feedback cutting approach to control the leakage power with improved read/write ability. The incorporated stacking effect further improves the leakage power. The simulated leakage power for the proposed cell is 0.61×, 0.49×, 0.80× and 0.55×, while the read static noise margin (RSNM) is 2.5×, 1×, 1.05× and 0.96×, write static noise margin (WSNM) 0 is 1.5×, 1.8×, 1.68× and 1.9× and WSNM 1 is 0.95×, 1.2×, 1.05×, and 1.2× at 0.4 V when compared with the conventional 6T and state of arts (single ended 6T, PPN based 10T and data aware write assist (DAWA) 12T SRAM architectures) respectively. The minimum supply voltage at which this cell can successfully operate is 220 mV. A 4 Kb memory array has also been simulated using proposed cell and it consumes 0.63×, 0.67× and 0.63× less energy than 6T during read, write 1 and write 0 operations respectively for supply voltage of 0.3 V.     

Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction

This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6 T SRAM core, a resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error detection (CED) and correction capabilities are provided by connecting the NVSRAM array with a dual-rail checker; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation, such that data from the non-volatile memory element is copied back to the SRAM core. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit.     

碳基无源器件研究进展综述

碳纳米材料具有诸多独特的物理特性,如极大的热导率和载流容量.根据国际半导体技术发展路线图给出的预测,碳纳米材料可望取代传统硅和铜材料成为下一代集成电路的基础材料.本文针对碳纳米材料在无源电子器件方面的发展现状和应用前景,详细讨论了碳纳米管、石墨烯纳米带等碳基纳米互连结构的电学特性.进而,简要评述了片上电感、电容器等碳基高频无源器件,并介绍了碳纳米材料在集成电路热管理方面的应用.     

Differential absorption optical coherence tomography with strong absorption contrast agents of gold nanorods

Plasmon-resonant gold nanorods (GNRs) are demonstrated as strong absorption contrast agents for optical coherence tomography (OCT). OCT imaging of tissue phantoms doped with GNRs of different resonant wavelengths and concentrations is studied. To utilize the high absorption property of GNRs, a differential absorp-tion OCT imaging is introduced to retrieve the absorption information of GNRs from conventional backscattered signals. It is shown that the contrast of the OCT image can be enhanced significantly when the plasmon resonant wavelength of the GNRs matches the central wavelength of the OCT source.     

基于仲裁器PUF的SRAM FPGA防克隆技术设计与实现

为保护电子设备中使用的静态随机存储器(SRAM)型现场可编程门阵列(FPGA)内部电路设计不被窃取,设计了用于SRAM FPGA的防克隆电路.该电路利用FPGA制造过程中的随机误差,提取每块芯片独一无二的ID.在此ID的控制下,被保护电路只能在指定的FPGA中正常运行,而在未指定的FPGA中运行时,无法产生正确的输出,从而达到防克隆目的.防克隆电路由使用仲裁器的物理不可克隆函数(PUF)、多数表决器、运算门阵列等三部分构成,其中仲裁器PUF电路用于提取ID,多数表决器起到提高输出稳定性的作用.最后在FPGA开发平台上证明了该电路的可行性.