Crosstalk bandwidth and stability analysis in graphene nanoribbon interconnects

Based on transmission line modeling (TLM), and using the Nichols chart, we present a bandwidth and stability analysis, together with step time responses, for coupled multilayer graphene nanoribbon (MLGNR) interconnects that is inquired for the first time. In this analysis, the dependence of the degree of crosstalk relative stability for coupled MLGNR interconnects comprising of both capacitive and mutual-inductive couplings between adjacent MLGNR has been acquired. The obtained results show that with increasing the length or decreasing the width of the MLGNRs, the stability in near-end output increases. While, any increase in the length or width of MLGNRs, decrease the stability of far-end output. Also, by increasing capacitive coupling or decreasing inductive coupling, the near-end output becomes more stable, and the far-end output becomes less stable. Moreover, any increase in the length or capacitive coupling, decreases the bandwidth, whereas any increase in the width or inductive coupling, increases the bandwidth. Finally, transient simulations with Advanced Design System (ADS) show that the model has an excellent accuracy.     

Analysis and design of a new SRAM memory cell based on vertical lambda bipolar transistor

A voltage-controlled negative-differential-resistance device using a merged integrated circuit of two n-channel enhancement-mode MOSFETs and a vertical NPN bipolar transistor, called vertical Lambda-bipolar-transistor (VLBT), is presented for memory application. The new VLBT structure has been developed and its characteristics are derived by a simple circuit model and device physics. A novel single-sided SRAM cell based on the proposed VLBT is presented. Due to the characteristics of the VLBT, it offers better static noise margin and larger driving capability as compared with conventional single-side CMOS memory cell.     

Double-gate 1T-DRAM cell using nonvolatile memory function for improved performance

We propose a double-gate (DG) 1T-DRAM cell combining SONOS type storage node on the back-gate (control-gate) for nonvolatile memory function. The cell sensing margin and retention time characteristics were systematically examined in terms of control-gate voltage (V_cg) and nonvolatile memory (NVM) function. The additional NVM function is achieved by Fowler-Nordheim (FN) tunneling electron injection into the nitride storage node. The injected electrons induce a permanent hole accumulation layer in silicon body which improves the sensing margin and retention time characteristics. To demonstrate the effect of stored electrons in the nitride layer, experimental data are provided using 0.6 μm devices fabricated on SOI wafers.     

A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications

Powering billions of devices is one of the most challenging barrier in achieving the future vision of IoT. Most of the sensor nodes for IoT based systems depend on battery as their power source and therefore fail to meet the design goals of lifetime power supply, cost, reliable sensing and transmission. Energy harvesting has the potential to supplant batteries and thus prevents frequent battery replacement. However, energy autonomous systems suffer from sudden power variations due to change in external natural sources and results in loss of data. The memory system is a main component which can improve or decrease performance dramatically. The latest versions of many computing system use chip multiprocessor (CMP) with on-chip cache memory organized as array of SRAM cell. In this paper, we outline the challenges involved with the efficient power supply causing power outage in energy autonomous/self-powered systems. Also, various techniques both at circuit level and system level are discussed which ensures reliable operation of IoT device during power failure. We review the emerging non-volatile memories and explore the possibility of integrating STT-MTJ as prospective candidate for low power solution to energy harvesting based IoT applications. An ultra-low power hybrid NV-SRAM cell is designed by integrating MTJ in the conventional 6T SRAM cell. The proposed LP8T2MTJ NV-SRAM cell is then analyzed using multiple key performance parameters including read/write energies, backup/restore energies, access times and noise margins. The proposed LP8T2MTJ cell is compared to conventional 6T SRAM counterpart indicating similar read and write performance. Also, comparison with the existing MTJ based NV-SRAM cells show 51–78% reduction in backup energy and 42–70% reduction in restore energy.     

Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction

This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6 T SRAM core, a resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error detection (CED) and correction capabilities are provided by connecting the NVSRAM array with a dual-rail checker; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation, such that data from the non-volatile memory element is copied back to the SRAM core. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit.     

FEC编码在高速光通信系统中的应用与性能分析

高速光纤通信系统的研究是当前光通信领域的一大热点,信道编码技术是其中的一项关键技术。文章首先介绍了前向纠错（FEC）编码技术及其在光通信系统中的应用,然后描述了ITU-TG．709中定义的FEC帧的具体格式,数学推导了FEC编码给带来的误码率改善,并列出了具体的计算结果。最后通过实测两款具有FEC数字包封功能的芯片,给出了其在系统传输中的误码率与光信噪比的关系曲线,验证了前向纠错功能。     

Architecture design,performance analysis and VLSI implementation of a reconfigurable shared buffer for high‐speed switch/router

Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high‐speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst‐case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer‐sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer‐sharing scheme by both a numerical model and extensive simulations under uniform and non‐uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 µm CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high‐speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers. Copyright © 2008 John Wiley & Sons, Ltd.     

Modeling of optimum size and shape for high photovoltaic performance of poly(3-hexylthiophene) nanopore in interdigitated bilayer organic solar cells

The interdigitated design for donor–acceptor in solar cell has been studied in some detail, but the optimum size and shape leading to direct enhancement in nanopore (or nanopillar) structure is still not well understood. Here, we demonstrate a modeling method to forecast the optimum size and shape for poly(3-hexylthiophene) (P3HT) nanopores in interdigitated P3HT: [6, 6]-phenyl C₆₁ butyric acid methyl ester (PCBM) photovoltaic device, based on experimental results of P3HT:PCBM bilayer solar cell. In our analysis, the energy generated at unit nanopore is supposed to the same as the one generated at infinite point of P3HT:PCBM bilayer solar cell with variable layer thickness. A definitive function in terms of a radius of unit nanopore with various shapes is established, substituting a regression function derived from the results of power conversion efficiency in bilayer solar cell. Interpreting the function, we finally showed that the effective radius for P3HT nanopores with rectangular or cylinder, cut-cone, cone shape should be less than 135, 53, 2 nm respectively.     

Broadband sub-6 GHz flower-shaped MIMO antenna with high isolation using theory of characteristic mode analysis (TCMA) for 5G NR bands and WLAN applications

A small size neutralization line integrated flower-shaped MIMO antenna is designed and analyzed for sub-6 GHz type 5G NR frequency bands like n79 (4400–5000 MHz), n78 (3300–3800 MHz), n77 (3300–4200 MHz), and WLAN (5150–5825 MHz) applications. The novel approach of theory of characteristic mode analysis (TCMA) is introduced to provide physical insight of the designed structure and its characteristics behavior. Due to the suggested modifications in the geometry, the isolation among the patches is greatly increased. The overall miniaturized dimension of the MIMO antenna is 25 × 40 mm². The edge-edge spacing among the elements is 0.0233λ. The prototype antenna is fabricated and measured that shows good agreement compared with simulated results. The designed MIMO antenna without the presence of decoupling structure offers an isolation of 28 dB, gain of 3.6 dBi, and radiation efficiency of 69.7% at the resonant frequency. The proposed MIMO antenna covers a broad range of frequency band from 3.296 to 5.962 GHz with −10 dB impedance bandwidth of 2666 MHz and maintains a good isolation of greater than 50 dB for the entire operating band. The tested radiation efficiency and gain are 85.3% and 6.22 dBi at 3.5 GHz. Moreover, the diversity parameters of the neutralization line integrated MIMO antenna, that is, channel capacity loss (CCL) isolation, mean effective gain (MEG), total active reflection coefficient (TARC) diversity gain (DG), and envelope correlation coefficient (ECC), are analyzed and discussed in this article.