Interconnects for nanoscale MOSFET technology: a review

In this paper,a review of Cu/low-k,carbon nanotube(CNT),graphene nanoribbon(GNR)and optical based interconnect technologies has been done,Interconnect models,challenges and solutions have also been discussed.Of all the four technologies,CNT interconnects satisfy most of the challenges and they are most suited for nanometer scale technologies,despite some minor drawbacks.It is concluded that beyond 32nm technology,a paradigm shift in the interconnect material is required as Cu/low-k interconnects are approaching fundamental limits.     

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations

Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP.     

Modeling, Analysis, and Design of Graphene Nano-Ribbon Interconnects

Graphene nanoribbons (GNRs) are considered as a prospective interconnect material. A comprehensive conductance and delay analysis of GNR interconnects is presented in this paper. Using a simple tight-binding model and the linear response Landauer formula, the conductance model of GNR is derived. Several GNR structures are examined, and the conductance among them and other interconnect materials [e.g., copper (Cu), tungsten (W), and carbon nanotubes (CNTs)] is compared. The impact of different model parameters (i.e., bandgap, mean free path, Fermi level, and edge specularity) on the conductance is discussed. Both global and local GNR interconnect delays are analyzed using an RLC equivalent circuit model. Intercalation doping for multilayer GNRs is proposed, and it is shown that in order to match (or better) the performance of Cu or CNT bundles at either the global or local level, multiple zigzag-edged GNR layers along with proper intercalation doping must be used and near-specular nanoribbon edge should be achieved. However, intercalation-doped multilayer zigzag GNRs can have better performance than that of W, implying possible application as local interconnects in some cases. Thus, this paper identifies the on-chip interconnect domains where GNRs can be employed and provides valuable insights into the process technology development for GNR interconnects.      

Resistivity of Graphene Nanoribbon Interconnects

Graphene nanoribbon (GNR) interconnects are fabricated, and the extracted resistivity is compared to that of Cu. It is found that the average resistivity at a given linewidth $(hbox{18} hbox{nm} ≪ W ≪ hbox{52} hbox{nm})$ is about three times that of a Cu wire, whereas the best GNR has a resistivity that is comparable to that of Cu. The conductivity is found to be limited by impurity scattering as well as line-edge roughness scattering; as a result, the best reported GNR resistivity is three times the limit imposed by substrate phonon scattering. This letter reveals that even moderate-quality graphene nanowires have the potential to outperform Cu for use as on-chip interconnects.      

A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function

This paper describes a 1.8-V-only 256-Mb four-level-cell (2 b/cell) NOR flash memory with background operation (BGO) function fabricated in a 130-nm CMOS self-aligned shallow trench isolation (SA-STI) process technology. The new memory array architecture is adopted in which the flash source is connected by local interconnect to reduce the source resistance and constrain the floating-gate coupling effect. The mirrored current sensing read architecture for multilevel-cell operation at a supply voltage of 1.8 V has realized a fast asynchronous random access time (67 ns) and burst read at 54 MHz. A high speed and high reliability of program/erase cycling (100 k) has been achieved by dual-step pulse program algorithm and optimized erase sequence. Page program time and block erase time are 1.54 ms/2 kb and 538 ms/1 Mb, respectively     

Current-mode techniques for high-speed VLSI circuits withapplication to current sense amplifier for CMOS SRAM's

The speed of VLSI chips is increasingly limited by signal delay in long interconnect lines. A simple analysis shows that major speed improvements are possible when using current-mode rather than conventional voltage-mode signal transporting techniques. The key to this approach is the use of low-resistance current-signal circuits to drastically reduce the impedance level and the voltage swings on long interconnect lines. As an example, a simple four-transistor current-sense amplifier for fast CMOS SRAMs is proposed. The circuit presents a virtual short circuit to the bit lines, thus reducing the sensing delay, which is rendered practically insensitive to the bit-line capacitance. In addition, the virtual short circuit ensures equal bit-line voltages, thus eliminating the need for bit-line equalization during a read access     

Spin filtering and rectifying effects in the zinc methyl phenalenyl molecule between graphene nanoribbon leads

The molecule zinc methyl phenalenyl (ZMP), which is a neutral planar phenalenyl-based molecule, has been successfully synthesized experimentally, and large magnetic anisotropy was demonstrated when it is grown on the ferromagnetic metal surface [K. V. Raman et al. Nature, 2013, 493, 509]. Here, by using nonequilibrium Green's functions combined with the density functional theory, we investigate the electronic transport properties in the ZMP molecule coupled to graphene nanoribbon (GNR) leads. When the ZMP molecule is linked to zigzag GNR (ZGNR) electrodes, perfect spin-filtering effect and large spin-rectifying effect are found. And when the ZMP molecule is coupled to armchair GNR (AGNR) electrodes, rectifying effect is obtained and the rectifying directions can be manipulated by substituting the hydrogen atoms at the edge of ZMP molecule with atoms oxygen or nitrogen. The above interesting properties can be used for the next generation nanoscale device. Analyses are proposed for these phenomena.     

Scaling Behaviors of Graphene Nanoribbon FETs: A Three-Dimensional Quantum Simulation Study

The scaling behaviors of graphene nanoribbon (GNR) Schottky barrier field-effect transistors (SBFETs) are studied by self-consistently solving the nonequilibrium Green's function transport equation in an atomistic basis set with a 3-D Poisson equation. The armchair edge GNR channel shares similarities with a zigzag carbon nanotube; however, it has a different geometry and quantum confinement boundary condition in the transverse direction. The results indicate that the I-V characteristics are ambipolar and strongly depend on the GNR width because the bandgap of the GNR is approximately inversely proportional to its width, which agrees with recent experiments. A multiple gate geometry improves immunity to short channel effects; however, it offers smaller improvement than it does for Si MOSFETs in terms of the on-current and transconductance. Reducing the oxide thickness is more useful for improving transistor performance than using a high-k gate insulator. Significant increase of the minimal leakage current is observed when the channel length is scaled below 10 nm because the small effective mass facilitates strong source-drain tunneling. The GNRFET, therefore, does not promise to extend the ultimate scaling limit of Si MOSFETs. The intrinsic switching speed of a GNR SBFET, however, is several times faster than that of Si MOSFETs, which could lead to promising high-speed electronics applications, where the large leakage of GNR SBFETs is of less concern.     

Transfer matrix model of multilayer graphene nanoribbon interconnects

A general, algorithmic and exact transfer matrix model is presented for multilayer graphene nanoribbon (MLGNR) interconnects that is based on multi transmission line method (MTLM). In the proposed transfer matrix formulation the effect of Fermi level shift in GNR layers is considered. Also the capacitive and inductive coupling between the GNR layers is regarded in this matrix model. Moreover, in order to get the precise results, the block number parameter for distributed property of the interconnects is proposed for the first time. The straightforward, general and algorithmic format of the proposed matrix model causes it to be used for different technology nodes and length of the interconnects. Moreover any variation in the physical parameters can be involved simply in this formulation. Using this matrix model, one can examine different analytical prospects such as Nyquist, Bode, and Nichols stability criteria, zero and poles and step time responses for on-chip MLGNR interconnects, implemented for integrated circuit applications. Also this matrix model can be used in circuit simulators such as HSPICE in order to simulate the VLSI-ULSI circuits. As the couple of examples, we have extracted Nyquist diagrams and step time responses for 10 nm, 14 nm, and 22 nm technology nodes. The results show that relative stability of MLGNR interconnects increases with increasing technology node and interconnect length. The results demonstrate a considerable difference between the responses obtained using traditional MLGNR interconnect formulation and the exact proposed matrix model.     

Graphene Nanoribbon Tunnel Transistors

A graphene nanoribbon (GNR) tunnel field-effect transistor (TFET) is proposed and modeled analytically. Ribbon widths between 3 and 10 nm are considered to effect energy bandgaps in the range of 0.46 to 0.14 eV. It is shown that a 5-nm ribbon width TFET can switch from on to off with only 0.1-V gate swing. The transistor achieves 800 $muhbox{A}/muhbox{m}$ on -state current and 26 $hbox{pA}/muhbox{m}$ off-state current, with an effective subthreshold swing of 0.19 mV/dec. Compared to a projected 2009 $n$MOSFET, the GNR TFET can provide 5$times$ higher speed, 20$ times$ lower dynamic power, and 280 000$times$ lower off-state power dissipation. The high performance of GNR TFETs results from their narrow bandgaps and their 1-D nature.      

Ionization coefficient of monolayer graphene nanoribbon

A semi-analytical model for impact ionization coefficient of graphene nanoribbon (GNR) is presented. The model is derived by calculating probability of electrons reaching ionization threshold energy E_t and the distance travelled by electron gaining E_t. In addition, ionization threshold energy is semi-analytically modelled for GNR. During modelling, we justify our assumptions using analytical modelling and comparison with simulation. Furthermore, it is shown that conventional silicon models are not valid for calculation of ionization coefficient of GNR. Finally, the profile of ionization is presented using the proposed models and the results are compared with that of silicon.     

石墨烯基电子学研究进展

综述了石墨烯晶体的能带结构和独特的电子性质,如双极性电场效应、单双层石墨烯效应、衬底效应、石墨烯纳米带(GNR)带隙等特殊效应的研究现状。介绍了石墨剥落技术、外延生长和化学气相淀积(CVD)等石墨烯材料的制备以及表征方法。列举了石墨烯在电子、显示、太阳电池、传感器和氢存储等方面的应用,如在石墨烯场效应管、石墨烯纳米带场效应管(SET)、石墨烯单电子晶体管、石墨烯金属晶体管、石墨烯基纳米电子机械系统(NEMS)、石墨烯分子开关以及石墨烯基高电子迁移率晶体管(HEMT)制备方面的应用。人们已经研究出不同栅长的n/p型顶栅石墨烯场效应管(GFET),并采用标准的S参数直接表征器件的高频性能。理论和实验表明,所有石墨烯纳米带场效应管(GNRFET)在室温下工作的前提是GNR的带宽尺寸小于10nm,并具有半导体场效应管的性能。     

Pulsed wave interconnect

Pulsed wave interconnect is proposed for global interconnect applications. Signals are represented by localized wave-packets that propagate along the interconnect lines at the local speed of light to trigger the receivers. Energy consumption is reduced through charging up only part of the interconnect lines and using the voltage doubling property of the receiver gate capacitances. In a 0.18-/spl mu/m CMOS technology case study, SPICE simulations show that pulsed wave interconnect can save up to 50% of energy and /spl sim/30% of chip area in comparison with the repeater insertion method. A proposed signal splitting structure provides reasonable isolations between different receivers. Measured S-parameters of 3.8-mm interconnect lines fabricated through CMOS foundry showed that the distortion and attenuation of a pico second signal are much less serious than the theoretical predictions. Pulsed wave interconnect also enables time division application of a single line to boost its bit rate capacity. The use of nonlinear transmission lines (NLTL) is also proposed to overcome pulse broadening and attenuation caused by dispersion and frequency-dependent losses. Pulsed waves on an NLTL may be generated, transmitted, split and detected with components realizable in bulk and SOI CMOS technologies. Tapered NLTL can be used for pulse compression. NLTL edge sharpening abilities may be applicable for signal rise time control.     

Process and reliability of air-gap Cu interconnect using 90-nm node technology

A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant.     

Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations

The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel/source/drain doping profiles. An increase of the memory readout current by a factor of two was achieved with an excellent low-leakage current level of the access gate transistor. The increase of the read current allows faster read access, while the excellent subthreshold behavior of the access gate transistor allows aggressive scaling of the access gate length down to 160 nm. A gate voltage as low as 1 V can be used for reading the cell, so there is no need for voltage boosting. The source-side injection programming speed is increased by one order of magnitude for devices with thin access gate oxide. The compact cell is suited for embedded applications in sub-100-nm CMOS generations.     

A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure

Low-noise, high-speed circuit techniques for high-density DRAMs (dynamic random-access memories), as well as their application to a single 5-V 16-Mb CMOS DRAM with a 3.3-V internal operating voltage for a memory array, are described. It was found that data-line interference noise becomes unacceptably high (more than 25% of the signal) and causes a serious problem in 16-Mb DRAM memory arrays. A transposed data-line structure is proposed to eliminate the noise. Noise suppression below 5% is confirmed using this transposed data-line structure. A current sense amplifier is also proposed to maintain the data-transmission speed in common I/O lines, in spite of a reduced operating voltage and increased parasitic capacitance loading in the memory array. A speed improvement of 10 ns is achieved. Using these circuit techniques, a 16-Mb CMOS DRAM with a typical RAS access time of 60 ns was realized     

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISCprocessor

Novel 2.5 V CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and a leakless buffer circuit are applied to a floating point macrocell for a 200 MHz superscalar RISC processor. The NTP circuit has two advantages: high noise immunity and high speed. Floating point operations can be executed in a two cycle latency using the high speed NTP circuit. The leakless buffer circuit with NMOS transmission gate in 128 floating point registers makes possible both high integration and low power dissipation, since the circuit causes no leak current without precharging the number of read lines. The processor makes use of 0.3 μm CMOS technology with a 2.5 V power supply and four metal layers. The floating point macrocell has 380 thousand transistors and dissipates 350 mW at 200 MHz. The peak performance of the floating point macrocell is 400 MFLOPS     

Pipelined architecture for fast CMOS buffer RAMs

A novel pipeline architecture for CMOS static RAMs (SRAMs) that allows operation at very high clock rates is described. Basic requirements for achieving high speed are the implementation of a hierarchical architecture and a memory cell with separate READ and WRITE data lines. The access speed of hierarchically organized memory blocks was between 2.5 and 3.5 ns. The maximum operating frequency of a 16 K pipelined hierarchical SRAM (PHSRAM) is in the range of 300 MHz. The hierarchical architecture and a seven-transistor memory cell provide a circuit using digital swings all over. Key advantages of the full-swing static logic circuitry are robustness with respect to fabrication tolerances and a high-noise immunity. Moreover, the circuit can be reduced to finer structure sizes without any redesign, since there are no critical analog circuit parts     

Interconnect scaling scenario using a chip level interconnect model

This paper describes an interconnect scaling scenario, which considers the impact of metal aspect ratio and pitch at each layer, new interconnect materials, and improved circuit design techniques. A new design methodology for a multilevel interconnect scheme is proposed on the basis of a chip level interconnect model. The design rule, the number of metal layers, and selection of interconnect materials at each device generation are projected using this methodology. It is shown that the 0.13-μm CMOS generation requires not only new interconnect materials but also improved circuit design techniques such as variable pitch router and insertion of repeater buffers. A high-performance LSI in the 0.13-μm CMOS generation needs seven layers using Cu interconnect and low-k dielectrics     

Comparisons of Performance Potentials of Silicon Nanowire and Graphene Nanoribbon MOSFETs Considering First-Principles Bandstructure Effects

In this paper, we investigate the performance potentials of silicon nanowire (SNW) and semiconducting graphene nanoribbon (GNR) MOSFETs by using first-principles bandstructures and ballistic current estimation based on the “top-of-the-barrier” model. As a result, we found that SNW-MOSFETs display a strong orientation dependence via the atomistic bandstructure effects, and [110]-oriented SNW-MOSFETs provide smaller intrinsic device delays than Si ultrathin-body MOSFETs when the wire size is scaled smaller than 3 nm. Furthermore, GNR-MOSFETs are found to exhibit promising device performance if the ribbon width is designed to be larger than a few nanometers and a finite band gap can be established.