Evaluation of process parameter space of bulk FinFETs using 3D TCAD

Using full 3D TCAD, an evaluation of process parameter space of bulk FinFET is presented from the point of view of DRAM, SRAM and I/O applications. Process and device simulations are performed with varying uniform fin doping, anti-punch implant dose and energy, fin width, fin height and gate oxide thickness. Bulk FinFET architecture with anti-punch implant is introduced beneath the channel region to reduce the punch-through and junction leakage. For 30 nm bulk FinFET, anti-punch implant with low energy of 15 to 25 keV and dose of 5.0 × 10¹³ to 1.0 × 10¹⁴ cm⁻² is beneficial to effectively suppress the punch-through leakage with reduced GIDL and short channel effects. Our simulations show that bulk FinFETs are approximately independent of back bias effect. With identical fin geometry, bulk FinFETs with anti-punch implant show same I_ON-I_OFF behavior and approximately equal short channel effects like SOI FinFETs.     

Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation

This paper investigates and compares the impacts of metal-gate work-function variation on important analog figures-of-merit (FOMs) for TFET and FinFET devices using 3-D atomistic TCAD simulations. Our study indicates that, at 0.6 V supply voltage and 0.2 V gate-voltage overdrive, TFET exhibits superior variation immunity regarding transconductance to drain–current ratio (g_m/I_DS), output resistance (R_out) and intrinsic gain, and comparable variability in g_m and cutoff frequency (f_T) as compared with the FinFET counterparts. In addition, how the correlations between pertinent parameters (e.g., g_m and R_out) impact the variation immunity of important analog FOMs are analyzed. Our study may provide insights for low-voltage analog design using TFET/FinFET technologies.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

The meta-stable dip (MSD) effect in SOI FinFETs

The meta-stable dip (MSD) effect is demonstrated and characterized in SOI FinFETs. With ascending scan of front-gate voltage (V_G1), the magnitude of drain current (I_D) tends to be fixed within a specific region of the front-gate voltage and this leads to a dip of transconductance (g_m). The dip width can be modulated through a control of bias condition or measurement speed such as back-gate voltage (V_G2), drain voltage (V_D) and step size of the front-gate voltage. From the dual-gate transient measurement, it is found that the MSD effect is highly dependent on the floating-body effect. In SOI FinFETs, the MSD effect is significantly affected by the fin width due to the fringing electric field of the lateral gates.     

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

PBTI degradation on FinFETs with HfO₂/TiN gate stack (EOT < 1 nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-κ oxide than in the sidewall of the fin. This could explain more severe PBTI degradation.     

Impact of the lateral straggle on the Analog and RF performance of TFET

In this work, the effect of the variation in lateral straggle on TFETs performance is demonstrated. The ion implantation technique during fabrication process causes the extension of dopants from source/drain region towards the channel. Even though the use of non-zero tilt angle at the time of ion implantation is necessary to avoid the channeling effect, however, series resistance, threshold voltage roll offs, switching speed and effective channel length of the device get affected by the non abrupt doping profile at the source/drain-body junction. It is established earlier that TFET is very convenient for Analog/RF application owing to its below 60 mV/decade subthreshold swing and reduced short channel effects. In order to show the effect of lateral straggle on TFET’s performance, various Analog figure of merits (FOMs) such as drain current (I_d), transconductance (g_m), transconductance generation factor (g_m/I_d), output resistance (R_o), intrinsic gain (g_mR_o) and RF figure of merits (FOMs) like unity gain cutoff frequency (f_T), transit frequency of maximum available power gain (f_MAX) are investigated for the variation in straggle parameter from 0 nm to 5 nm in order to optimize the device performance. The circuit performance of the device for different lateral straggle is carried out using common source amplifier.     

ESD issues in advanced CMOS bulk and FinFET technologies: Processing,protection devices and circuit strategies

The ESD performance of several CMOS bulk and SOI technologies is reviewed. The ESD area-efficiency of FinFETs is put in relation to bulk and SOI. CMOS bulk technologies have improved over the past generations owing to the possibility of reduced ESD layout dimensions. While having observed It2 values of less than 2 mA/μm² in 130 nm technology, we are able to obtain almost 4 mA/μm² in 45 nm. Downscaling will shift the challenge for a robust ESD design from the ESD protection device in the IO cell to the metal routing and voltage clamping in the supply tree. This will increase cost and effort for ESD protection of modern IC’s in spite of improvement in It2.For FinFET technologies, the influence of device layout, electrical operation modes and processing is discussed. The initially extremely low ESD values of FinFETs have been strongly improved by overall process maturity and added process features. The ESD levels of FinFET technologies are now scalable up to the levels compliant with full IC design constraints. While the area-performance is still about two times lower than in bulk CMOS, it is much better than anticipated earlier.In light of the challenges ahead for technology and circuit applications, the impact on ESD protection strategies is studied. Classical protection approaches are critically examined regarding the latest technology developments and new requirements for IO interface circuits. A switch from bulk to FinFET technology is still regarded as a major disruption for product architecture and thus ESD.     

Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation

In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack Schottky-Barrier Source/Drain Gate All Around (SM-GS-SB-S/D GAA) structures are proposed for low- power wireless applications. The Analog/RF performance for wireless applications of these devices are demonstrated. The effect of Schottky-Barrier (Metal) S/D is studied for Single Metal (SM)–SB-GAA, (Dual Metal) DM-SB-GAA, SM-GS-SB-GAA and GME-GS-SB-GAA MOSFETs, and it is found that GME-GS-SB-GAA MOSFET with metal drain source shows much improved performance in terms of transconductance (g_m), output conductance (g_d), Early Voltage (V_EA), Maximum Transducer Power Gain, cut-off frequency (f_T), and I_on/I_off ratio. Further, harmonic distortion for wireless applications is also studied using ATLAS-3D device simulator. Due to low parasitic S/D resistance the metal Source/Drain DM-GS-SB-S/D-GAA MOSFET demonstrates remarkable I_on of~31.8 μA/μm and saturation transconductance g_m of~68.2 μS with improved third order derivative of transconductance g_m3.     

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I_D=5 μA/μm and V_DS=0.5 V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V_DD=0.5 V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ～20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V_DD=0.5 V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ～10%, ～35% and ～25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.     

Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack

Bias-Temperature Instability (BTI) is one of the key device reliability concerns for both digital and analog circuit operations. Features of work-function metal (WFM) for V_T modulation in 10 nm FinFET process technology results in WFM dependent BTI characteristics. Similar levels of aging degradation to those of previous 14 nm technology were observed in both DC and AC operations. As BTI-induced V_T variability is expected to increase with 3D fin dimension scaling, such variability must be accurately characterized and considered for circuit designs. This paper reports the impact of transistor- level BTI degradation on circuits by studying Ring Oscillator (RO) and SRAM. The SRAM cell stabilities in terms of SNM (Static Noise Margin) and WRM (Write Margin) were further studied through SRAM HTOL stresses by characterizing V_min shift. Robust 10 nm SRAM and product level HTOL reliability up to 500 h were demonstrated.     

Three-Dimensional FinFET Source/Drain and Contact Design Optimization Study

The optimization of dopant-segregated Schottky (DSS) and raised source/drain (RSD) FinFETs is investigated through a 2-D and 3-D TCAD study. ldquoSilicide gatingrdquo due to fringing fields extending from a flared silicide contact degrades DSS and RSD FinFET performances. Thus, for a multifin DSS device, the individual source/drain fins should have minimal silicide flaring and be strapped with a metal bar. For large fin pitches (FPs), this results in lower intrinsic delay and much lower delay dependence on FP than optimized RSD FinFETs, which have source/drain fins strapped using lateral epitaxial growth and accessed with vias. However, RSD FinFETs achieve lower delay for small FP and fin heights (H _fin) due to low via-to-gate fringing capacitance. Thus, a new structure is proposed, called the recessed strap DSS FinFET, which combines the merits of optimized DSS and RSD FinFETs in a way that provides equivalent or improved performance over all ranges of FP and H _fin.     

The optimum fin width in p-MuGFETs with the consideration of NBTI and hot carrier degradation

Generally it is known that NBTI degradation increases with decrease of a channel width in p-MOSFETs but hot carrier degradation decreases. In this work, a guideline for the optimum fin width in p-MuGFETs is suggested with consideration of NBTI and hot carrier degradation. Using the device lifetime defined as the stress time necessary to reach ΔV_TH = 10 mV, the optimum fin widths have been extracted for different stress voltages and temperatures. When a fin width is narrower than the optimum fin width, the device lifetime is governed by the NBTI degradation. However, when fin width is wider than the optimum fin width, the device lifetime is dominantly governed by hot carrier degradation. The optimum fin width decreases with the increase of the stress voltage but it increases with the increase of the stress temperature.     

Electrical properties and barrier modification of GaAs MIS Schottky device based on MEH-PPV organic interfacial layer

We report fabrication and electrical characterization of GaAs based metal-interfacial layer-semiconductor (MIS) device with poly[2-methoxy-5-(2^/-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV), as an interfacial layer. MEH-PPV raises the barrier height in Al/MEH-PPV/p-GaAs MIS device as high as to 0.87 eV. A Capacitance-Voltage (C–V) characteristic exhibits a low hysteresis voltage with an interface states density of 1.69×10¹¹ cm⁻² eV⁻¹. Moreover, a high transition frequency (f_c) of about 50 kHz was observed in the accumulation mode. The photovoltaic response of Al/MEH-PPV/p-GaAs device was measured under the air masses (AM) 1.0 and 1.5. The open circuit voltage (V_OC), short circuit current (I_SC), fill factor and the efficiency of the Al/MEH-PPV/p-GaAs device were found to be 1.10 V, 0.52 mA, 0.65, and 5.92%, respectively, under AM 1.0 condition.     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

Performance analysis of nanoscale GeSn MOSFETs for mixed-mode circuit applications

Using extensive numerical analysis we investigate the impact of Sn ranging 0–6% in compressively strained GeSn on insulator (GeSnOI) MOSFETs for mixed-mode circuit performance at channel lengths (L_g) ranging 100–20 nm with channel thickness values of 10 and 5 nm. Our results reveal that 10 nm thick Ge_0.94Sn_0.06 channel MOSFETs produce improvement of peak transconductance g_m, peak gain Av, peak cut-off frequency f_T and maximum frequency of oscillations f_max by 80.5%, 18.8%, 83.5% and 81.7%, respectively compared with equivalent GeOI device at L_g =20 nm. Furthermore, such devices exhibit 78.8% increase in ON-current I_ON while yield 44.5% reduction in delay as compared to Ge control devices enabling them attractive for logic applications. Thinning of the channel thickness from 10 to 5 nm increases peak Av, peak transconductance efficiency and reduces output conductance and OFF-current I_OFF while degrading other parameters in all GeSnOI and control Ge devices.     

Stepwise co-sensitization as a useful tool for enhancement of power conversion efficiency of dye-sensitized solar cells: The case of an unsymmetrical porphyrin dyad and a metal-free organic dye

A tertiary arylamine compound (DC), which contains a terminal cyano-acetic group in one of its aryl groups, and an unsymmetrical porphyrin dyad of the type Zn[Porph]-L-H₂[Porph] (ZnP-H₂P), where Zn[Porph] and H₂[Porph] are metallated and free-base porphyrin units, respectively, and L is a bridging triazine group functionalized with a glycine moiety, and were synthesized and used for the fabrication of co-sensitized dye-sensitized solar cells (DSSCs). The photophysical and electronic properties of the two compounds revealed spectral absorption features and frontier orbital energy levels that are appropriate for use in DSSCs. Following a stepwise co-sensitization procedure, by immersing the TiO₂ electrode in separate solutions of the dyes in different sequence, two co-sensitized solar cells were obtained: devices C (ZnP-H₂P/DC) and D (DC/ZnP-H₂P).The two solar cells were found to exhibit power conversion efficiencies (PCEs) of 6.16% and 4.80%, respectively. The higher PCE value of device C, which is also higher than that of the individually sensitized devices based on the ZnP-H₂P and DC dyes, is attributed to enhanced photovoltaic parameters, i.e. short circuit current (J_sc = 11.72 mA/cm²), open circuit voltage (V_oc = 0.72 V), fill factor (FF = 0.73), as it is revealed by photovoltaic measurements (J–V curves) and by incident photon to current conversion efficiency (IPCE) spectra of the devices, and to a higher total dye loading. The overall performance of device C was further improved up to 7.68% (with J_sc = 13.45 mA/cm², V_oc = 0.76 V, and FF = 0.75), when a formic acid treated TiO₂ ZnP-H₂P co-sensitized photoanode was employed (device E). The increased PCE value of device E has been attributed to an enhanced J_sc value (=13.45 mA/cm²), which resulted from an increased dye loading, and an enhanced V_oc value (=0.76 V), attributed to an upward shift and increased of electron density in the TiO₂ CB. Furthermore, dark current and electrochemical impedance spectra (EIS) of device E revealed an enhanced electron transport rate in the formic acid treated TiO₂ photoanode, suppressed electron recombination at the photoanode/dye/electrolyte interface, as well as shorter electron transport time (τ_d), and longer electron lifetime (τ_e).     

Performance of commercial foundry-level AlGaN/GaN HEMTs after hot electron stressing

The performance degradation of commercial foundry level GaN HEMTs placed under a constant-power drain voltage step-stress test has been studied. By utilizing electroluminescence measurement techniques to optimize hot electron stress testing conditions (Meneghini, 2012), no significant permanent changes in saturation current (I_dss), transconductance (Gm), and threshold voltage (V_th) can be seen after stress testing of drain voltages from 30 V up to 200 V. We observe little permanent degradation due to hot electron effects in GaN HEMTs at these extreme operating conditions and it is inferred that other considerations, such as key dimensions in channel or peak electric field (Chynoweth, 1958; Zhang and Singh, 2001) [2,3], are more relevant to physics of failure than drain bias alone.     

In situ modification of low-cost Cu electrodes for high-performance low-voltage pentacene thin film transistors (TFTs)

We demonstrate low-voltage pentacene thin film transistors (TFTs) using in situ modified low-cost Cu (M-Cu) as source–drain (S/D) electrodes and solution-processed high capacitance (200 nF/cm²) gate dielectrics. Under a gate voltage of ?3 V, the device with M-Cu electrodes shows a much higher apparent mobility (1.0 cm²/V s), a positively shifted threshold voltage (?0.62 V), a lower contact resistance (0.11 MΩ) and a larger transconductance (12 μS) as compared to the device with conventional Au electrodes (corresponding parameters are 0.71 cm²/V s, ?1.44 V, 0.41 MΩ, and 5.7 μS, respectively). The enhancement in the device performance is attributed to the optimized interface properties between S/D electrodes and pentacene. Moreover, after encapsulation the M-Cu electrodes with a thin layer of Au in the aim of suppressing unfavorable surface oxidation, the electronic characteristics of the device are further improved, and highly enhanced apparent mobility (2.3 cm²/V s) and transconductance (19 μS) can be achieved arising from the increased conductivity of the electrode itself. Our study provides a simple and feasible approach to achieve high performance low-voltage OTFTs with low-cost S/D electrodes, which is desirable for large area applications.     

Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

Fin Field Effect Transistors (FinFETs) are used for Complementary Metal Oxide Semiconductor applications beyond the 45?nm node of the Semiconductor Industry Association (SIA) roadmap because of their excellent scalability and better immunity to short channel effects. This article examines the impact of high-k dielectrics on FinFETs. The FinFET device performance is analysed for On Current, Off Current, I _on/I _off ratio, drain induced barrier lowering, electrostatic potential along the channel, electric field along the channel, transconductance, output resistance, intrinsic gain, gate capacitance and transconductance generation factor, by replacing the conventional silicon dioxide gate dielectric material, with various high dielectric constant materials. Nanosize ZrO₂ (zirconium-di-oxide) is found out to be the best alternative for SiO₂ (silicon-di-oxide). It is also observed that the integration of high-k dielectrics in the devices significantly reduces the short channel effects and leakage current. The suitability of nanoscale FinFETs is observed with the help of an inverter circuit and their gain values are calculated for circuit applications.     

Investigation on the thermal behavior of 0.15 μm gate-length In0.4Al0.6As/In0.4Ga0.6As MHEMT

In this study, we have successfully investigated the electrical performances of In_0.4Al_0.6As/In_0.4Ga_0.6As metamorphic high-electron-mobility transistor (MHEMT) at temperatures range from 275 K to 500 K comprehensively. By extracting the device S-parameters, the temperature dependent small signal model has been established. At room temperature, 0.15 μm T-gate device with double δ-doping design exhibits f_T and f_MAX values of 103 GHz and 204 GHz at V_ds = 1 V, an extrinsic transconductance of 678 mS/mm, and a current density of 578 mA/mm associated with a high breakdown voltage of ?13 V. Power measurements were evaluated at 40 GHz and the measured output power, linear power gain, and maximum power-added efficiency, were 7.12 dBm, 10.15 dB, and 23.1%, respectively. The activation energy (E_a) extracted from Arrhenius plots is = 0.34 eV at 150 ≦ T ≦ 350 K. The proposed device is promisingly suitable for millimeter-wave power application.