Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

激光烧结Al2O3/Ti系FGM的温度场与热应力场

用有限元法对激光烧结Al2O3/Ti系FGM的温度场和残余热应力场进行了模拟计算,并对烧结过程试样中的温度分布进行了实时测量.结果表明:激光照射面(Al2O3层)和背光面(Ti层)的温度落差为325℃.陶瓷侧温度梯度大于金属侧,成分梯度指数p值愈大,陶瓷侧温度梯度愈大.试样内残余热应力分布受p值控制,依据残余热应力最小且陶瓷层为压应力的设计准则,确定了激光烧结Al2O3/Ti系FGM的最佳成分梯度指数p=0.5.     

The influence of defects on device performance of MBE-grown Si homojunction and strained Si1-xGex/Si heterostructures

Different Si homojunction and strained Si_1-xGe_x/Si heterojunction diodes and bipolar transistors have been fabricated by Si-MBE. The effect of annealing on Si homojunction diodes and transistors are studied. It is found that annealing generally improves the Si device performance, such as the ideality factor and breakdown characteristics. The influence of⁶⁰Co γ irradiation on the Si_1-xGe_x/Si diode performances are investigated by studying the temperature dependence of their electrical characteristics, and the results are correlated with the quality of the MBE-films. γ irradiation causes a drop in material conductivity due to the generation of atom-displacement defects in the whole volume of the wafers and increases the defect density at hetero-interfaces. The forward I-V curves of Si_1-xGe_x/Si devices may shift towards lower or higher voltages, depending on the film quality and the irradiation dose. The increase of defect density in strained Si_1-xGe_x/Si films appears to occur easier for the films with lower quality. Electrical measurements and calculations show that the defect-associated tunneling process is important in current transport for these MBE grown Si homojunction and strained Si_1-xGe_x/Si heterojunction devices, which have initially medium film quality or have been treated by irradiation.     

D/S架构即时型植物信息系统的开发设计

在对植物信息系统的开发设计过程中,提出了结合即时通讯技术,同时弥补C/S与B/S混合结构缺陷的新软件架构D/S(Desktop/Server),并以D/S为框架,建立即时型植物信息系统模型.通过对该模型中各模块的作用及相互关系的分析,阐述了业务流程与数据建模相结合的设计出发点,并通过对系统结构及主要技术实现的剖析,进一步说明该设计方案的优越性和实用性.     

表面态密度分布和源漏电阻对6H-SiC PMOS器件特性的影响

建立了一个价带附近的界面态密度分布模型,并用该模型较好地模拟了6H-SiC PMOS器件的阈值电压随温度变化的趋势、C-V特性以及转移特性.理论C-V特性曲线是用数值解泊松方程的方法得到的,在解泊松方程的过程中考虑了场致离化效应.由于SiC PMOS器件的源漏电阻比较大,因此,在计算强反型情况下的漏电流时,同时考虑了源漏电阻的影响.结果表明,源漏电阻对漏电流的影响很大.     

基于WebGL的3D立库可视化系统设计与实现

针对当前扩大化和普及化的仓储物流,提出了一种3D自动化立体仓库可视化系统的实现方案,用以解决仓储系统中遇到的数据不直观的问题.该系统采用JavaScript编程语言,以Three.js引擎为基础,构建了基于WebGL的三维自动化立体仓库的可视化系统,该系统能有效直观的进行仓储管理,适合现代化仓储企业的管理需求.     

Reliability assessment of SiO2/ZrO2 stack gate dielectric on strained-Si/Si0.8Ge0.2 heterolayers under dynamic and AC stress

The reliability characteristics of SiO₂/ZrO₂ gate dielectric stacks on strained-Si/Si_0.8Ge_0.2 have been investigated under dynamic and pulsed voltage stresses of different amplitude and frequency in order to analyze the transient response and the degradation of oxide as a function of stress parameters. The current transients observed in dynamic voltage stresses have been interpreted in terms of the charging/discharging of interface and bulk traps. The evolution of the current during unipolar pulsed voltage stresses shows the degradation being much faster at low frequencies than at high frequencies. Results have been compared with those obtained after CVS, as a function of injected charge and pulse frequency.     

基于EWB的D/A数模转换器的仿真研究

阐述了D／A转换器的仿真原理，给出了T形电阻网络D／A转换器仿真模型的构造方法，并采用EWB进行了系统仿真，仿真结果表明该方法是合理、可行的。