虚拟医疗设备的系统构建

为了解决传统医疗仪器在显示、数据处理、存储能力受限、无法有效利用网路进行数据共享以及维护繁琐等方面的问题,提出了基于Labview虚拟仪器技术,融合HL7(healthy level7)协议.利用PC强大的处理功能,实现医疗设备的虚拟化,建立虚拟医疗设备系统的方案.有效地解决了传感器、虚拟仪器及HL7协议的集成问题,并对系统实现的各个子模块进行了详细的描述.     

Energy-aware application performance management in virtualized data centers

Both performance and energy cost are important concerns for current data center operators. Traditionally, however, IT and mechanical engineers have separately optimized the cyber and physical aspects of data center operations. This paper considers both of these aspects with the eventual goal of developing performance and power management techniques that operate holistically to control the entire cyber-physical complex of data center installations. Toward this end, we propose a balance of payments model for holistic power and performance management. As an example of coordinated cyber-physical system management, the energy-aware cyber-physical system (EaCPS) uses an application controller on the cyber side to guarantee application performance, and on the physical side, it utilizes electric current-aware capacity management (CACM) to smartly place executables to reduce the energy consumption of each chassis present in a data center rack. A web application, representative of a multi-tier web site, is used to evaluate the performance of the controller on the cyber side, the CACM control on the physical side, and the holistic EaCPS methods in a mid-size instrumented data center. Results indicate that coordinated EaCPS outperforms separate cyber and physical control modules.     

Mesoscale performance simulation of multicore processor systems

Modern microprocessor design relies heavily on detailed full-chip performance simulations to evaluate complex trade-offs. Typically, different design alternatives are tried out for a specific sub-system or component, while keeping the rest of the system unchanged. We observe that full-chip simulations for such studies is overkill. This paper introduces mesoscale simulation, which employs high-level modeling for the unchanged parts of a design and uses detailed cycle-accurate simulations for the components being modified. This combination of high-level and low-level modeling enables accuracy on par with detailed full-chip modeling while achieving much higher simulation speeds than detailed full-chip simulations. Consequently, mesoscale models can be used to quickly explore vast areas of the design space with high fidelity. We describe a proof-of-concept mesoscale implementation of the memory subsystem of the Cell/B.E. processor and discuss results from running various workloads.     

Energy-aware capacity scaling in virtualized environments with performance guarantees

We investigate the trade-off between performance and power consumption in servers hosting virtual machines running IT services. The performance behavior of such servers is modeled through Generalized Processor Sharing (GPS) queues enhanced with a green speed-scaling mechanism that controls the processing capacity to use depending on the number of active virtual machines. When the number of virtual machines grows large, we show that the stochastic evolution of our model converges to a system of ordinary differential equations for which we derive a closed-form formula for its unique stationary point. This point is a function of the capacity and the shares that characterize the GPS mechanism. It allows us to show that speed-scaling mechanisms can provide large reduction in power consumption having only small performance degradation in terms of the delays experienced in the virtual machines. In addition, we derive the optimal choice for the shares of the GPS discipline, which turns out to be non-trivial. Finally, we show how our asymptotic analysis can be applied to the dimensioning and service partitioning in data-centers. Experimental results show that our asymptotic formulas are accurate even when the number of virtual machines is small.     

Writeback throttling in a virtualized system with SCM

Storage class memory (SCM) has the potential to revolutionize the memory landscape by its non-volatile and byte-addressable properties. However, there is little published work about exploring its usage for modern virtualized cloud infrastructure. We propose SCM-vWrite, a novel architecture designed around SCM, to ease the performance interference of virtualized storage subsystem. Through a case study on a typical virtualized cloud system, we first describe why current writeback manners are not suitable for a virtualized environment, then design and implement SCM-vWrite to improve this problem. We also use typical benchmarks and realistic workloads to evaluate its performance. Compared with the traditional method on a conventional architecture, the experimental result shows that SCM-vWrite can coordinate the writeback flows more effectively among multiple co-located guest operating systems, achieving a better disk I/O performance without any loss of reliability.     

一种基于同构多核处理器的动态节能调度算法

在节能计算系统中节能调度是一个重要的研究方向。目前针对节能调度的研究中,多从动态电压频率调节（DVFS）的角度进行。但是随着芯片制造工艺的改进,处理器核心电压越来越低,所能调节的电压范围越来越小,通过DVFS技术实现节能遇到了理论上的瓶颈。提出了一种基于同构多核处理器的动态节能调度算法。在系统负载较轻的情况下,通过将系统任务分配到较少的处理核心上而使其他处理核心处于休眠状态来达到动态节能的效果。实验表明该算法具有较好的节能效果。     

Soft computing system for bank performance prediction

This paper presents a soft computing based bank performance prediction system. It is an ensemble system whose constituent models are a multi-layered feed forward neural network trained with backpropagation (MLFF-BP), a probabilistic neural network (PNN) and a radial basis function neural network (RBFN), support vector machine (SVM), classification and regression trees (CART) and a fuzzy rule based classifier. Further, principal component analysis (PCA) based hybrid neural networks, viz. PCA-MLFF-BP, PCA-PNN and PCA-RBF are also included as constituents of the ensemble. Moreover, GRNN and PNN were trained with a genetic algorithm to optimize the smoothing factors. Two ensembles (i) simple majority voting based and (ii) weightage based are implemented. This system predicts the performance of a bank in the coming financial year based on its previous 2-years’ financial data. Ten-fold cross-validation is performed in the training sessions and results are validated with an independent production set. It is demonstrated that the ensemble is able to yield lower Type I and Type II errors compared to its constituent models. Further, the ensemble also outperformed an earlier study [P.G. Swicegood, Predicting poor bank profitability: a comparison of neural network, discriminant analysis and professional human judgement, Ph.D. Thesis, Department of Finance, Florida State University, 1998] that used multivariate discriminant analysis (MDA), MLFF-BP and human judgment.     

Efficient and scalable scheduling for performance heterogeneous multicore systems

Performance heterogeneous multicore processors (HMP for brevity) consisting of multiple cores with the same instruction set but different performance characteristics (e.g., clock speed, issue width), are of great concern since they are able to deliver higher performance per watt and area for programs with diverse architectural requirements than comparable homogeneous ones. However, such power and area efficiencies of performance heterogeneous multicore systems can only be achieved when workloads are matched with cores according to both the properties of the workload and the features of the cores.     

Analysing performance in a word prediction system with multiple prediction methods

In this article, we investigate the performance of a hybrid prediction system with a phrase prediction utility in English word prediction from two viewpoints. From the application user’s point of view, measures of effort savings are important in word prediction. Global performance measures such as the average percentage of keystroke or character savings, however, hide rather than display the details of the functioning of the prediction system as a whole. In the present study, we analysed in detail the performance of a prediction system with a phrase prediction utility along with single word prediction. Our preliminary results with a corpus of 383 lexical bundles show that, from a technological viewpoint, the following three parameters affect the practical utility of the phrase prediction method in a hybrid prediction system: (1) cost of selecting an appropriate prediction mode for single word prediction and phrase prediction; (2) token frequency of phrases in the text predicted, and (3) coverage of the phrasal lexicon. We found that all three affect the phrase prediction performance in different proportions. When the percent of ambiguous search keys finding both phrases and single words is 20%, phrase frequency 35%, and coverage of the phrasal lexicon 98%, the character savings percentage for the whole text will be improved by 6% points under optimal conditions. The system is practically useful as long as an appropriate prediction mode can be selected automatically or the cost of disambiguation of a prediction mode is not too high.     

异构多核计算系统的Codelet任务调度策略

Codelet数据流计算模型在处理大规模并行计算任务时效果显著,但该模型目前缺少在异构多核环境中的任务调度策略。因此,提出了一种在异构多核环境下基于蚁群算法的Codelet任务调度策略。该调度策略将启发式算法与蚁群算法相融合,在发挥各自优势的同时克服了启发式算法不能得出最优解的缺陷以及蚁群算法初始信息匮乏的问题。实验结果表明,智能蚁群任务调度策略相比Codelet运行时系统中原生的动态调度和静态调度策略具有更高的执行效率。     

一种基于多核嵌入式系统的TD-LTE同步校正方法

针对TD-LTE系统中同步性错误随机发生的问题,提出了一种通过ARM+DSP+FPGA平台的嵌入式系统实现帧号和原语的同步校正方法。该方法基于TD-LTE射频一致性测试仪表硬件平台,通过该嵌入式系统中ARM、DSP、FPGA间的协调工作,由GPMC模块通过帧号和原语两方面对系统同步性进行校正。在TD-LTE射频一致性测试仪表硬件平台中进行了验证,结果表明,该方法在实现帧号与子帧号同步校正的基础上明显提高了TD-LTE系统通信的稳定性。     

Task optimization based on CPU pipeline technique in a multicore system

Currently, the multicore system is prevalent in desktops, laptops or servers. The web proxy can save network traffic overhead and shorten communication cost. Especially with the fast development of wireless Internet accessing, the web proxy will take a more important role in the future. To obtain the fast response and high hit rate from the proxy, we study the processing of web proxy and deeply exploit parallel features which exist in kinds of proxy work flow. We propose the CP technique to build parallel tasks in a proxy system. The result shows that our scheme can efficiently improve the data throughput and fully utilize the computing resources provided by the multicore system.     

Appropriate allocation of workloads on performance asymmetric multicore architectures via deep learning algorithms

Asymmetric multicore processors (AMP) have become popular in both high-end and low-end computing systems due to its flexibility and high performance. A performance asymmetric multicore architecture (P-AMP) is the subcategory of AMP, which integrates the different micro-architecture cores in the same chip. Due to the heterogeneity nature of cores and applications, recognizing an optimal hardware configuration in terms of core, voltage-frequency pair for each application is still an NP-hard problem. Optimization of energy-delay product (EDP) is an additional challenging task in such architectures.To address these challenges, we developed a novel core prediction model called lightweight-deep neural network (LW-DNN) for asymmetric multicore processors. The proposed LW-DNN includes three phases, feature selection, feature optimization, and core prediction module. In the first and second phases, workload characteristics are extracted and optimized using the pre-processing algorithm and in the third phase, it predicts the appropriate cores for each workload at runtime to enhance the energy-efficiency and performance.We modeled a deep learning neural network using scikit-learn python library and evaluated in ODROID XU3 ARM big-Little performance asymmetric multicore platform. The embedded benchmarks we considered are MiBench, IoMT, Core-Mark workloads. The proposed LW-DNN prediction module compared with other traditional algorithms in terms of accuracy, execution time, energy consumption, and energy-delay product. The experimental results illustrate that accuracy achieved up to 97% in core prediction, and the average improvement in minimization of energy consumption is 33%, 35% in energy-delay product, 33% minimized in execution time correspondingly.     

基于TMS320C6678多核DSP的分布式通信系统

根据TMS320C6678芯片的特点,针对核间、片间、板间的通信要求,提出了一种跨系统的透明传输模型及实现,并分析了传输性能,对基于TMS320C6678的嵌入式软件系统设计提供了指导。     

Dynamic ranking-based MapReduce job scheduler to exploit heterogeneous performance in a virtualized environment

The Journal of Supercomputing - “More data, more information.” Big data helps businesses and research communities to gain insights and increase productivity. Many public cloud service...