SDH芯片功能验证平台的设计与实现

集成电路芯片的规模不断增大，功能越来越复杂，设计验证工作量也越来越大，成为整个设计周期的“瓶颈”。文章针对同步数字体量（SDH）宽带交换芯片设计中的功能验证，设计了初步的SDH验证平台，提出了具有一定通用性的SDH芯片的功能验证方案和实现方法，包括分层的描述和验证方法，一系列标准测试数据和自动观测模拟结果的若干加速C程序。该平台已用于40Gbit／s交换芯片的功能验证，加速了验证过程，取得了满意的效果。     

基于FPGA的音频监控系统的设计与实现

广播电台信号的监控是播出安全的重要保障。为了实现对电台音频信号的远程和本地监控,提出了利用FPGA来处理数字音频信号,并将处理的结果网络化传输的系统方案。文中具体阐述了系统中的音频采集、音频分析、音频切换、网络传输模块和软件的设计,并给出了系统实物图和实际测试结果。测试表明,该系统工作可靠,性能稳定,减轻了电台听音人员的负担。     

A new set of channel allocation algorithms providing a smooth transition from fully dynamic to totally fixed

A set of three allocation algorithms is proposed and analysed. As opposed to a number of allocation algorithms, whose performance is greatly dependent on the traffic profile, these techniques are dynamically adaptable to the change of the traffic load, combining the features of dynamic channel allocation and fixed channel allocation, migrating smoothly from one to another technique to give the best performance in any circumstances. Although the proposed strategies assign the channels in a fully dynamic fashion, this is carried out in a disciplined way so that channels are packed into reuse groups and the reuse distance is kept to a minimum, increasing the reuse efficiency. Copyright © 1999 John Wiley & Sons, Ltd.     

实施ERP促进企业实现现代化发展

企业资源计划作为企业管理思想的精髓,越来越被更多的企业所接受。企业资源计划(ERP)是信息化时代企业全部战略的关键部分。ERP的宗旨主要是将企业的各方面资源(人力、资金、信息、物料、设备、时间、技术)充分调配、平衡和优化,为企业提高资金运营水平、建立高效率供销链、减少库存、提高生产效率、降低成本、提高客户服务水平提供强有力的工具。现代企业管理与传统企业管理、先进与落后以及企业应用ERP与开展企业管理创新、推进企业管理现代化和提高企业竞争力之间存在着必然联系。当今时代,部分公司企业通过全面上线ERP系统,使流程得以优化;信息得以共享;物流过程得以监控。在管理效益及经济效益方面均取得了可观的成果,在激烈的市场竞争中能够得以立足。     

Designing a binary controller to enhance end-to-end congestion control

Active queue management (AQM) is proposed to enhance end-to-end congestion control through purposefully dropping packets in the intermediate nodes. In this letter, a novel packet dropping mechanism is developed through designing a binary controller applying the robust control theory. The new mechanism can simplify the manipulation on the AQM router so as to be helpful for implementing the high performance router. The numerical simulation results show that the binary controller can satisfy with the technical requirements for AQM     

Designing a Length-Modulated Azide Photocrosslinker to Improve the Stretchability of Semiconducting Polymers

To impart high stretchability to semiconducting polymers, researchers have used a photocrosslinking approach based on the nitrene chemistry of an azide-incorporated molecular additive. However, understanding of the molecular design of azide crosslinkers with respect to their effects on the electrical and mechanical properties of semiconducting polymer thin films is lacking. In this study, the effects of an azide photocrosslinker's molecular length and structure on the microstructural, electrical features, and stretchability of photocrosslinked conjugated polymer films is investigated. For a systematic comparison, a series of nitrene-induced photocrosslinkers (n-NIPSs) with different numbers of ethylene glycol repeating units (n = 1, 4, 8, 13) that bridge two tetrafluoro-aryl azide end groups is synthesized. Two semicrystalline conjugated polymers and two nearly amorphous conjugated polymers are co-processed with n-NIPSs and crosslinked by brief exposure to UV light. It is found that, among the synthesized n-NIPSs, the shortest one (1-NIPS) is the most efficient in improving the stretchability of crosslinked indacenodithiophene-benzothiadiazole films and that the improvement is achieved only with nearly amorphous polymers, not with semicrystalline conjugated polymers. On the basis of systematic studies, it is suggested that crosslinking density in amorphous regions is important in improving thin film stretchability.     

General approach to implementing analogue Viterbi decoders

Commercial realisations of analogue Viterbi decoder are available for magnetic read channels. However, these implementations are restricted to a particular coding scheme. The authors present a general approach to the implementation of analogue Viterbi decoders having arbitrary coding schemes. The proposed method exploits the ability of simple analogue circuits to perform the required mathematical functions. Simulation results are presented for a 0.8 μm BiCMOS process     

Characterization of a shielded transition to a dielectric waveguide

A shielded sub-mm/THz monolithic transition between a layered dielectric waveguide and a strip-ridge line is characterized using two different approaches: the integral equation-mode matching (IEMM) method and the finite difference time domain (FDTD) technique. While higher order modes are considered, a simple method for determining the transition's circuit model (i.e., two-port scattering matrix) from the IEMM results is implemented and the electrical performance is studied as frequency and conductor width are varied. The FDTD analysis gives further insight into the behavior of the transition in a very wide frequency range (0-540 GHz). The transition is found to be very efficient over a wide frequency band and a broad range of conductor widths     

一种模糊人工神经网络控制器的设计与研究

模糊控制与人工神经网络控制有许多相似之处，如何最大程度地发挥这两种控制的优点是一个很重要的问题。本文利用模糊控制算法快速、简便的优点弥补了人工神经网络算法复杂、缓慢的缺点，利用神经元特征函数使数控制更容易处理，以此为基础研制出一种模糊人工神经网络控制器。     

Designing a digital neurocomputer

In this article we discuss the flow of design for neural network hardware and go deeper into the design constraints and implementation possibilities. The performance measures and problems of different measurements are also discussed. It is noted that performance is one comparison criteria, but there are also many others, some of which are also discussed. In order to anchor the discussion to real life, the article includes a case study of our TUTNC neurocomputer. In addition, examples of commercial neural computing systems and their world wide web pages are given     

On computing and implementing the running bispectra

The paper extends recursion to bispectrum estimation problems and presents the systolic array implementation of the recursive higher order spectrum in which the bispectrum estimate is updated every data sample. Forward and reverse sequence running Fourier transforms are first systolically realized. The results are then used to drive a second systolic array, whose outputs represent the FT of the data third-order moment. The proposed systolic arrays have no global communications with a number of processing elements independent of the size of the employed 2D lag window     

运用可配置处理器内核的设计

虽然专用集成电路(ASIC)设计者不希望从零开始开发整个系统的每一个部分,但是他们必须确信整个系统和每个部分都按专用特性工作,即使第三方供应商可能提供系统的部件.目前,嵌入式系统是由几组工程师去设计的,因而出现硬件和软件分别开发的倾向,导致最终产品的工作特性偏离原来的指标.根据这种情况,使用第三方的知识产权(IP)只会增加多头开发和延长上市时间的可能性.     

Designing the CF-18 to be operationally ready

Primary Hornet program requirements include improved Operational Readiness (OR) and reduced Life Cycle Cost (LCC) compared to previous tactical aircraft. These requirements were translated into definitive and challenging reliability (R) and maintainability (M) design requirements. This paper describes the design and management techniques used to design superior R and M characteristics into the CF-18. A key to the Hornet's improved Operational Readiness is the firm R and M guarantees which will be demonstrated during the development program. Another important program management feature is the substantial R, M, LCC, and program management incentives (totalling $39M) which the contractor can earn. Principal CF-18 features designed to provide improved reliability include avionics equipment derating, improved cooling of the avionics, and reduced parts in the major subsystems such as radar, engine, and crew station. The Hornet's F404 engine also is designed for simplicity and reliability, being about four times as reliable as the J79. A major factor in achieving this improved CF-18 reliability is designing and testing to a realistic operational mission environment (OME). Most Hornet subsystems were required to complete reliability development testing utilizing this simulated OME. Maintainability features of the CF-18 design include improved equipment access, extensive built-in-test (BIT) and fault isolation, and an auxiliary power unit (APU) for ground maintenance. The Hornet's R and M performance during the flight test program demonstrates that the challenging reliability and maintainability design requirements are being met and often exceeded. The paper concludes with a summary of lessons learned during the Hornet program.     

应用LPM简化CPLD器件开发的探讨

随着EDA技术的发展,数字逻辑系统的规模越来越大、集成度也越来越高,而产品的上市时间日益缩短。面对如此压力,设计者单纯地应用硬件描述语言或原理图来应付,并不是一件简单的事情。通过引入支持LPM的EDA软件工具,设计者就可以快速地设计出结构独立且硅片利用率高的产品。以基于LPM ROM设计的7段显示译码电路为例,详细阐述了应用LPM模块简化CPLD器件开发的方法。     

不间断电源(UPS)的可靠性设计

介绍了与UPS相关的可靠性概念，阐述了UPS的可靠性设计方法，可靠性指标的预计方法，这些内容也可作为其它电源产品设计时的参考。     

结构振动试验转接器的设计及安装问题

一些产品及其相关部件在作振动试验时，由于产品的外形或特殊要求不能直接安装在振动台面上，需要通过特别设计的转接器（夹具）来进行连接，这种夹具实际上是一种附加结构，它作为台面与试件之间的中介，如设置不当将影响振动试验结果的可靠性。本文通过对某事例的分析与研究，从试验频带、允许误差、跟随条件以及安装共振频率等方面阐明与讨论了相关夹具的特性、设计原则与安装等问题。     

设计和仿真无线局域网设备天线

对带有开关电路的2.4 GHz极化分集印刷天线进行电磁场及电磁场与电路协同仿真 通过采用极化分集技术,可以用低成本PCB基片制造具有良好接收机性能的无线局域网设备(WLAN)天线.本文将描述如何使用最新的三维电磁场(EM)仿真工具来设计和仿真一对2.4GHz正交极化的印刷偶极子天线,同时预测表面电流和相关的远场辐射图.     

Realizing the transition to IPv6

While the details of the next-generation IPv6 protocol are now reaching maturity, the next hurdle in realizing the promises of IPv6 is the need for deployment on a wider scale. Previously, the migration from IPv4 to IPv6 has been considered nontrivial, a factor generally attributed to thwarting its success. However, with the advent of a number of new transitioning techniques the evolution to IPv6 is now becoming increasingly feasible. These transitioning techniques offer tunneling and translation solutions that enable the gradual introduction of IPv6 support into an existing IPv4 infrastructure. Nevertheless, it is not yet clear what form this evolution is likely to take, which phases are likely to exist, and how the transition process will proceed. This article examines existing IETF IPv6 transitioning mechanisms and discusses the key issues involved in IPv6 deployment. We examine those aspects that potentially affect the choice of transition mechanisms and look at what factors are likely to mould the evolutionary path     

An optoelectronic CMOS circuit implementing a simulated annealingalgorithm

An original optoelectronic implementation of simulated annealing is presented. A compact and simple optical system provides a chip with arrays of independent random noise sources. The silicon chip is composed of a mesh of computing cells. Each cell includes both analog and digital circuits and includes two photosensors. A detailed analysis of this cell is given including a presentation of the design constraints. A 4×4-cells prototype chip was implemented in a 1 μm CMOS digital technology and was successfully operated at 20000 iterations per second. The measurements and characterization of this chip made possible the successful design of a 600-cells chip also presented. These results demonstrate the video-rate application of simulated annealing to early vision tasks