CMOS Front-end Amplifier Dedicated to Monitor Very Low Amplitude Signal from Implantable Sensors

We describe in this paper a low-noise, low-power and low-voltage analog front-end amplifier dedicated to very low amplitude signal recording and processing applications. Our main focus is acquiring action potentials from peripheral nerves to recuperate lost functions in paralyzed patients. Low noise and low DC offset are realized using Chopper stabilization (CHS) technique. In addition, due to the use of a rail-to-rail input stage, low power supply (1.8 V) and wide common mode input range (0–1.8 V) are achieved also. It features a gain of 51 dB and a bandwidth of 4.5 kHz. The equivalent input noise is about 56 nV/ . The proposed preamplifier includes a matching clock generator, a 4th order continuous-time low-pass filter and an instrumentation amplifier. The proposed design has been implemented in 0.35 m double-poly n-well CMOS process with an active die area of 450 × 1150 m². The total data acquisition device consumes only 775 W.     

A Fully Integrated, Low Noise and Low Power BiCMOS Front-end Readout System for Capacitive Detectors

Bipolar transistors are interesting for low noise front-end readout systems when high speed and low power consumption are required. This paper presents a fully integrated, low noise front-end design for the future Large Hadron Collider (LHC) experiments using the radiation hard SOI BiCMOS process. In the present prototype, the input-referred Equivalent Noise Charge (ENC) of 990 electrons (rms) for 12 pF detector capacitance with a shaping time of 25 ns and power consumption of 1.4 mW/channel has been measured. The gain of this front-end is 90 mV/MIP (Minimum Ionisation Particle: 1 fC) with non-linearity of less than 3% and linear input dynamic range is MIP. These results are obtained at room temperature and before irradiation. The measurements after irradiations by high intensity pion beam with an integrated flux of pions/cm² are also presented in this paper.     

A CMOS Monolithic Image-Reject Filter

A CMOS inductorless image-reject filter based on active RLC circuitry is discussed and designed with the emphasis on low-noise, low-power, and gigahertz-range circuits. Two -enhancement techniques are utilized to circumvent the low characteristics inherent in the simple feedback circuit. The frequency tuning is almost independent of tuning, facilitating the design of the automatic tuning circuitry. The stability and the tuning scheme of the filter are also discussed. Simulations using 0.6 m CMOS technology demonstrate the feasibility of the tunable image-reject filter for GSM wireless applications. Simulation results show 4.75 dB voltage gain, 9.5 dB noise figure, and –20 dBm IIP3 at a passband centered at 947 MHz. The image signal suppression is 60 dB at 1089 MHz and the power consumption is 27 mW.     

Low-Voltage BiCMOS Four-Quadrant Multiplier and Squarer

A new low-voltage low-power BiCMOS four-quadrant multiplier using cascode NPN and NMOS pairs is presented. This circuit has been fabricated in a 1 m BiCMOS process. Experimental results show that for a power supply of ±1.5 V, the linear range is over ±0.8 V with the linearity error less than 2%. The total harmonic distortion is less than 2% with input range up to ±0.8 V. The measured –3 dB bandwidth of the proposed multiplier is about 10 MHz. Its static power dissipation is about 50 W. The squarer modified from the proposed multiplier has the input range up to ±1 V. This circuit is expected to be useful in low-voltage analog signal processing applications.     

A 4 GHz ΔΣ Fractional-N Frequency Synthesizer

A 4 GHz fractional-N frequency synthesizer for wireless communications applications is implemented in a 0.35 m BiCMOS process. The synthesizer achieves a close-in phase noise of –66 dBc/Hz. The key building blocks are an ECL multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation, a digital third-order MASH -modulator that controls the modulus of the prescaler, a very linear phase detector that enables the synthesizer to achieve a low close-in phase noise, and a chargepump providing a constant output current over a large output voltage range. The power dissipation of the synthesizer chip is 27.7 mW from a 2.7 V supply.     

Noise considerations for mixed‐signal RF IC transceivers

This paper discusses design tradeoffs for mixedsignal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multipath fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit nonlinearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design tradeoffs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixedsignal noise coupling and to model substrate noise effects are presented.     

A 5.8 GHz Low Noise Amplifier for Wireless LAN Applications in Silicon Bipolar Technology

A monolithic integrated low-noise amplifier for operation in the 5.8-GHzband is described. Two different versions have been implemented where the biasing wasadapted to allow operation over a different range of supply voltage. At 5-V, theamplifiers gain is about 17-dB, with a noise figure of 4.2-dB and 1-dB compressionpoint at –15-dBm input power. The circuits have been designed utilizing a0.6-micron silicon bipolar production technology, featuring npn transistors with and of about20-GHz.     

Compact High Gain CMOS Op Amp Design using Comparators

This paper discusses the design of high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 m nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of ±2.5 V. It occupies an area of 113 m×474 m.     

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability

In this paper, we design a rank-order filter with k-WTA capability for 1.2 V supply voltage. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover, without modifying the circuit, the k-WTA function can be easily configured. The circuit has been designed using a 0.5 m DPDM CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE post-layout simulation show that the response time of the circuit is 10 s for each rank-order operation, the input dynamic range is rail-to-rail, and the resolution is 10 mV for 1.2 V supply voltage. An experimental chip has been fabricated, in which accuracy of the comparator is measured as 40 mV for low-voltage operation. The dynamic power dissipation of the chip is 550 W.     

An Implantable CMOS Amplifier for Nerve Signals

In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 m CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 10 kHz bandwidth, a CMRR of more than 87 dB and a PSRR greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 4.8 nV/ . The amplifier power consumption is 275 W, drawn from a power supply; V _DD = –V _SS = 1.5 V.     

The Design of a 2-V 900-MHz CMOS Bandpass Amplifier

A 900 MHz low-power CMOS bandpassamplifier suitable for the applications of RFfront-end in wireless communication receiversis proposed and analyzed. In this design, thetemperature compensation circuit is used tostabilize the amplifier gain so that theoverall amplifier has a good temperaturestability. Moreover, the compact tunablepositive-feedback circuit is connected to theintegrated spiral inductor to generate thenegative resistance and enhance its value. The simple diode varactor circuit isadopted for center-frequency tuning. These twoimproved circuits can reduce the powerdissipation of the amplifier. An experimentalchip fabricated by 0.5 mdouble-poly-double-metal CMOS technologyoccupies a chip area of ; chip area. The measuredresults have verified the performance of thefabricated CMOS bandpass amplifier. Under a2-V supply voltage, the measured quality factoris tunable between 4.5 and 50 and the tunablefrequency range is between 845 MHz and 915 MHz. At , the measured is 20 dB whereas thenoise figure is 5.2 dB in the passband. Thegain variation is less than 4 dB in the rangeof 0–80^°C. The dc powerdissipation is 35 mW. Suitable amplifier gain,low power dissipation, and good temperaturestability make the proposed bandpass amplifierquite feasible in RF front-endapplications.     

Finite-Memory Systems

Let K be a field, k and n positive integers and let matrices with coefficients in K. For any function

A CMOS Offset Phase Locked Loop for a GSM Transmitter

This paper describes a CMOS offset phase locked loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of –163.5 dBc/Hz, the phase error of 0.66° rms, and the settling time of 40 s were achieved. The IC was implemented by using 0.35-m CMOS process. It takes 860 m×620 m of total chip area and consumes 17.6 mA with a 3.0 V power supply.     

A CMOS Low-Noise Instrumentation Amplifier Using Chopper Modulation

This paper describes a low-power, low-noise chopper stabilized CMOS instrumentation amplifier for biomedical applications. Low thermal noise is achieved by employing MOSTs biased in the weak/moderate inversion region, whereas chopper stabilization is utilized to shift 1/f-noise out of the signal band hereby ensuring overall low noise performance. The resulting equivalent input referred noise is approximately 7 nV/ ?{Hz}\sqrt{\rm Hz} for a chopping frequency of 20 kHz. The amplifier operates from a modest supply voltage of 1.8 V, drawing 136 A of current thus consuming 245 W of power. The gain is 72.5 dB over a 4 kHz bandwidth. The inband PSRR is above 90 and the CMRR exceeds 105 dB.     

Frequency Independent Nonlinear Feedforward Phase Estimator

The major focus of this work deals with fast and efficient phase estimation in an additive white Gaussian noise environment, where the received signal is a function of both phase and frequency error (, ). The paper proposes a modified version of the Viterbi and Viterbi phase estimator, and compares this modified version with the original. The comparison is performed in terms of two criteria – estimator variance and phase ambiguity resolution. Results suggest that the new estimator has a lower variance than the original technique when a frequency error is present. In addition, when the frequency is perfectly synchronized, the two estimators yield similar performances at moderate to high levels of signal-to-noise ratios. Phase ambiguity resolution by unique word preambles is also investigated. Although the new estimator requires additional processing to resolve ambiguity, its probability of resolution error is shown to be almost the same as for the V & V estimator.     

A Performance Analysis of Pragmatic MPSK TCM

The performance of 8-PSK, 16-PSK and 32-PSK TCM are examined in the additive white gaussian noise (AWGN), Rician fading and Rayleigh fading channels. The TCM is implemented using the Pragmatic Approach to TCM based on the common rate , constraint length 7, 64-state convolutional code. The analytic performance model has been enhanced to account for the unencoded bit(s) resulting from implementation of TCM using the Pragmatic Approach. Averaging of the Euclidean error weight profiles is also employed. The results provide an improved upper bound on published data from simulations and measurements. The results are then employed to facilitate the evaluation of a concatenated Reed-Solomon (RS) MPSK TCM code, as well as, TCM with diversity in the form of symbol repetition.     

Leveraged Current Mirror Op Amp

A small change to the standard current mirror op amp configuration is shown to improve performance, with few, if any, disadvantages. Adding a pair of fixed current sources allows reduced operating-point current in the output stage, while the resulting leveraging effect increases slew rate. For equal total power dissipation, the new configuration improves DC gain and gain-bandwidth (GBW) over conventional current-mirror and folded cascode op amps, as shown by hand analyses and SPICE simulations. Also, because of increased input stage transconductance, the new configuration reduces thermal and flicker noise.     

A 50-MHz CMOS amplifier channel for a laser radar

An integrated CMOS amplifier channel consisting of a transimpedance preamplifier, postamplifiers, and gain control circuitry has been designed for the receiver of a pulsed time-of-flight laser radar. The measurement results, a total transimpedance ofZ _t 250 k with a bandwidth ofBW 65 MHz and an input-referred noise current ofi _ni 7 pA/Hz, show that a range measurement resolution of centimeter/decimeter class could be achieved by detecting the edge of the received laser pulse.     

A scalable wireless virtual LAN

This paper presents a Wireless Virtual Local Area Network (WVLAN) to support mobility in IPoverATM local area networks. Mobility is handled by a joint ATMlayer handoff for connection rerouting and MAClayer handoff for location tracking, such that the effects of mobility are localized and transparent to the higherlayer protocols. Different functions, such as Address Resolution Protocol (ARP), mobile location, and ATM connection admission are combined to reduce protocol overhead and frontend delay for connectionless packet transmission in connectionoriented ATM networks. The proposed WVLAN, through the use of ATM technology, provides a scalable wireless virtual LAN solution for IP mobile hosts.