一种宽带多模数字抽取滤波器

提出了一种应用于连续时间Σ-Δ ADC的多模数字抽取滤波器。通过采用不同类型滤波器级联结构,合理分配不同级间下采样因子,有效降低了电路复杂度、面积和功耗。通过级间滤波器相互配合,实现了该滤波器的多带宽、多模式功能。基于65 nm CMOS工艺进行后端设计,仿真结果表明,该多模抽取滤波器的工作带宽为20~50 MHz,当工作带宽为20 MHz和50 MHz时,有效位数分别为10.64位和10.48位。     

Adaptive Laguerre-lattice filters

Adaptive Laguerre-based filters provide an attractive alternative to adaptive FIR filters in the sense that they require fewer parameters to model a linear time-invariant system with a long impulse response. We present an adaptive Laguerre-lattice structure that combines the desirable features of the Laguerre structure (i.e., guaranteed stability, unique global minimum, and small number of parameters M for a prescribed level of modeling error) with the numerical robustness and low computational complexity of adaptive FIR lattice structures. The proposed configuration is based on an extension to the IIR case of the FIR lattice filter; it is a cascade of identical sections but with a single-pole all-pass filter replacing the delay element used in the conventional (FIR) lattice filter. We utilize this structure to obtain computationally efficient adaptive algorithms (O(M) computations per time instant). Our adaptive Laguerre-lattice filter is an extension of the gradient adaptive lattice (GAL) technique, and it demonstrates the same desirable properties, namely, (1) excellent steady-state behavior, (2) relatively fast initial convergence (comparable with that of an RLS algorithm for Laguerre structure), and good numerical stability. Simulation results indicate that for systems with poles close to the unit circle, where an (adaptive) FIR model of very high order would be required to meet a prescribed modeling error, an adaptive Laguerre-lattice model of relatively low order achieves the prescribed bound after just a few updates of the recursions in the adaptive algorithm     

A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link

This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface,which is compliant with many serial communication specifications such as USB2.0,PCI-E2.0 and Rapid 10.The low and high frequency loops are merged to decrease the effect of delay between the two paths,in addition,the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain.The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces,which brings as much as 25 dB loss.The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation.In addition,AC coupling is adopted to suppress the common input from the forward stage.A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology.The actual area is 0.6×0.57 mm~2 and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss.The overall power dissipation is approximately 23.4 mW.     

High-speed CMOS continuous-time complex graphic equalizer formagnetic recording

A high-speed continuous-time CMOS analog adaptive equalizer for use in magnetic recording read channels is presented. The equalizer is implemented as the summation of several bandpass filters covering different frequency bands as in a graphic equalizer. The outputs from each filter are weighted by a complex coefficient and summed, which results in a linear combiner structure guaranteed to converge under least mean square (LMS) adaptation. System-level simulations of our “complex graphic equalizer (CGE)” show that its performance is comparable to that of a ten-tap finite impulse response (FIR) equalizer following a fourth-order low-pass filter when tested with two different sequence detectors: EPR4-MLSD and fixed delay tree search with decision feedback (FDTS/DF). A five-band tunable CGE has been fabricated using a 0.8-μm CMOS technology. The highest band of the fabricated CGE was centered at 80 MHz (corresponding to channel data rate of about 200 Msymbols/s). Measured dynamic range was 68 dB, and measured total harmonic distortion was only -75 dB while consuming 97 mW at 3.3 V. The measured CGE performance agreed within 0.2 dB with the simulation results for an FDTS/DF system with an ideal CGE operating at 2.5 user bits/PW50     

Digital Filters for Real-Time ECG Signal Processing Using Microprocessors

Traditionally, analog circuits have been used for signal conditioning of electrocardiograms. As an alternative, algorithms implemented as programs on microprocessors can do similar filtering tasks. Also, digital filter algorithms can perform processes that are difficult or impossible using analog techniques. Presented here are a set of real-time digital filters each implemented as a subroutine. By calling these subroutines in an appropriate sequence, a user can cascade filters together to implement a desired filtering task on a single microprocessor. Included are an adaptive 60-Hz interference filter, two low-pass filters, a high-pass filter for eliminating dc offset in an ECG, an ECG data reduction algorithm, band-pass filters for use in QRS detection, and a derivative-based QRS detection algorithm. These filters achieve real-time speeds by requiring only integer arithmetic. They can be implemented on a diversity of available microprocessors.     

A fully parallel CMOS analog median filter

A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on current saturating transconductance comparators, while the time delay is implemented using first-order all-pass filters. Both circuits allow modular expansion for the implementation of large median filter array processors. Based on these blocks, a new fast technique for parallel image processing is presented. It is shown that an image of 91/spl times/80 pixels can be processed in less than 8 /spl mu/s using an array of median filter cells. Experimental results of a test chip prototype in 2-/spl mu/m CMOS MOSIS technology are presented.     

Sorting continuous-time signals: analog median and median-typefilters

There are two natural orderings in signals: temporal order and rank order. There is no compelling reason to explore only one of these orderings, either in the discrete-time or in the continuous-time case. Nevertheless, the concept of rank order for continuous-time signals remains virtually neglected, which is in striking contrast to the discrete-time case: ranked order discrete-time filters, of which the running median is the most common example, have been intensively studied for three decades. The dependence of these nonlinear systems on the order statistics of the input samples stands in contrast with the tapped delay line filter, which depends on temporal order only. However, continuous-time signals can also be meaningfully sorted: a fact that is explored in this paper to define and study the analog median filter and other ranked-order filters. The paper introduces the basic tools needed to analyze and understand these continuous-time nonlinear filters (the distribution function and the sorting) and presents some of their properties in a tutorial way. The analog median filter is defined in terms of the (unique) nonincreasing left-continuous sorting. More general filters can also be defined, including filters similar to α-trimmed mean filters and L filters. These include filters that depend on one parameter and contain the running average and running median as special cases. The rate of convergence of the digital median filter to the analog median filter is discussed and related to the signal sampling period, the duration of the filter window, and the smoothness of the input signal. The paper introduces the concept of noise width and studies the effect of additive and multiplicative noise at the output of the analog median filter in terms of the noise width and the smoothness of the input signal     

A Fractionally Delaying Complex Hilbert Transform Filter

In this paper, we present a novel complex discrete-time filter. This is a fractionally delaying (FD) Hilbert transform filter (HTF) further called the FD HTF. The filter is based on a pair of rotated variable fractional delay (VFD) filters. It is capable of performing the Hilbertian as well as VFD filtering of the incoming discrete-time signal at the same time. Thus, one can substitute a cascade of the HTF and the VFD filters with an aggregated filter proposed here. The technique is simple to implement. The advantages lie in lower total delay introduced by the compound filter and in a modular structure. The rotated VFD filters in the pair differ only in the value of one parameter - the VFD. The proposed FD HTF can be applied to adaptive quadrature sub-sample estimation of delay.     

An artificial intelligence approach to active filter synthesis

This paper deals with a novel active filter synthesis method using artificial intelligence (AI). The AI-based synthesis methodology uses original analog circuit representation performed by a Prolog backward-chaining inference mechanism. Circuit representation is specified as an analog circuit language to describe filter topologies, performance characteristics, and subcircuits. Synthesis is organized as a Prolog searching program based on backward-chaining strategy to transform input specifications into an appropriate filter structure. The Prolog program performs symbolic equation transformations to proper filter transfer characteristics. The proposed synthesis methodology has been developed for integrated continuous-time filter structures using operational transconductance amplifiers and capacitors to realize tunable and active C filters. A synthesis program has been implemented in Turbo Prolog on an IBM PC AT computer, and a filter example is presented demonstrating the use of the program.This paper was supported by the Ministry of Education of Poland Grant CPBP 02.14.     

Power and Area-Efficient Adaptive Equalization at Microwave Frequencies

We present a low power analog adaptive equalization technique suitable for combating inter-symbol-interference at very high data rates. The proposed technique, which we term the lumped parameter equalizer, addresses several of the problems associated with conventional microwave equalizers based on the tapped delay line structure. The theory is given, and simulation results comparing it with the performance of ideal tapped delay line filters are shown. Circuit implementations are discussed, along with the effect of nonidealities on equalizer performance.      

Widely programmable high-frequency continuous-time filters indigital CMOS technology

We present design considerations for programmable high-frequency continuous-time filters implemented in standard digital CMOS processes. To reduce area, accumulation MOS capacitors are used as integrating elements. The filter design problem is examined from the viewpoint of programmability. To allow frequency scalability without deterioration of noise performance and of the frequency response shape, we employ a technique called “constant-capacitance scaling,” which assures that even parasitic capacitances remain invariant when transconductors are switched in and out of the filter. This technique is applied to the design of a programmable fourth order Butterworth continuous-time filter with a bandwidth programmable from 60 to 350 MHz implemented in a 0.25-μm digital CMOS process. The filter has a dynamic range of 54 dB, dissipates 70 mW from a 3.3-V supply, and occupies an area of 0.15 mm²     

Active cancellation of acoustic noise using a self-tuned filter

In an increasingly noisy society, methods of reducing noise are becoming more important. This work proposes an analog electroacoustic circuit for active control of narrow-band low-frequency acoustic noise using adaptive filtering techniques. The circuit aims at producing antinoise, which is acoustically added to the disturbing noise to produce an error signal that is fed back to the circuit. The proposed circuit is a modified Kerwin-Huelsman-Newcomb biquad filter that tunes itself to the incoming noise frequency using the zero tuning techniques. The circuit was implemented on a printed circuit board and it was successful in reducing noise by 15-20 dB in open space. Active noise control specifically for narrow-band noise cancellation using adaptive analog filters seems to be a better solution than its digital signal processing counterpart in speed, cost, and robustness.     

PCM编解码器中高性能开关电容滤波器设计

基于PCM(Pulse-Code-Modulation, 脉冲编码调制)语音编解码器设计了其中的发送端开关电容滤波器,包括高通滤波器和低通滤波器.对高通滤波器和低通滤波器的设计分别采用两种不同的方法--级联法和梯形法,然后把这两部分级联起来就实现了带通滤波器.仿真结果表明开关电容带通滤波器通带波纹0.24 dB,阻带衰减37 dB,对60 Hz以下频率的衰减大于32 dB,动态范围达到90 dB,满足D4信道处理单元发送滤波器的技术要求[1].设计的开关电容滤波器在一款PCM语音编解码芯片中成功实现.     

A mixed-signal approach to high-performance low-power linearfilters

We present a new approach to the design of high-performance low-power linear filters. We use p-channel synapse transistors as analog memory cells, and mixed-signal circuits for fast low-power arithmetic. To demonstrate the effectiveness of our approach, we have built a 16-tap 7-b 200-MHz mixed-signal finite-impulse response (FIR) filter that consumes 3 mW at 3.3 V. The filter uses synapse pFETs to store the analog tap coefficients, electron tunneling and hot-electron injection to modify the coefficient values, digital registers for the delay line, and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap coefficients. The measured maximum clock speed is 225 MHz; the measured tap-multiplier resolution is 7 b at 200 MHz. The total die area is 0.13 mm². We can readily scale our design to longer delay lines     

Adaptive cascade networks for deep nulling

Although the analogy between array antennas and tapped delay line filters is well established, there is nothing in antenna theory that is quite the same as the simple cascade connection of two or more filter sections. By applying adaptive techniques, however, it is possible to set up a cascade beam forming network having most of the advantages of the cascade filter connection. In particular, it is possible to provide deep nulls for the suppression of powerful jammers despite the presence of unavoidable errors in the parameter settings. Our calculations indicate that a subsidiary advantage is the fact that the cascade network will settle more rapidly than a conventional adaptive network when the eigenvalues are widely separated.     

A class of predictive analog filters for sensor signal processingand control instrumentation

A class of analog continuous-time filters is introduced, having predictive properties for specified narrow-band signal models, such as low-order polynomials or sinusoids. Such filters are designed by using model transfer functions designed in the discrete-time domain. Z-to-s-domain mapping is done using the inverse bilinear transformation. The analog filters are implemented with active-RC structures, using the state-variable structure for biquads and a single-op-amp structure for real poles and zeros. The application examples include a filter for zero-crossing detectors, polynomial predictors for sensor signal smoothing, and an optimized sixth-order ramp-tracking filter for anti-aliasing and anti-imaging in digital signal processor (DSP) systems where high selectivity is required     

一种抑制直扩通信窄带干扰的新型非线性自适应预测滤波器

为了更有效地抑制直接序列扩频通信中的窄带干扰,论文提出了一种非线性Laguerre滤波抑制直扩频通信窄带干扰的方法,给出相应的自适应算法。该方法利用具有IIR和FIR滤波器特点的Laguerre时延单元构造非线性自适应预测滤波器。该方法可以使预测器的记忆深度与预测器的阶数解偶,以更少的阶数达到更优的抑制性能。仿真实验结果表明:与Vijayan和Poor传统非线性自适应预测滤波器相比,该滤波器能够保证均方误差的收敛稳定性,并能在信噪比改善提高12dB的前提下,使滤波器阶数降低为原来的1/3~1/5,具有一定的现实意义。     

A 3-V continuous-time filter with on-chip tuning for IS-95

This paper describes a low-voltage channel selection analog front end with continuous-time low-pass filters and on-chip tuning for a receiver in an IS-95 cellular phone. The filters were realized as balanced seventh-order elliptical g_mC filters to achieve low current consumption. The transconductors were realized by using second-generation current conveyors (CCII) and resistors to achieve good intermodulation distortion performance. A novel CCII circuit topology was developed to fulfil the low supply-voltage requirement. The cutoff frequency tuning was implemented with capacitance matrices and a time-domain master-slave tuning circuit     

Frequency-warped filter banks and wavelet transforms: adiscrete-time approach via Laguerre expansion

We introduce a new generation of perfect-reconstruction filter banks that can be obtained from classical critically sampled filter banks by means of frequency transformations. The novel filters are Laguerre type IIR filters that can be directly derived and designed from ordinary orthogonal or biorthogonal filter banks. Generalized downsampling and upsampling operators based on dispersive delay lines are the building blocks of our structures. By iterating the filter banks, we construct new orthogonal and complete sets of wavelets whose passbands are not octave spaced and may be designed by selecting a single parameter     

Automatic Tuning System for Integrator-Based Continuous-Time Filters

This paper proposes an automatic tuning system to adjust frequency characteristics of integrated continuous-time filters especially at high frequencies. Frequency characteristic deterioration of a filter using integrators with electrically controllable unity-gain frequencies can be easily evaluated and compensated even when they are affected by deviations of element values and parasitic elements. The compensation requires detection of both frequency and excess phase shifts of the integrators. Their two values are electrically detected by two detection systems usually used in the conventional frequency tuning system. The proposed system is stable, simple and easy to be implemented on an integrated circuit. As an example a 4th-order biquad bandpass filter with 10 MHz center frequency, 2 MHz passband width, and 0.5 dB passband ripples is designed using a bipolar process. Simulation results by SPICE show the effectiveness of the proposed system.