Current-Mode High Output Impedance Sinusoidal Oscillator Configuration Employing Single FTFN

In this study, a general current-mode high output impedance sinusoidal oscillator configuration is proposed. The proposed oscillator configuration uses a single four terminal floating nullor (FTFN), two capacitors and five resistors. The oscillator configuration exhibits high output impedance which makes easy to drive loads without using any buffering devices and provide non-interactive control of oscillation condition and oscillation frequency. The proposed topology also yields single frequency oscillators with reduced number of passive components. All of the proposed oscillators permit good frequency stability and exhibit low active and passive sensitivities. Theoretical analysis is verified with experimental results.     

Systematic Design of Companding Systems by Component Substitution

A design method for externally linear, internally nonlinear systems is presented which allows them to be derived from externally equivalent systems in a systematic way and with a minimum synthesis effort, just performing a simple component-to-component substitution. As a particular case, the synthesis of the most popular versions of voltage companding systems from externally equivalent Gm-C systems is addressed. The practical design of companding systems based on the MOS square law (Square-Root Domain systems) is fully illustrated along the complete design flow, from the Gm-C prototype to silicon. These systems, feasible in CMOS technologies and formerly difficult to obtain due to the inherent complexity of existing synthesis methods, particularly benefit from the simplicity of the proposed approach. Experimental results for two versions of tunable Square-Root Domain biquadratic filters and oscillators thus obtained and fabricated in a 2.4-m CMOS process are presented, featuring favorable tunability and low THD.     

A log-domain multiphase sinusoidal oscillator

A novel multiphase sinusoidal oscillator topology, realized by employing the concept of log-domain filtering, is introduced in this paper. The realization of the oscillator's topology is achieved by establishing a loop constructed from an inverting and non-inverting log-domain lossy integrators. Attractive benefits offered by the novel topology are the ability for independent electronic tuning of the condition of oscillation and the frequency of oscillation, and the ability for realizing both even- and odd-order oscillators without any manipulation of the basic configuration. The operation of the proposed oscillator has been verified through simulation results.     

New Single-Resistance-Controlled Oscillator Configurations Using Unity-Gain Cells

Unity-gain voltage followers and unity-gain current followers have attracted attention in the recent literature in the context of analog signal processing as well as signal generation because of the advantages of wider bandwidth and low power consumption of these active elements as compared to other more complex building blocks. Motivated by these advantages, followers have been used as alternatives to other more complex building blocks in the realisation of filters, oscillators and more recently, in impedance converters. Although some configurations for realizing sinusoidal oscillators using unity-gain voltage/current followers have been described in the earlier literature, only one of them is a second-order single-resistance-controlled oscillator but requires as many as eight followers. This paper derives, through a state-variable synthesis approach, a number of new follower-based single-resistance-controlled oscillators requiring a much smaller number (only two to four) of followers. The new circuits are shown to possess a number of other interesting features. The workability of the new structures has been confirmed by SPICE simulation results using CMOS-based followers. S.S. Gupta was born on July 2, 1962 at Kalinjer (Banda), UP, India. He obtained B.E. in 1982 (from Government Engineering College, Rewa, India) and M.E. (Honors) in 1988 (from Motilal Nehru National Institute of Technology, Allahabad, India)- both in Electrical Engineering. He worked as a Lecturer in Electrical Engineering Department of Motilal Nehru National Institute of Technology, Allahabad during 1984–85. He worked as Design Engineer at Bharat Heavy Electricals Limited, Jhansi during 1985–87 before joining Ministry of Industry, Govt. of India in 1988 where he worked as Assistant Development Officer till June 2000. Since June 2000, he is working as Assistant Professor in the Division of Electronics and Communication Engineering, Netaji Subhas Institute of Technology, New Delhi. His teaching and research interest are in the areas of Network Synthesis and Filter Design, Analog Integrated Circuits and Signal Processing, Bipolar and MOS current mode circuit design and chaotic nonlinear circuits and he has published thirteen papers in various international journals of repute. Raj Senani was born on March 14, 1950 at Budaun, UP, India. He received B.Sc. from Lucknow University, B.Sc. Engg. from Harcourt Butler Technological Institute, Kanpur, M.E. (Honors) from Motilal Nehru National Institute of Technology, Allahabad and Ph.D. in Electrical Engg. from the University of Allahabad. Dr. Senani held the positions of Lecturer (1975–1986) and Reader (1987–1988) at the Electrical Engineering Department of M.N.R. Engineering College, Allahabad. He joined the Electronics and Communication Engineering (ECE) Department of the Delhi Institute of Technology (DIT), Delhi in 1988 as an Assistant Professor. He became a Professor in 1990. Since then, he has served as Head, ECE Department (1990–1993, 1997–1998), Head Applied Sciences (1993–1996), Head, Manufacturing Processes and Automation Engineering (1996–1998), Dean Research (1993–1996), Dean Academic (1996–1997), Dean Administration (1997–1999), Dean Post Graduate Studies (1997–2001), Director, Netaji Subhas Institute of Technology (NSIT) during June 1996–September 1996, February 1997–June 1997 and May 2003–January 2004. He is currently functioning as Head, Division of ECE at NSIT (2000-till date). Professor Senani's teaching and research interests are in the areas of Circuits, Systems and Signal Processing, Bipolar and CMOS analog integrated circuits, Current-mode Signal processing, Electronic Instrumentation, Chaotic nonlinear circuits and Log-domain/Translinear circuits. He has authored or co-authored 100 research papers in the above areas which have been published in IEEE (USA), IEE (UK) and other international journals of repute. He served as an Honorary Editor of the Research Journal of the Institution of Electronics and Telecommunication Engineers (IETE, India) during 1990–1995, in the area of Circuits and Systems and has been a Member of the Editorial Board of the IETE Journal on Education since 1995. He has been functioning as Editorial reviewer for a number of IEEE (USA), IEE (UK) and other international journals of repute. He is currently serving as an Associate Editor for the Journal on Circuits, Systems and Signal Processing, Birkhauser Boston (USA). He is listed in several editions of Marquis' Who's Who in the World, Marquis' Who's Who in Science and Engineering, Marquis' Who' Who in Finance and Industry (all published from N.J., USA during 1998–2004); 2000 Outstanding Scholars of the 21st Century and Outstanding people of the 20th Century (both published by International Biographical Centre, Cambridge); Indo-American Who's Who (2001), Indo-Asian Who's Who (2003), Asia's Who's Who of Men & Women of Achievement (2003), Asia/Pacific Who's Who (2004) and a number of other international biographical directories.     

瞬时缩展微分电路实现小波函数的方法

瞬时缩展电路又称对数域电路,是近些年来国际学术界用来发展低电压低功率模拟VLSI的一个重要关键技术。其有效地解决了低电压电源、噪声和高频性能的矛盾,使电路在最小电源电压下获得适当的动态范围和低功率。他是实现小波变换芯片的重要途径之一。提出了一种微分电路,采用瞬时缩展电路技术实现。对其工作原理进行了分析,并利用该技术实现了一种小波函数,为小波实时信号处理的VLSI综合提供了一条新的途径。     

一种降低OFDM系统PAPR的改进压扩方法

正交频分复用（OFDM）技术是一种多载波调制方式。作为第四代移动通信系统的核心技术,OFDM己成为当今高速无线通信领域的研究热点。正交频分复用（OFDM）系统存在高峰值平均功率比（PAPR）问题,这一问题会导致系统性能降低,为其实用化设置了障碍。文中研究了一种改进的降低PAPR的非线性压缩与扩展算法,可以得到更好的PAPR性能。该方法的特点在于采用一种计算复杂度较低的非线性压扩函数,同时融合了叠加训练序列方法的改进非线性压扩算法,从而有效地降低系统PAPR。理论研究和仿真结果表明,与传统方法相比,所提出的改进压缩与扩展方法可以在降低系统复杂度的同时得到更好的PAPR性能。     

Current-Mode Multiplier/Divider Circuits Based on the MOS Translinear Principle

In this paper, novel current-mode analog multiplier/divider circuits based on a pair of voltage-translinear loops are presented, featuring simplicity, precision and wide dynamic range. They are suitable for standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Two versions, based on stacked and up-down voltage-translinear loops, respectively, are described. Experimental results are provided in order to verify their correct operation.     

一种用于AC-DC的可修条振荡器的设计

该文主要设计了一种用于AC-DC电源管理芯片中的频率为100khz的可修条高精度振荡器,它以比较器为核心电路,并利用系统内部产生的恒流源对电容进行充放电,经过控制电路的作用后,使输出波形为线性度很好的三角波。通过HSPICE的仿真结果表明,三角波具有较好的线性度,其信号振荡频率随电源电压和温度的波动变化较小,性能良好,...     

降低OFDM峰均比的压扩变换方法研究

基于压扩变换的OFDM信号PAPR抑制方法具有实现简单、抑制效果明显的优点。对现有压扩变换PAPR抑制方法进行了分析和研究,并在此基础上,提出了一种基于均匀分布的压扩变换方法。该方法能够将任何分布的调制信号均变为均匀分布。仿真结果表明,与现有方法相比,该方法抑制PAPR的效果较为明显,且易于实现,具有较好的实用性。     

A Low-Voltage Fully Differential MOSFET-C Bandpass-Based Voltage-Controlled Oscillator for Frequency Tuning

A low-voltage fully differential MOSEFT-C bandpass-based voltage-controlled oscillator for the purpose of frequency-tuning of filters is proposed. This oscillator is guaranteed to start oscillating and provide well-controlled amplitude. Experimental filters and the filter tuning circuit are designed to demonstrate its use. The performance of this circuit is shown by experimental results.     

Winner-Take-All Class AB Input Stage

A novel technique to implement class AB differential amplifier input stages is proposed. It is based on the use of Winner-Take-All circuits for achieving dynamic current boosting, and is well suited for low-voltage operation. Experimental measurements of an OTA using this technique, fabricated in a 0.5-μm CMOS technology, show a slew rate of 92 V/μs for an 80-pF load and 120 μW of static power consumption.     

An Electronically Tunable Sinusoidal Oscillator Suitable for High Frequencies Operation Based on a Single Dual-Output Variable-Gain CCII

A novel sinusoidal oscillator, constructed from only one CCII with variable current gain, is presented and analyzed. The oscillator provides electronically tunable frequency, with good stability and low sensitivities, while variation of current gain does not affect the condition of oscillations. By the proposed circuit topology, the parasitic elements which exist at current conveyor terminals are absorbed by the external components and their action is diminished. Moreover, the parasitic poles of the current conveyor are taken into account and compensation technique and design criteria are applied, so that the oscillator can operate above 35 MHz.     

基于瞬时自相关的信号分选方法研究

信号的分选和识别是信号处理系统的重要部分,在信号处理中占有举足轻重的作用.目前,空间中的信号环境越来越复杂,对信号的分选和识别而言,难度越来越大.通过对线性调频信号与相位编码信号的分析,讨论了一种基于瞬时自相关的瞬时频率提取的方法,并在后面用匹配滤波器进行信号的匹配.这种方法是对信号分选方法的一种新的尝试.     

降低OFDM信号峰均功率比的压扩方法研究

本文通过理论推导和分析,确定了基于误差函数降低正交频分复用(OFDM)系统峰均功率比的非线性压扩方法中两个关键参数的取值,修正了以前的结果,并在此基础上提出了一种新的压扩函数来降低OFDM系统的峰均功率比.理论分析和仿真结果表明,新的压扩方法能够在保持原信号平均功率不变的情况下使峰均功率比降低到7.8dB以下,并且系统具有较好的误比特率性能.     

Novel Architectures of Class AB CMOS Mirrors with Programmable Gain

Two schemes for power-efficient gain-programmable V-I conversion based on class AB CMOS mirrors are introduced. The proposed topologies also allow for high-speed gain-programmable precision rectification. Experimental results from a test chip prototype in 0.5- m CMOS technology with ±1 V supplies are shown that validate the proposed circuits.     

基于瞬时参数的调制识别算法

通信信号的调制识别是目前研究的热点问题.文章通过提取信号的瞬时参数,构造识别特征,成功识别出AM、DSB、LSB、USB、FM信号,并给出了仿真结果.     

基于电流模式施密特触发器的CCCII±张弛振荡器

提出了一种基于电流模式施密特触发器的CCCII±弛振荡器。该电路的振荡信号周期可由接地电容线性改变，而频率则与CCCII＋偏置电流成正比，PSPICE仿真结果与理论分析相符。     

New CMOS Class AB Transmitter for 10 Gb/s Serial Links

This paper presents a new fully differential CMOS class AB transmitter for 10 Gb/s serial links. The transmitter consists of a fully differential multiplexer, a rail-to-rail configured pre-amplification stage, and a push-pull output stage. The multiplexer achieves a high multiplexing speed by using modified pseudo-NMOS logic where pull-up networks are replaced with self-biased active inductors. The rail-to-rail configured pre-amplification stage with active inductors amplifies the signals from the multiplexer. The fully differential output current is generated by a class AB output stage operated in a push-pull mode. High data rates of the transmitter are obtained by ensuring that the transistors in both the pre-amplification and output stages are always in saturation and the voltage swing of all critical nodes is small. The fully differential configuration of the transmitter effectively suppresses common-mode disturbances, particularly those coupled from the power and ground rails, the electro-magnetic interference exerted from channels to neighboring devices is also minimized. The transmitter minimizes switching noise by drawing a constant current from the supply voltage. The transmitter has been implemented in TSMC 0.18 μm 1.8 V 6-metal CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3 device models. Simulation results demonstrate that the transmitter provides a 5 mA peak-to-peak differential output current with 100 ps eye-width and >5 mA eye-height at 10 Gb/s. The transmitter consumes 18 mW with a total transistor area of 100 μm² approximately. Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995, and the M.A.Sc. degree in Electrical and Computer Engineering from Ryerson University, Toronto, Ontario, Canada in 2004. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. From 2002 to 2004, she was a research assistant and a M.A.Sc. student with the Microsystem Research Laboratory in the Department of Electrical and Computer Engineering at Ryerson University. She is now with Intel Corp., CA. as an IC design engineer. Her research interests are in analog CMOS circuit design for high-speed data communications. Jean Jiang was awarded the Ontario Graduate Scholarship in 2003–2005 for academic excellence. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the M.A.Sc. degree in chemical engineering and Ph.D. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Ontario, Canada, and Lambton College of Applied Arts and Technology, Sarnia, Ontario, Canada. He was with Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer during 1989–1994. Since 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book Computer Methods for Analysis of Mixed-Mode Switching Circuits (Springer-Verlag, 2004, with Ajoy Opal). Dr. Yuan received the Ryerson Research Chair award from Ryerson University in Jan. 2005, the Research Excellence Award from the Faculty of Engineering and Applied Science of Ryerson University in 2004, the post-graduate scholarship from Natural Science and Engineering Research Council of Canada during 1997–1998, and the Teaching Excellence Award from Changzhou Institute of Technology in 1988. Dr. Yuan is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

基于电流模式施密特触发器的CCCⅡ±张弛振荡器

提出了一种基于电流模式施密特触发器的CCCⅡ±张弛振荡器.该电路的振荡信号周期可由接地电容线性改变,而频率则与CCCⅡ±的偏置电流成正比,PSPICE仿真结果与理论分析相符.     

基于局域波的非参数瞬时频率估计

对于频率缓变的单一分量信号叠加噪声的情况,根据其瞬时频率中真实瞬时频率占主导趋势的特点,先使用平滑相位差分法——极大似然法估计噪声信号的瞬时频率,用局域波分解法求极大似然法估计瞬时频率的趋势项,从而得到与理论瞬时频率相符的结果,与其他的瞬时频率估计方法相比,本方法具有精度高、计算量小的优点.