Wafer level and flip chip design through solder prediction modelsand validation

In flip chip package applications, bumped dies are flip-chip assembled to substrate metal pads creating joints that serve electrically and mechanically. Resulting solder joint profiles are defined by the solder bump volume, the under bump metallurgy (LTBM) area, and the substrate metal pad size and shape. Solder bump height and diameter was predicted by the geometrical truncated sphere model and surface evolver model at the wafer level, using the known solder volume deposited by stencil printing method. The surface evolver model was used to predict the assembled solder joint height, gap height, collapse height, and maximum bump diameter of flip chip assemblies. In turn, substrate pads were fine-tuned to achieve required gap heights. Collapse heights provided the means to develop assembly tolerances and relative risk of bridging was determined from knowledge of resulting bump diameters. Through validated design of the stencil printing technology and prediction of realistic bump and assembly solder geometries, the results are improved processes and die level design and assembly. Optimized design parameters are incorporated and accurately represented in simulation and experimentally validated with assemblies     

Modeling and sensitivity analysis of circuit parameters for flip-chip interconnects using neural networks

This paper presents a neural network-based technique for modeling and analyzing the electrical performance of flip-chip transitions. A lumped element model using a simple pi equivalent circuit is used to characterize the electrical properties of the flip-chip bond. Statistical experimental design is used to extract the electrical parameters for flip-chip characterization from measurements and full-wave simulations up to 35 GHz. The extracted data is used to train back-propagation neural networks to obtain an accurate model of the pi equivalent circuit components and s-parameters as a function of layout parameters. The prediction error of the models is less than 5%. The models are used to obtain response surfaces for the entire range of variation of layout parameters. The neural network models are subsequently used to perform sensitivity analysis. All electrical parameters are shown to be sensitive to conductor overlap. The inductance and capacitance of the pi equivalent circuit are sensitive to the bump height. However, the return loss (S₁₁) is insensitive to the change in bump height. The coplanar waveguide width has a significant impact on the s-parameters, as it affects the matching of flip-chip transitions     

Impact of probing procedure on flip chip reliability

Probe-after-bump is the primary probing procedure for flip chip technology, since it does not directly contact the bump pad, and involves a preferred under bump metallurgy (UBM) step coverage on the bump pads. However, the probe-after-bump procedure suffers from low throughputs and high cost. It also delays the yield feedback to the fab, and makes difficult clarification of the accountability of the low yield bumped wafer between the fab and the bumping house. The probe-before-bump procedure can solve these problems, but the probing tips may over-probe or penetrate the bump pads, leading to poor UBM step coverage, due to inadequate probing conditions or poor probing cards. This work examines the impact of probing procedure on flip chip reliability, using printing and electroplating bumpings on aluminum and copper pads. Bump height, bump shear strength, die shear force, UBM step coverage, and reliability testing are used to determine the influence of probing procedure on flip chip reliability. The experimental results reveal that bump quality and reliability test in the probe-before-bump procedure, under adequate probing conditions, differ slightly from the corresponding items in the probe-after-bump procedure. UBM gives superior step coverage of probe marks in both probe-before-bump and probe-after-bump procedures, implying that UBM achieves greater adhesion and barrier function between the solder bump and the bump pad. Both printing and electroplating bump processes slightly influence all evaluated items. The heights of probe marks on the copper pads are 40–60% lower than those on the aluminum pads, indicating that the copper pad enhances UBM step coverage. This finding reveals that adequate probing conditions of the probe-before-bump procedure are suited to sort flip chip wafers and do not significantly affect bump height, bump shear strength, die shear force, or flip chip reliability.     

Characterization of flip chip bonded structure with Cu ABL power bumps

Power distribution in both 2D and 3D integrated circuit (IC) devices becomes one of the key challenges in device scaling, because the on-chip power dissipation becomes significantly severe and causes thermal reliability issues. In this study, the process solution to resolve the on-chip power dissipation by improving power distribution was investigated through newly designed power bumps called ABL (advanced bump layer) bumps. Rectangular-shaped Cu ABL bumps were fabricated and bonded on Si substrate using flip chip bonding process. The bump height difference in signal and ABL power bumps, bonding interface, and electrical resistivity of flip chip bonded structure were evaluated. The lowest electrical resistivity of Cu ABL bump system was estimated to be 3.3E−8 Ω m. The process feasibility of flip chip bonded structure with Cu ABL bumps has been demonstrated.     

MECHATRONICS 2000. Seventh Mechatronics Forum InternationalConference and Mechatronics Education Workshop

The following topics are dealt with: flip chip solder joint quality inspection; direct chip attach packaging for microsystems; reliability analysis of no-underfill flip chip package; ASIC/memory integration by system-on-package; wafer-level and flip chip designs through solder prediction models and validation; reliability evaluation of under bump metallurgy in two solder systems; a method to improve the efficiency of the CMP process; thermal and reliability analysis of packaging systems     

倒装焊对探测器频响特性影响的理论分析及工艺优化

针对光探测器在倒装焊过程中频响性能恶化的问题,建立等效电路模型分析出其原因,并通过优化倒装焊工艺条件予以有效解决。该电路模型包括探测器芯片、过渡热沉和倒装焊环节三个部分。基于倒装焊后探测器的S11参数和频响曲线提取出倒装焊环节特征参数,确认焊点接触电阻过大是引起探测器频响下降的主要原因。通过优化倒装焊工艺条件,有效减小了焊点接触电阻,基本消除了倒装焊对探测器频响特性的影响。     

Electrical Characteristics of the Three-Dimensional Interconnection Structure for the Chip Stack Package with Cu through Vias

A chip stack specimen of a three-dimensional (3-D) interconnection structure with Cu vias of 75-μm diameter, 90-μm height, and 150-μm pitch was successfully fabricated using via hole formation with deep reactive ion etching (RIE), Cu via filling with pulse-reverse pulse electroplating, Si thinning, Cu/Sn bump formation, and flip-chip bonding. The contact resistance of a Cu/Sn bump joint and Cu via resistance could be determined from the slope of the daisy chain resistance versus the number of bump joints of the flip-chip specimen containing Cu vias. When the flip chip was bonded at 270°C for 2 min, the contact resistance of a Cu/Sn bump joint of 100-μm diameter was 6.74 mΩ, and the resistance of a Cu via of 75-μm diameter and 90-μm height was 2.31 mΩ. As the power transmission characteristics of the Cu through via, the S₂₁ parameter was measured up to 20 GHz.     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

Solder bump reliability-issues on bump layout

The reliability of solder bumps in a typical under-filled flip chip package is calculated three-dimensionally (3-D) using the finite element method and a viscoplastic material model for the solder. Simulations are performed with varying bump placement, underfill coverage and board size. The average plastic work in a bump is used to compare the loading and bump reliability of different geometries. The results show possible improvements over the traditional bump placement by changing the geometry of the interconnects on the flip chip package. Three changes that improve reliability are discussed in detail: the redistribution of bump rows, the reduction of board size and the inclusion of heat transfer bumps.     

Design of Solder Joint Structure for Flip Chip Package with an Optimized Shear Test Method

The structure of flip chip solder bumps was optimized in terms of shear height and shear speed using a shear test method with both experimental investigation and nonlinear, three-dimensional, finite element analysis being conducted. A representative, Pb-free solder composition, Sn-3.0Ag-0.5Cu, was used to optimize the shear test of the flip chip solder joints. Increasing the shear height, at a fixed shear speed, decreased the shear force, as did decreasing the shear speed, at a fixed shear height. These experimental and computational results supported the recommendation of low shear height and low shear speed condition for the shear testing of flip chip solder bumps. This optimized shear test method was applied to investigate the effect of various heights of mini bumps on the shear force of the solder joints. The shear force increased with increasing Ni-P mini bump height.     

Growth prediction of tin/copper intermetallics formed between 63/37 Sn/Pb and OSP coated copper solder pads for a flip chip application

This study quantifies the effect of temperature and time on the growth of Cu-Sn intermetallics, specifically for flip chip/ball grid array packaging technology. The activation energy and the growth rates were determined for solid state diffusion, after the initial assembly reflow(s). Three different types of solder joints were investigated. 1) BGA 63/37 solder joints which were formed by a standard convection oven attach of 30 mil (760 /spl mu/m)diameter solder spheres to OSP protected, Cu plated ball pads of an organic flip chip substrate. The ball pads are solder mask defined and of 0.635 mm nominal diameter. 2) Flip chip bump pad solder joint consisting of 63/37 eutectic solder bumped die attached to a nonsolder mask defined, OSP protected, Cu plated pad of the flip chip substrate. The flip chip bumps on the die are created by screen printing solder paste on the die pads and subsequent reflow attach, by a standard convection oven to the die under bump metallurgy (UBM). The nominal die UBM pad diameter is 0.085 mm. 3) Solder joint formed on a coupon which involved the reflow of the balls randomly placed on a Cu plated layer with no solder mask coating. The investigation was performed by first establishing the intermetallic growth rate at six different temperatures, ranging from 85/spl deg/C to 150/spl deg/C. The relationship between intermetallic growth and time was shown to essentially follow the common parabolic diffusion relationship to temperature especially above 100/spl deg/C. The activation energy (E/sub a/) and the growth constant (k/sub 0/) were then calculated from this data. The results showed that the E. for the total intermetallic thickness was essentially similar for the three solder joint configurations of the ball, bump and the coupon described above. E. varied from 0.31 eV to 0.32 eV, while the k/sub 0/ varied from 18.0 /spl mu/m/s/sup 1/2 / to 24.2 /spl mu/m/s/sup 1/2 /.     

浅析贴片设备

由于表面组装技术不断地朝着小型化的方向发展 ,特别是在细间距、小直径的凸点和使用的焊剂等诸多因素的推动下 ,促使设备供应商根据倒装芯片技术的需求而研制新一代的贴装机。介绍了设备的制造厂家根据倒装芯片的特点 ,采用柔性 (软件 )方法和视觉系统等方案对现有的设备进行改型 ,从而实现了贴装设备的自动化。实践证明研制开发倒装芯片技术的自动组装技术可使生产率、材料和工艺设备取得明显的进步     

倒装焊中复合SnPb焊点形态模拟

本文给出了倒装焊(flip-chip)焊点形态的能量控制方程,采用Surface Evolver软件模拟了倒装焊复合SnPb焊点(高Pb焊料凸点,共晶SnPb焊料焊点)的三维形态.利用焊点形态模拟的数据,分析了芯片和基板之间SnPb焊点的高度与焊点设计和焊接工艺参数的关系.研究表明:共晶SnPb焊料量存在临界值,当共晶SnPb焊料量小于临界值时,焊点的高度等于芯片上高Pb焊料凸点的半径值;当共晶SnPb焊料量大于临界值时,焊点的高度随共晶SnPb焊料量的增加而增加.另外,采用无量纲的形式给出了焊点高度与共晶焊料量、焊盘尺寸、芯片凸点的尺寸,芯片重量之间的关系模型,研究结果对倒装焊焊点形态的控制、工艺参数的优化和提高焊点可靠性具有指导意义.     

Transmission property of flip chip package with adhesive interconnection for RF applications

The radio frequency (RF) and high frequency performance of the flip chip interconnects with anisotropic conductive film (ACF) and non-conductive film (NCF) was investigated and compared by measuring the scattering parameters (S-parameters) of the flip chip modules. Low cost electroless-Ni immersion-Au (ENIG) plating was employed to form the bumps for the adhesive bonding. To compare the accurate intrinsic RF performance of the ACF and NCF interconnect without lossy effect of chip and substrate, a de-embedding modeling algorithm was employed. The effects of two chip materials (Si and GaAs), the height of ENIG bumps, and the metal pattern gap between the signal line and ground plane in the coplanar waveguide (CPW) on the RF performance of the flip chip module were also investigated. The transmission properties of the GaAs were markedly improved on those of the Si chip, which was not suitable for the measurement of the S-parameters of the flip chip interconnect. Extracted impedance parameters showed that the RF performance of the flip chip interconnect with NCF was slightly better than that of the interconnect with ACF, mainly due to the capacitive component between the bump and substrate and self inductance of the conductive particle surface in the ACF interconnect.     

读出电路铟柱打底层对铟柱成球高度的影响

针对超大规模红外探测器读出电路铟柱成球后高度过低导致倒装互连难度增加这一问题,设计了试验,并分析讨论了读出电路铟柱打底层（UBM）形状对铟柱成球高度的影响。得出了铟球高度与铟柱尺寸和铟柱生长高度成正比,与读出电路铟柱打底层尺寸成反比,并提出了进一步增加铟球高度的思路。     

Bump formation for flip chip and CSP by solder paste printing

Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail.This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.     

红外焦平面探测器互连中的In缩球工艺

铟缩球工艺对红外焦平面探测器的互连很有帮助.依据所做的实验叙述了铟缩球工艺的过程,论述了铟缩球工艺能提高铟柱高度,减小高度差,及减低焊接压力等优点.     

The effect of solder bump pitch on the underfill flow

An underfill encapsulant was used to fill the gap between the chip and substrate around solder joints to improve the long-term reliability of flip chip interconnect systems. The underfill encapsulant was filled by the capillary effect. In this study, the filling time and pattern of the underfill flow in the process with different bumping pitch, bump diameter, and gap size were investigated. A modified Hele-Shaw flow model, that considered the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. This model estimated the flow resistance induced by the chip and substrate as well as the solder bumps, and provided a reasonable flow front prediction. A modified model that considered the effect of fine pitch solder bumps was also proposed to estimate the capillary force in fine pitch arrangements. It was found that, on a full array solder bump pattern, the filling flow was actually faster for fine pitch bumps in some arrangements. The filling time of the underfill process depends on the parameters of bumping pitch, bump diameter, and gap size. A proposed capillary force parameter can provide information on bump pattern design for facilitating the underfilling process.     

Fatigue analysis of high-speed photodiode submodule by using FEM

Higher frequencies, super high-speed, and low-cost demands in wireless communication devices have lead to high density packaging technologies such as flip chip interconnections and multichip modules, as substitutes for wire bonding interconnection. Solder is widely used to connect chips to their packaging substrates in flip chip technology and surface mount technology. We constructed global full 3-D FE models for one photodiode on a submount to predict the fatigue life of solder interconnects during an accelerated thermal cycling testing. The 3-D FE models applied is based on the Darveaux approach does this approach have a non-linear viscoplastic analysis. In the bump structural photodiode submodule, the shortest fatigue life of 233 cycles was obtained at the thermal cycling testing condition from −65 to 150 °C. The bump material, rather than submount material, affected and varied the fatigue life. Also, The fatigue life is decreased with increase in creep strain energy density.     

A study on coining processes of solder bumps on organic substrates

Solder flip chip bumping and subsequent coining processes on printed circuit board (PCB) were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCBs has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation; region of elastic deformation; region of linearly increase of applied loads; region of rapidly increase of applied loads. In order to reduce applied loads for coining solder bumps on a PCB, the effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Lower coining loads were needed to prevent potential substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying coining loads. It was found that coining process temperature had more significant effect to reduce applied coining loads during the coining process.