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1.
3D封装与硅通孔(TSV)工艺技术   总被引:5,自引:0,他引:5  
在IC制造技术受到物理极限挑战的今天,3D封装技术越来越成为了微电子行业关注的热点。对3D封装技术结构特点、主流多层基板技术分类及其常见键合技术的发展作了论述,对过去几年国际上硅通孔(TSV)技术发展动态给与了重点的关注。尤其就硅通孔关键工艺技术如硅片减薄技术、通孔制造技术和键合技术等做了较详细介绍。同时展望了在强大需求牵引下2015年前后国际硅通孔技术进步的蓝图。  相似文献   

2.
《电子与封装》2015,(8):1-8
以硅通孔(TSV)为核心的三维集成技术是半导体工业界近几年的研发热点,特别是2.5D TSV转接板技术的出现,为实现低成本小尺寸芯片系统封装替代高成本系统芯片(So C)提供了解决方案。转接板作为中介层,实现芯片和芯片、芯片与基板之间的三维互连,降低了系统芯片制作成本和功耗。在基于TSV转接板的三维封装结构中,新型封装结构及封装材料的引入,大尺寸、高功率芯片和小尺寸、细节距微凸点的应用,都为转接板的微组装工艺及其可靠性带来了巨大挑战。综述了TSV转接板微组装的研究现状,及在转接板翘曲、芯片与转接板的精确对准、微组装相关材料、工艺选择等方面面临的关键问题和研究进展。  相似文献   

3.
硅转接板是3D IC中实现高密度集成的关键模块,获取其技术参数对微系统的设计至关重要.以实际研制的一种2.5D硅转接板为研究对象,对大马士革铜布线(Cu-RDL)、硅通孔(TSV)关键电参数的测试结构与测试方法进行了研究,并对TSV电参数测试结构的寄生电容进行了分析.研究结果表明,研制的2.5D硅转接板中10 μm×8...  相似文献   

4.
数家研究小组和公司已经展示了通过芯片叠层和穿透硅通孔(TSV)互连来实现复杂3D芯片的可行性。  相似文献   

5.
用于3D集成中的晶圆和芯片键合技术   总被引:1,自引:0,他引:1  
3D集成技术包括晶圆级、芯片与晶圆、芯片与芯片工艺流程,通过器件的垂直堆叠得到其性能的提升,并不依赖于基板的尺寸和技术。所有的报道均是传输速度提高,功耗降低,性能更好及更小的外形因素等优势使得这种技术的名气大振。选择晶圆或芯片级集成的决定应基于几个关键因素的考虑。对于不同种类CMOS、非CMOS器件间的集成,芯片尺寸不匹配引发了衬底的变化(如300mm对150mm).芯片与晶圆或芯片与芯片的堆叠也许是唯一的选择。另外,当芯片的成品率明显地不同于晶圆与晶圆键合方法时,在堆叠的晶圆中难以使确认好芯片的量达到最大。在这种情况下,应将一枚或两枚晶圆划切成小芯片并仅将合格的芯片垂直地集成。只要适当地采用晶圆与晶圆键合工艺便可实现高成品率器件同类集成。晶圆间键合具有最高的生产效率,工艺流程简便及最小的成本。满足选择晶圆级或芯片级工艺总的工艺解决方案应结合对准和键合细节来考虑决定最终的设备选择和工艺特性。所有这些工艺的论证证实对于多数产品的制造3D集成是可行的,而且有些也已成为生产的主流。  相似文献   

6.
提出了一种应用于3D封装的带有硅通孔(TSV)的超薄芯片的制作方法。具体方法为通过刻蚀对硅晶圆打孔和局部减薄,然后进行表面微加工,最后从硅晶圆上分离出超薄芯片。利用两种不同的工艺实现了TSV的制作和硅晶圆局部减薄,一种是利用深反应离子刻蚀(DRIE)依次打孔和背面减薄,另一种是先利用KOH溶液湿法腐蚀局部减薄,再利用DRIE刻蚀打孔。通过实验优化了KOH和异丙醇(IPA)的质量分数分别为40%和10%。这种方法的优点在于制作出的超薄芯片翘曲度相较于CMP减薄的小,而且两个表面都可以进行表面微加工,使集成度提高。利用这种方法已经在实验室制作出了厚50μm的带TSV的超薄芯片,表面粗糙度达到0.02μm,并无孔洞地电镀填满TSV,然后在两面都制作了凸点,在表面进行了光刻、溅射和剥离等表面微加工工艺。实验结果证实了该方法的可行性。  相似文献   

7.
为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20~30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.  相似文献   

8.
晶圆级芯片尺寸封装(WCSP)消除了类似传统的芯片键合、引线键合和倒装芯片贴装过程的封装工序。这种办法可以为半导体产品用户实现更快的上市时间。WCSP封装应用空间正在扩大到新的领域,并根据管脚数量和器件类型进行细分。WCSP封装正在集成无源、分立元件、射频和存储器器件方面得到应用,并扩展到逻辑集成电路和MEMS器件。但伴随着这种应用的增长出现了很多问题,其中包括随着芯片尺寸和管脚数量的增长对电路板可靠性的影响。概述当今的挑战,以及这些集成和硅通孔技术的未来趋势。  相似文献   

9.
针对基于硅通孔技术的3D IC在工作过程中的受热问题,利用热弹性力学理论建立了三维有限元数值模拟分析模型,对结构进行了热分析,同时探讨了器件由此产生的热应力.计算结果表明,由芯片到底面的热通路为散热的主要通道,其它表面的对流条件对热场分布影响不大;芯片与通孔接触面的边角处有应力集中,在热载荷的长期、交变作用下容易发生开...  相似文献   

10.
《电子测试》2011,(4):111-112
科电工程有限公司(Electronic Scientific EngineeringLtd)继去年的7月与日本AstroDesign公司和矽映公司(Silicon ImageInc)在深圳和上海联合举办了《3D技术和发展分享研讨会》后,  相似文献   

11.
Manufacturing of core based three-dimensional (3D) integrated circuit (IC) is an emerging field of semiconductor industry that promises greater number of devices on chip, increased performance and reduced power consumption. But due to scaling in technology features these chips are more complex. Hence testing of these 3D ICs is a challenging task and designing the test wrapper of core is also an important issue in this respect. This paper follows a IEEE 1500-style wrapper design for 3D ICs using Through Silicon Vias (TSVs) for testing purpose. It is assumed that the core elements are distributed over several layers of the ICs. As the number of available TSVs are limited due to small chip area, this work is intended to design balanced wrapper chains using minimum number of TSVs so that testing time of a core is reduced. In this work we have proposed a polynomial time algorithm of O(N) to design the test wrapper. The results are presented based on the ITC’02 SOC test benchmarks and compared with prior works. Obtained results show that our algorithm provides better utilization of TSVs compared to the work presented in Noia et al. (2011).  相似文献   

12.
3DIC集成与硅通孔(TSV)互连   总被引:7,自引:2,他引:7  
介绍了3维封装及其互连技术的研究与开发现状,重点讨论了垂直互连的硅通孔(TSV)互连工艺的关键技术及其加工设备面临的挑战.提出了工艺和设备开发商的应对措施并探讨了3DTSV封装技术的应用前景。  相似文献   

13.
<正>随着科学技术的发展,3D SIP(system-in-package)技术已成为世界热点。基于MEMS圆片级封装WLP(Wafer-level packaging)的SIP技术是目前3D SIP最重要技术之一,它充分利用MEMS的TSV(Through-silicon via)和圆片级键合技术,实现Si与GaAs、Si与陶瓷等异质材料间垂直互联和圆片级集成。该技术可以将传感  相似文献   

14.
介绍了3D堆叠技术及其发展现状,探讨了W2W(Wafer to wafer)及D2W(Die to wafer)等3D堆叠方案的优缺点,并重点讨论了垂直互连的穿透硅通孔TSV(Through silicon via)互连工艺的关键技术,探讨了先通孔、中通孔及后通孔的工艺流程及特点,介绍了TSV的市场前景和发展路线图。3D堆叠技术及TSV技术已经成为微电子领域研究的热点,是微电子技术及MEMS技术未来发展的必然趋势,也是实现混合集成微系统的关键技术之一。  相似文献   

15.
基于Comsol Multiphysics平台,通过使用有限元仿真对三维集成电路的硅通孔(TSV)模型进行了热仿真分析。分别探究了TSV金属层填充材料及TSV的形状、结构、布局和插入密度对三维(3D)集成电路TSV热特性的影响。结果表明:TSV金属层填充材料的热导率越高,其热特性就越好,并且采用新型碳纳米材料进行填充比采用传统金属材料更能提高3D集成电路的热可靠性;矩形形状的TSV比传统圆形形状的TSV更有利于3D集成电路散热;矩形同轴以及矩形双环TSV相比其他结构TSV,更能提高TSV的热特性;TSV布局越均匀,其热特性越好;随着TSV插入密度的增加,其热特性越好,当插入密度达6%时,增加TSV的数目对TSV热特性的影响将大幅减小。  相似文献   

16.
Much research has been carried out to realize through-silicon via (TSV) technology for three-dimensional (3D) chip stacking packaging. A vertical chip interconnection method using Cu/Sn-Ag bumps and nonconductive films (NCFs) is one of the most promising approaches for 3D TSV vertical interconnection. In this work, the relationship between the viscosity of pre-applied NCFs and loading forces was investigated to predict the gap change between a TSV chip and a substrate chip. Existing theories of squeeze flow are adapted to predict the gap change of a real TSV chip and a substrate chip during TSV bonding using a simplified model. The real gaps measured during bonding of test dies were matched to check the validity of the prediction model. Considering the thixotropy of NCFs, the prediction well matched the real gap changes between bumped TSV chips and substrate chips during bonding.  相似文献   

17.
This paper provides a new test technique for detecting defects in Through Silicon Via (TSV) in 3-D ICs and presents a substrate-dependent equivalent electrical model for TSVs. Process-related defects that affect the functional electrical performance of the TSV are identified, and fault models are developed for each individual defect. The fault models are integrated into the equivalent electrical model of the TSV for testing. Our test technique uses an RF carrier signal modulated with a multi-tone signal with added Gaussian white noise to synthesize the test stimulus; the peak-to-average ratio is measured as output response. We find a significant difference in peak-to-average ratio between defect-free and defective TSVs. Our test technique is very sensitive to small defects in these nanostructures, thereby identifying the defects with high accuracy.  相似文献   

18.
硅通孔(TSV)三维封装因其独特工艺而受到广泛关注,然而其内部缺陷无法被直接观测成为目前的检测难题。为了对TSV三维封装内部缺陷进行检测,提出了一种基于激光主动激励的内部缺陷分类与量化方法。通过红外激光主动热源施加到TSV三维封装结构表面,激发TSV内部缺陷的外部温度分布响应,通过理论与仿真分析,掌握缺陷特征在主动激励下的表现规律;构建卷积神经网络对缺陷样本信息进行训练,实现内部缺陷的分类识别与量化。试验表明,该方法能在不损坏样品的前提下有效对内部缺陷进行识别分类及量化,准确率可达95.56%。  相似文献   

19.
Under the current process and layer bonding technology for the TSV (through-silicon-via) based 3D ICs, it is known that the TSV resource is one of the major sources of the function failure of the chip. Furthermore, TSV takes much larger size and pitch than the normal logic components. For this reason, a careful allocation of the TSV resource has been required in 3D IC designs, and several works have been proposed to allocate minimal TSVs. This work also addresses the problem of TSV allocation and optimization, but overcomes one of the critical limitations of the previous works, which is the unawareness or no exploitation of the possibility of TSV resource sharing, previously merely resorting to a simple binding of the data transfers to TSVs. This is because the previous 3D layer partitioners have performed TSV allocation and minimization without any link to the data transfer information accessible from the high-level synthesis flow. This work proposes a set of TSV resource sharing and optimization algorithms (as a post-processing of 3D layer partitioning) by utilizing the life time information of the data transfers taken from the high-level synthesis. Specifically, we propose three algorithms for TSV resource sharing and optimization, which can be selectively applied depending on the sharing granularity and design complexity: (1) word-level TSV sharing, (2) bit-level TSV sharing, and (3) TSV refinement combined with register replication. Through experiments with benchmark designs, it is confirmed that our proposed algorithms are able to reduce the number of TSVs by 41.1% on average in word-level TSV sharing and 26.0% in bit-level TSV sharing compared with the results produced by the conventional layer partitioning with no TSV sharing while still meeting the timing constraint of designs.  相似文献   

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