Effect of deep impurity levels on Schottky barrier diode characteristics

In the presence of an arbitrary number of deep donor levels volt-ampere and volt-farad characteristics are obtained for the Schottky barrier diode which contains a thin dielectric layer between the metal and the semiconductor. The analysis of these characteristics shows that the deep levels can significantly influence both the capacitance and the rectifying properties of the Schottky diode; the thicker the dielectric layer, the greater the effect of the deep levels upon volt-ampere relationship and the lesser upon volt-farad one. One can determine the parameters of the deep levels from these relationships. The results of the calculation are in agreement with the data of the experiment performed.     

Electrical characteristics of an epitaxial high barrier Schottky diode

A Schottky barrier diode with high barrier height injects minority carriers at the forward biased condition. With injection of minority carriers the current density–voltage characteristics are altered significantly from that of the conventional exponential relationship. A model incorporating drift and diffusion currents for both holes and electrons, carrier recombination within the drift region and also the blocking properties of the low–high (n^- n⁺) interface is developed. The previous works on high barrier Schottky diodes used empirical expressions to combine the high injection model with the low injection model in order to study its behaviour at intermediate levels of injection. Whereas in the present work, a boundary condition is applied to combine the high injection model with an intermediate injection model. To combine an intermediate level model with a low injection level model, another boundary condition is introduced. The present work provides solutions for important physical quantities such as the minority carrier profile and current within the drift region, injection ratio and storage time.     

Fabrication and electrical characteristics of Schottky diode based on organic material

The current-voltage (I-V), capacitance-voltage (C-V) and capacitance-frequency (C-f) characteristics of Al/Orange G/n-Si/AuSb structure were investigated at room temperature. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (BH) and the series resistance. The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions, and it was seen that there was a good agreement between series resistances from both methods. The C-V characteristics were performed at 10 kHz and 500 kHz frequencies, and C-f characteristics were performed 0.0 V, +0.4 V and −0.4 V.     

Static characteristics of high-barrier Schottky diode under high injection level

Static J–V, σ–J, γ–J characteristics based on numerical 1D simulation for Me–n–n⁺ and Me–n structures are given. The forward voltage drop of the former structure is less then the last one under high level injection because of LH (nn⁺) junction reflecting properties with respect to minority carriers. Holes stimulate base conductivity modulation but, in spite of this, the hole current gives a negligible contribution to the total current. It is shown that the injection ratio is a less significant parameter compared to base conductivity modulation if it is necessary to estimate charge storage. Influence of substrate is investigated. In addition to forming an LH barrier, the substrate acts as a source of majority carriers and defines the forward voltage drop across the diode structure. Bandgap narrowing in the substrate is taken into account. A comparison with experimental results is also given.     

Temperature dependence of Schottky diode characteristics prepared with photolithography technique

A Richardson constant (RC) of 8.92 Acm^?2K^?2 from the conventional Richardson plot has been obtained because the current–voltage data of the device quite well obey the thermionic emission (TE) model in 190–320 K range. The experimental nT versus T plot of the device has given a value of T₀ = 7.40 K in temperature range of 160–320 K. The deviations from the TE current mechanism at temperatures below 190 K have been ascribed to the patches introduced by lateral inhomogeneity of the barrier heights. Therefore, an experimental RC value of 7.49 A(cmK)^?2 has been obtained by considering Tung’s patch model in the temperature range of 80–190 K. This value is in very close agreement with the known value of 8.16 Acm^?2K^?2 for n-type GaAs.     

Fabrication and characteristics of a 4H-SiC junction barrier Schottky diode

4H-SiC junction barrier Schottky(JBS)diodes with four kinds of design have been fabricated and characterized using two different processes in which one is fabricated by making the P-type ohmic contact of the anode independently,and the other is processed by depositing a Schottky metal multi-layer on the whole anode.The reverse performances are compared to find the influences of these factors.The results show that JBS diodes with field guard rings have a lower reverse current density and a higher breakdown voltage,and with independent P-type ohmic contact manufacturing,the reverse performance of 4H-SiC JBS diodes can be improved effectively. Furthermore,the P-type ohmic contact is studied in this work.     

4H-SiC结型势垒肖特基二极管的制作与特性研究

本文设计制作了两种具有不同结构参数的4H-SiC结型势垒肖特基二极管,在制作过程中采用了两种制作方法：一种是对正电极上的P型欧姆接触进行单独制作,然后制作肖特基接触的工艺过程;另一种是通用的通过一次肖特基接触制作就完成正电极制作的工艺过程。器件制作完成后,通过测试结果比较了采用场限环作为边界终端与未采用边界终端的器件的反向特性,结果显示采用场限环有效地提高了该器件的击穿电压,减小了其反向电流。另外,测试结果还显示采用独立制作P型欧姆接触的工艺过程有效提高了4H-SiC结型势垒肖特基二极管的反向特性,其中P型欧姆接触的制作过程和结果也在本文中做出了详细叙述。     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Influence of pinning trap in Ti/4H–SiC Schottky barrier diode

Ti/4H–SiC Schottky barrier diode without any intentional edge termination is fabricated. The obtained properties, low on-resistance of 3 mΩ cm² and low leakage current of 10⁻⁴ A/cm² at 1000 V, are evaluated by device simulation considering pinning at metal/semiconductor interface. The breakdown voltage is explained by minimization of electric field enhancement at the Schottky electrode edge due to pinning. The leakage current corresponds to Schottky barrier tunneling current depending on drift layer doping and Schottky barrier height.     

Effect of various treatments on Schottky diode properties

The cause of the appearance of an excess current near the crystallization temperature of the amorphous metal PbSb alloy is studied. The effect of ultrasonic treatment on the properties of silicon solar cells based on Schottky diodes with the amorphous metal (a-PbSb)-n-Si alloy is explained. It is shown that the appearance of the excess current in Schottky diodes (a-PbSb)-n-Si upon thermal annealing is associated with structural changes in the amorphous metal film during the transition to the polycrystalline state. The effect of ultrasonic treatment on the photovoltaic properties of solar cells depends on the chosen treatment conditions.     

平面肖特基二极管的制作

为研究制作THz频段下工作的肖特基二极管器件,系统研究了平面肖特基二极管的制作工艺。通过分子束外延(MBE)生长了掺杂浓度分别为5×1018 cm-3的缓冲层和2×1017 cm-3的外延层,并研究温度对厚度的影响,使得膜层厚度控制良好,晶格完整。通过参数控制,减小了等离子体增强化学气相沉积(PECVD)的SiO2钝化层应力,使压指结构的翘曲情况得以改善。研究了不同退火温度下欧姆接触的情况,使接触电阻率减小到0.8×10-7 ?/cm2。用电子束光刻和干法刻蚀制作了亚微米级的阳极区域,结合GaAs湿法刻蚀的速率控制,完成了表面沟道的制作,制作出完整的平面肖特基二极管。通过I-U曲线理论计算,二极管的截止频率达到太赫兹量级,为后续工作奠定了基础。     

Characterization of erbium-silicided Schottky diode junction

Trap density, lifetime, and the Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted trap density, lifetime, and Schottky barrier height for hole are determined as 1.5/spl times/10/sup 13/ traps/cm/sup 2/, 3.75 ms and 0.76 eV, respectively. By using the developed method, the interface of the Schottky diode can be evaluated quantitatively.     

Avalanche robustness of SiC Schottky diode

Reliability is one of the key issues for the application of Silicon carbide (SiC) diode in high power conversion systems. For instance, in high voltage direct current (HVDC) converters, the devices can be submitted to high voltage transients which yield to avalanche. This paper presents the experimental evaluation of SiC diodes submitted to avalanche, and shows that the energy dissipation in the device can increase quickly and will not be uniformly distributed across the surface of the device. It has been observed that failure occurs at a fairly low energy level (< 0.3 J/cm²), on the edge of the die, where the electrical field intensity is the greatest. The failure results in the collapse of the voltage across the diode (short-circuit failure mode). If a large current is maintained through the diode after its failure, then the damage site is enlarged, masking the initial failure spot, and eventually resulting in a destruction of the device and an open circuit.     

Thermally annealed gamma irradiated Ni/4H-SiC Schottky barrier diode characteristics

Thermal annealing effects on gamma irradiated Ni/4H-SiC Schottky barrier diode (SBD) characteristics are analyzed over a wide range of temperatures (400–1100 °C). The annealing induced variations in the concentration of deep level traps in the SBDs are identified by thermally stimulated capacitance (TSCAP). A little decrease in the trap density at E_C – 0.63 eV and E_C – 1.13 eV is observed up to the annealing temperature of 600 °C. Whereas, a gamma induced trap at E_C – 0.89 eV disappeared after annealing at 500 °C, revealing that its concentration (< 10¹³ cm⁻³) is reduced below the detection limit of the TSCAP technique. The electrical characteristics of irradiated SBDs are considerably changed at each annealing temperature. To understand the anomalous variations in the post-annealing characteristics, the interface state density distribution in the annealed SBDs is extracted. The electrical properties are improved at 400 °C due to the reduction in the interface trap density. However, from 500 °C, the electrical parameters are found to degrade with the annealing temperature because of the increase in the interface trap density. From the results, it is noted that the rectifying nature of the SBDs vanishes at or above 800 °C.     

Reverse I-V characteristics in Au-GaAs Schottky diode in the presence of interfacial layer

The existence of an interfacial layer in an Au-GaAs Schottky diode may be revealed by measuring its I-V characteristics at very low reverse bias voltage. It is shown in this letter that a voltage dividing factor m can be used [see (2) of the text] to describe the effect of the interfacial layer on the I-V characteristics of the diode at low bias voltage.     

Inhomogeneous barrier height effect on the current-voltage characteristics of an Au/n-InP Schottky diode

We report the current-voltage(I-V) characteristics of the Schottky diode(Au/n-InP) as a function of temperature. The SILVACO-TCAD numerical simulator is used to calculate the I-V characteristic in the temperature range of 280-400 K. This is to study the effect of temperature on the I-V curves and assess the main parameters that characterize the Schottky diode such as the ideality factor, the height of the barrier and the series resistance. The I-V characteristics are analyzed on the basis of standard thermionic emission(TE) theory and the inhomogeneous barrier heights(BHs) assuming a Gaussian distribution. It is shown that the ideality factor decreases while the barrier height increases with increasing temperature, on the basis of TE theory. Furthermore, the homogeneous BH value of approximately 0.524 eV for the device has been obtained from the linear relationship between the temperature-dependent experimentally effective BHs and ideality factors. The modified Richardson plot, according to the inhomogeneity of the BHs, has a good linearity over the temperature range. The evaluated Richardson constant A^* was 10.32 A·cm^-2·K^-2, which is close to the theoretical value of 9.4 A·cm^-2·K^-2 for n-InP. The temperature dependence of the I-V characteristics of the Au/n-InP Schottky diode have been successfully explained on the basis of the thermionic emission(TE) mechanism with a Gaussian distribution of the Schottky barrier heights(SBHs). Simulated I-V characteristics are in good agreement with the measurements[Korucu D, Mammadov T S. J Optoelectronics Advanced Materials, 2012, 14:41]. The barrier height obtained using Gaussian Schottky barrier distribution is 0.52 eV, which is about half the band gap of InP.     

Low frequency characteristics of a quasioptical Schottky diode detector part I: Theory

A theoretical study is made of saturation effects of FIR point contacts Schottky diodes when used in the envelope detection mode of operation. A model is described that fits experimental results for radiation wavelength ranging from microwaves down to FIR wavelengths. This model permits the prediction of saturation levels throughout this range.     

基于平面肖特基二极管的W波段检波器

肖特基二极管技术为常温下毫米波信号的检测提供了有效的解决方案。它具有极低的寄生电容和级联电阻,可用于该频段的倍频器、混频器和检波器当中。相比于Galey Cell和热辐射测定器(Bolometer),基于肖特基二极管的直接检波技术具有低噪声、高反应率和常温使用的特点。本文介绍了一种基于波导结构的零偏置肖特基二极管检波器,采用E面探针传输波导基模电磁波,通过阻抗匹配实现微带线到二极管的耦合。测试结果表明,在-30 dBm输入功率下：电压反应率的峰值可达8 900 V/W;在75 GHz~105 GHz的频率范围内,电压反应率在1 000 V/W以上。     

基于肖特基二极管的140 GHz次谐波混频器

肖特基二极管混频器是毫米波太赫兹频段的超外差接收机中的关键器件,其研制对于太赫兹通信和雷达应用具有重要意义。本文描述了一种基于低寄生参量肖特基Z-极管DBES105a的140GHz二次谐波混频器（SHM）的仿真设计和制作测试。为了计算二极管特性阻抗,通过对二极管半导体物理结构的研究,建立了肖特基二极管三维电磁仿真模型。次谐波混频器采用波导腔体悬置微带线结构,通过HFSS＋ADS联合仿真设计。仿真结果显示,在65GHz,7dBm本振信号激励下,140GHz频点处的SSB转换损耗为6．3dB,1dB转换损耗带宽为14GHz,DSB噪声温度小于400K。测试结果显示,最低SSB转换损耗为26dB／135GHz,3dB转换损耗带宽为8GHz。