关系排序的一种硬件实现

本文提出了一种利用硬件实现关系排序的模型，该模型采用总线相联的细胞阵列结构形式。它适宜于用ＶＬＳＩ实现，关系元组沿阵列管道边传输边排序，传输与排序同时完成，元组的串入串出满足计算机顺序存取的要求，利用ｎ个细胞对ｎ个元组排序只需２ｎ步，输入和输出各ｎ步，时延为零，尤其重要的是，输出的序列就是排了序的元组本身。     

多值DYL可编程逻辑阵列及其复杂性

本文提出一种采多元逻辑电路的多值可编程逻辑阵列。该阵列由输入译码器，二值“或非”“阵列，二值“或”列及输出译码器四部分组成，具有规则的形状和简单的结构，并且易于实现超大规模集成，此外还讨论了该阵列的逻辑设计和结构复杂性。     

GAL的OLMC工作状态研究

可编程器件，尤其是通过阵列逻辑是一种可由用户编程组态赋于其一定逻辑功能的数字电路器件，通用阵列逻辑（GAL）中的核心电路是输出逻辑宏单元OLMC，它的各种各样组态形式的实现是由结构控制中的SYN，AC（0），AC1（n)来控制的，8个OLMC的不同组态形式就可构成不同的数学系统。     

一种LED图形(光柱)显示器的驱动方法

介绍了一种ＬＥＤ图形显示器（光柱）的电路设计，由于采用了可编程键盘／显示控制芯片ＩＮＴＥＬ８２７９和可编程逻辑阵列芯片ＧＡＬ，因而电路具有结构简单、易于与微机接口等特点     

直接可编程树型结构函数

本文提出一种新型的直接可编程树型结构函数．实现这种函数的电路，具有的特点是：１）它有独特的数学模型；２）该数学函数呈现嵌套子表达式的树型结构，对输入变量或控制变量可直接编程，电路输出由此编程确定；３）电路内部不需设置熔丝．实验结果表明，在许多方面，由于该电路具有十分强大的功能，它完全可以替代ＰＬＤ，ＰＬＡ，ＰＡＬ，ＧＡＬ等可编程逻辑器件，且使用十分灵活，设计、制作成本更加低廉．     

基于DSP+FPGA结构图像处理系统设计与实现

为了实现视频图像的实时处理，采用基于DSP FPGA的线性流水阵列结构，用现场可编程门阵列FPGA对采集的视频数字图像做预处理，并结合大规模可编程逻辑阵列CPLD进行逻辑控制，实现了视频图像的采集和目标提取的视频数字图像处理系统。介绍了该视频图像处理系统的硬件组成、工作原理和各种视频跟踪算法的应用。该系统与计算机联结，配以适当的图像处理软件和开发系统，即可形成一个通用的实时图像处理平台。     

基于ADN8830的非制冷焦平面探测器温度控制系统设计

高精度的温控系统是实现高性能非制冷红外焦平面热像仪设计的关键。针对非制冷焦平面阵列像元温度保持恒定可以提高测试精度的问题,提出了基于ADN8830单芯片热电制冷器控制器的温控系统设计。通过可编程逻辑器件CPLD来控制数模转换芯片DAC为ADN8830提供不同的目标温度设置电压,从而实现不同环境温度下的焦平面阵列像元温度的恒定。最后,通过对所设计电路进行测试表明,相比于由单片机m cu实现的电路,该电路具有温度控制精度高,配置灵活,功耗低、体积小等优点。     

MK9—5卷接机组电气控制系统PLC改造

对ＭＫ９－５卷接机组进行ＰＣ电气控制系统改造作了详细介绍。该系统用三菱Ａ２系列可编程控制器取代原有全部逻辑控制电路及控制电路，实现了全ＰＬＣ控制。     

ZVS条件下死区时间控制技术的FPGA实现

设计了一种由现场可编程逻辑阵列FPGA实现的ZVS条件下死区时间控制电路,该电路不仅可有效防止上下功率管的同时导通,而且能够减小功率级的损耗,降低放大器的谐波畸变率.阐述了所设计电路的特点和功能,并对其进行了功能仿真和静态时序分析.     

基于单片机的光电二极管阵列驱动电路设计

介绍了一种基于单片机的光电二极管阵列驱动电路。在单片的单片机上完成光电二极管阵列时序信号产生、A/D转换及数据传输整个过程,能够检测nA级微弱信号,与常用的可编程逻辑器件相比具有成本低、功耗低、电路结构简单的特点。     

Multiple-valued logic and optimization of programmable logic arrays

Shows a method of designing programmable logic arrays (PLAs) using multiple-valued input, two-valued output functions (MVITVOFs). A MVITVOF is an extension of the two-valued logic function. An expression for a MVITVOF directly represents a multiple-output PLA with decoders. Each product of the expression corresponds to each column of the PLA, so the number of products; in the expression equals the number of columns of the PLA. The array size of the PLA is proportional to the number of products; the PLA can thus be minimized by minimizing the expression     

Memories in microprocessor systems

In this final article the techniques for implementing the address decoding strategies described in the previous article in this series¹ are considered. These techniques are divided into four groups according to the type of device used — random logic, n line to m line decoders, PROMs or programmable logic arrays. The merits of the different techniques are discussed.     

MPEG-2实时解码中的输入缓冲器控制

分析了ＭＰＥＧ２ 的时序模型,研究了理想解码器的输入缓冲器工作过程以及实际实时解码器解码开始的时刻、解码非瞬时、码流非平稳等因素对输入缓冲器的影响,指出实际解码器的输入缓冲器必须增大。在输入缓冲器容量受限制的情况下,给出了输入缓冲器控制策略。该策略已经成功地应用于作者研制的高清晰度电视功能样机中。     

AVS和MPEG-2熵解码结构与电路实现

针对高清视频AVS和MPEG2解码系统,提出一种新的可复用的熵解码电路。该电路采用复用的结构,每个周期内完成一个AVS/MPEG2码字的解码;采用组合逻辑映射查表技术,不需要存储AVS码表;通过复用解码控制电路,减小了面积。对该模块进行了仿真和综合,在0.18微米工艺下,频率为166 MHz,面积为9k等效逻辑门,存储器使用量为3 kbit ROM。     

Conversion schemes in residue code

In this paper, an implementation scheme involving decoders and residue adders has been suggested to convert input data in fixed radix representation to residue representation. A method dealing with the reverse process is also demonstrated. A comparison has been made with the methods known hitherto.     

New Products

Cogar Corporation has announced A family of DTL/TTL compatible MOS Read/Write monolithic memories. The new memories are complete subsystems that combine logic and memory functions on a single printed circuit plug-in card. Each module on the card contains up to 2048 bits of memory. Signal buffers, word drivers, sense amplifiers and latches are also included on the same card. One clock generates the required logic timing sequence. The system is based on MOS technology for the storage arrays and bipolar technology for the interface electronics. It is designed to keep the input loading low and provide line driving capability at output.     

Logic programming with arrays

Nial is a programming language designed around a mathematical treatment of data as nested arrays. A goal of the research described is to integrate within Nial a functional style of programming based on the theory of arrays with the declarative capabilities of a logic programming environment. This is partially accomplished by storing logic clauses as arrays which can be manipulated using logic clauses. Arrays as terms are considered as part of the syntax of the clauses. The approach to logic programming is based on providing a flexible environment for experimenting with full clausal or Horn clause logic. A variety of predefined control strategies and the capability for user-defined control strategies have been provided. The expressive capabilities of combining logic and functional programming styles provides a suitable language for many application areas. The philosophy and design behind a combined logic/database model used to prototype a knowledge-based systems application are described     

Testable design of two-dimensional cellular logic arrays for detecting stuck-at and bridging faults

In this paper the problem of detecting bridging faults in two-dimensional (2-D) cellular logic arrays realizing an arbitrary Boolean function is considered in a new framework. A testable design of such combinational logic arrays has been proposed in which a set of universal tests can be initiated to detect all single stuck-at and bridging faults. The augmentation of the network for inducing testability is simple and is also independent of the function realized.