静态时序分析及其在IC设计中的应用

讨论了静态时序分析算法及其在IC设计中的应用。首先，文章讨论了静态时序分析中的伪路径问题以及路径敏化算法，分析了影响逻辑门和互连线延时的因素。最后通过一个完整的IC设计流程介绍了静态时序分析的应用。     

一种基于时延配置表的FPGA静态时序分析算法

为减小现场可编程门阵列(FPGA)关键路径的延时误差,提出一种基于时延配置表的静态时序分析算法。算法建立了一种基于单元延时与互连线延时配置表的时延模型。该模型考虑了工艺角变化对延时参数的影响,同时在时序分析过程中,通过分析路径始节点与终节点的时钟关系,实现了复杂多时钟域下的路径搜索与延时计算。实验结果表明,与公认的基于查找表的项目评估技术(PERT)算法和VTR算法相比,关键路径延时的相对误差平均减少了8.58%和6.32%,而运行时间平均仅增加了19.96%和9.59%。     

电路抗老化设计中基于门优先的关键门定位方法

随着CMOS工艺尺寸不断缩小,尤其在65 nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45 nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。     

考虑物理布局布线约束的快速时序收敛

本文提供了一种准确高效的多角多模的快速时序收敛ECO解决方案,可以支持复杂So C集成电路层次化设计和多电压域设计。在时序优化过程中不但考虑了物理布局因素约束,还综合考虑了物理布线带来的影响,可以满足20nm先进工艺条件下的设计规则。不但保证了时延计算精度,而且与物理实现PR工具和静态时序分析STA工具保持着很好的一致性。它具有先进的优化算法,灵活的流程控制,能快速实现Setup,Hold,Max-transition等多目标的时序收敛,保证了芯片按时投片生产和产品上市时间。     

RapidIO交换芯片的静态时序约束设计

静态时序分析是目前通用的芯片时序验证的重要方法,其依赖于时序模型和时序约束。时序约束是检验设计电路时序的准则,好的时序约束可以正确地体现芯片的设计需求。针对RapidIO交换芯片中存在的多时钟域构成、高速通道的高速时钟频率要求,2x/4x绑定模式下多lane时钟同步等的特殊要求,以及较多的跨异步时钟处理存在的问题,文中提出一种多分组的全芯片时序约束,通过设置时钟定义、时钟组定义、端口延迟定义、时序例外和虚假路径等,以及修正和优化必要的setup time/hold time违例,解决RapidIO交换芯片静态时序分析中的时序违例等时序问题,实现时序收敛的目的。实验验证及流片测试结果表明,所有时序路径均满足时序要求,RapidIO芯片的时序约束设计正确、完备。     

深亚微米ASIC设计中的静态时序分析

随着集成电路的飞速发展,芯片能否进行全面成功的静态时序分析已成为其保证是否能正常工作的关键.描述了静态时序分析的原理,并以准同步数字系列(PDH)传输系统中16路E1 EoPDH(ethemet over PDH)转换器芯片为例,详细介绍了针对时钟定义、端口约束等关键问题的时序约束策略.结果表明,静态时序分析对该芯片的时序收敛进行了很好的验证.     

SoC静态时序分析中时序约束策略的研究及实例

文章简要描述了静态时序分析的原理，并在一款音频处理SoC芯片的验证过程中，详细介绍了针对时钟定义、多时钟域、端口信号等关键问题的时序约束策略。实践结果表明，静态时序分析很好地满足了该芯片的验证要求．而且比传统的动态验证效率更高。     

动态时序分析及其在纳米级IC设计中的应用

文章讨论了动态时序分析算法及其在纳米级IC设计中的应用.首先,针对静态敏化算法存在的静态伪路径(Static False Path)问题,提出了动态敏化算法,分析了静态敏化和动态敏化的关系.最后讨论了在电源噪声和串扰噪声影响下的动态时序分析.实验结果表明,串扰噪声条件下的动态时序分析结果比静态时序分析给出的保守结果准确得多.     

基于门级路径的高精度晶体管级时序分析技术

在超大规模集成电路设计中,时序分析的精度和完备性决定了芯片是否能达到预期的性能.门级静态时序分析技术凭借容量和速度的优势,在集成电路时序分析市场上占据着主导地位,但是随着市场竞争加剧,芯片项目周期要求越来越短、性能要求越来越高,门级静态时序分析在精度上已无法满足芯片关键路径要在短时间内快速收敛的需求.本文探讨了针对芯片...     

静态时序分析中的门延时计算

静态时序分析由于速度快和容量大而广泛应用于时序验证,而门延时的计算则是静态时序分析中的关键部分。以前利用等效输出驱动点导纳函数相等原理产生的模型,由于不能很好的与等效电容公式结合,门延时的计算存在过于悲观性或乐观性结果。本文采用输出驱动导纳和互连线拓扑结构相结合的方法, 对门延时负载模型进行了改进,很好地与等效电容计算结合,保证了静态时序分析的准确性。     

Efficient logic-level timing analysis using constraint-guidedcritical path search

As the operating speed of digital circuits dramatically increases with the advance of VLSI technology, it is becoming more critical to ensure that the circuits are free from timing-related design errors. In a traditional static timing approach nonfunctional paths cannot be distinguished from functional ones since the functionality of a circuit is ignored. This often results in overestimation of circuit delay and can degrade the circuit performance. In today's design methodology where the use of automated logic synthesis and module-based design are popular, circuits with a very large number of nonfunctional (false) paths are common. This paper describes an efficient logic-level timing analysis approach that can provide an accurate delay estimate of a digital circuit which may have many long false paths. By using logic incompatibilities in a circuit as constraints for critical path search, the algorithm determines the longest sensitizable path without explicit path enumeration. Since the number of false paths that can be implicitly eliminated is potentially exponential to the number of path constraints, performance improvement is significant     

考虑多输入跳变的STA伪关键路径识别算法

通过在当前静态时序分析(STA)中引入多输入跳变(MIT)参数库和布尔可满足方法,提出了一种考虑多输入跳变的静态时序分析伪关键路径识别算法。实验结果表明,与传统的静态时序分析算法相比,该算法能识别50%的伪关键路径,并且真实关键路径延时平均减少14.67%,提高了真实关键路径延时边界预估的精确性。     

A rated-clock test method for path delay faults

Current test generation algorithms for path delay faults assume a variable-clock methodology for test application. Two-vector test sequences assume that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such tests may be acceptable for combinational circuits, their use for nonscan sequential circuit testing is impractical. A rated-clock path delay simulator shows a large drop in coverage for vectors obtained from existing test generators that assume a variable clock. A new test generation algorithm provides valid tests for uniform rated-clock test application. In this algorithm, signals are represented for three-vector sequences. The test generation procedure activates a target path from input to output using the three-vector algebra. For an effective backward justification, we derive an optimal 41-valued algebra. This is the first time, rated-clock tests for large circuits are obtained. Results for ISCAS-89 benchmarks show that rated-clock tests cover some longest, or close to longest, paths     

考虑信号上升/下降时间的IC关键路径算法

关键路径问题是数字集成电路静态时序分析中最重要的问题之一。关键路径查找的基本拓扑算法由于没有考虑输入信号上升／下降时间(slew)，在实践中证明并不是完全正确的。文章提出了改进的算法，保证了关键路径查找在考虑信号slew以后的正确性。该算法具有很强的实用性，对从基本拓扑算法发展而来的其他关键路径查找算法也有重要的参考价值。     

Current sensing differential logic: a CMOS logic for highreliability and flexibility

In this paper, we present a highly reliable and flexible CMOS differential logic called current sensing differential logic (CSDL). This CSDL eliminates the timing constraints between the enable signal and input signals, which cause difficulties in design with conventional differential logic families, by employing a simple clocking scheme. The power-delay product of CSDL is also reduced by using a swing suppression technique. To verify the reliability and the applicability of the proposed CSDL in large very large-scale-integration systems, a 64-bit carry-lookahead adder has been fabricated in a 0.6 μm CMOS technology. Experimental results show that the critical path delay is 3.5 ns with a power consumption of 27 mW at 50 MHz     

Hysteresis effect in floating-body partially depleted SOI CMOS domino circuits

This paper investigates in detail the basic mechanisms of hysteretic delay and noise margin variations for floating-body partially depleted SOI CMOS domino circuits. We first consider the ‘clock cycling scenario’, which completely eliminates (or isolates) the hysteresis effect of the output inverter, thus allowing one to observe and understand the hysteresis effect of the front-end domino logic stage. Three cases, based on whether the input signals are domino input signals, from other domino circuits, static input signals, from static circuits or latches; or a combination of domino and static input signals, are examined and differentiated. It is shown that hysteretic delay variation is the largest and the noise margin worst for the case with mixed domino and static input signals. Although the delay and noise margin disparities among the three types of input signals are significant at the beginning of the clock cycles, they converge as the circuit approaches steady state. The ‘data cycling scenario’ with the combined hysteresis effect of both the front-end domino logic stage and the output inverter is then discussed. Circuits operating under the ‘data cycling scenario’ are shown to have less body charge loss through the switching cycles than under the ‘clock cycling scenario’.     

Timing slack optimization approach using FPGA hybrid routing strategy of rip-up-retry and pathfinder

To improve the path slack of Field Programmable Gate Array （FPGA）, this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a col- location table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized （reduced） by 85.8% on average compared with the Versatile Place and Route （VPR） tim- ing-driven routing algorithm, while the run-time is only increased by 15.02% on average.     

Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems

Debugging and speed-binning a fabricated design requires a pattern-dependent timing model to generate patterns, which static timing analysis is incapable of providing. To address these issues, we propose a timing analysis tool that integrates a pattern-dependent delay model into its analysis. Our approach solves for the delay by using the concept of circuit unrolling and formulation of timing questions as decision problems for input into a satisfiability (SAT) solver. We generate a critical path and input vectors that stimulate it, taking into account pattern-dependent effects such as data-dependent gate delays and multiple-inputs switching. The effectiveness and validity of the proposed methodology is illustrated through experiments on various benchmark circuits and comparisons directly with SPICE.     

Critical Path Selection for Delay Testing Considering Coupling Noise

The objective of delay testing is to detect any defects or variations that manifest into timing failures. In path based delay testing this is done by testing a subset of paths in the circuit that are more likely to fail and hence are critical. Since path delays are vector dependent, the set of critical paths selected depends on the vectors assumed when estimating the path delays. This implies that to find the real critical paths, it is important to consider the effect of dynamic (vector dependent) delay effects such as coupling noise and supply noise during path selection. In this work a methodology to incorporate the effect of coupling noise during path selection is described. For any given path, both logic and timing constraints are extracted and a constrained optimization problem is formulated to estimate the maximum path delay in the presence of coupling noise.