An accurate DC model for high-voltage lateral DMOS transistors suited for CACD

Double-diffused lateral MOS transistors with a drain-source breakdown voltage larger than 280 V have been integrated in an epitaxial junction isolated IC process. For these devices a four-component dc model suited for computer-aided circuit design (CACD) is developed based upon 2-D device simulation. The nonhomogeneously doped backgate is well described by two cascoded MOS transistors with different threshold voltages and gain factors. In the drift region the nonlinear dependence of the electron drift velocity on the applied electrical field is taken into account, and modulation of the on-resistance caused by a varying substrate voltage is incorporated properly. In order to model the characteristics in the entire range of operation, 10 parameters have to be optimized. The method for the parameter extraction is discussed, and a comparison between measuredI-Vcharacteristics and calculated values according to the model is given.     

A compact model for flicker noise in MOS transistors for analog circuit design

Designers need accurate models to estimate 1/f noise in MOS transistors as a function of their size, bias point, and technology. Conventional models present limitations; they usually do not consistently represent the series-parallel associations of transistors and may not provide adequate results for all the operating regions, particularly moderate inversion. In this brief, we present a consistent, physics-based, one-equation-all-regions model for flicker noise developed with the aid of a one-equation-all-regions dc model of the MOS transistor.     

An accurate large-signal MOS transistor model for use in computer-aided design

Some MOS transistor models for computer-aided design, each having a given accuracy and complexity, are presented. These models apply before saturation and in the saturation region. Before saturation, the proposed theory takes into account the behavior of mobility versus gate-channel and drain-source biases. In the saturation region the effect of mobile carriers on the drain-channel space-charge layer in an approximate two-dimensional analysis is taken into account. This model has been checked for dc characteristicsI_{D} (V_{DS})and different channel lengths, dynamic resistances in the saturation region, transfer characteristics of various inverters, and dynamic response of these circuits. The accuracy is within 5 percent.     

An analog technology integrates bipolar, CMOS, and high-voltage DMOS transistors

This paper describes the development of an analog technology that integrates bipolar, CMOS, and DMOS transistors on a single chip. The architecture of the process was chosen for its simplicity and versatility. The influence of the process variables and trade-offs in the performance of the devices have been outlined. Some key elements of DMOS and bipolar transistor behavior are discussed. The successful application of the technology to a plasma display driver has been demonstrated.     

A new and improved physics-based model for MOS transistors

An improved MOS device model is derived based upon a first-order model for the dependency of MOS surface mobility on surface field and lateral drain field. A comparison with experimental data shows that a consistent set of physical parameters can be used to describe both long-channel nMOS devices and short-channel devices. The model can form the basis for improved compact MOS models for circuit analysis.     

Investigations on the high current behavior of lateral diffused high-voltage transistors

This paper describes the high current behavior of a lateral, n-channel, high-voltage transistor. The starting points are TCAD experiments where the phenomenological behavior is analyzed. Based on these results a transistor high current model is derived, which is based on the vertical integrated free carrier concentration in the drift region. The important model parameter is the gate voltage, which defines the boundary condition for the free electron concentration at the beginning of the drift region. Because of the coupling of the carrier continuity equation and the Poisson equation (drift-diffusion model), this boundary condition plays a major role, and defines the carrier concentration inside the drift region. Together with an intrinsic low-voltage transistor model (intrinsic NMOS transistor), a series network is solved numerically. The network behavior reflects the TCAD experiments quite well and covers the different electrical regimes (the on-resistance regime, the quasi-saturation regime, and the saturation regime). The model output is compared with the TCAD experiments and the measured transistor data as well.     

下一代CMOS IC--双栅极MOS晶体管

IC业人士普遍认为,3、5年内,CMOS IC会达到在一块芯片上集成1亿支MOS晶体管的水平.到2006年,利用0.10～0.13 μ m光刻技术生产的CMOS逻辑IC将会在先进的半导体工厂流片.据分析,这种IC MOS晶体管的典型工艺参数和技术参数将是:沟道长度0.05μm;栅氧化层厚度1～2nm;阈值电压0.25V;电源电压1.2V.根据现有的IC基本知识,这已接近IC技术的基本极限.在基本极限附近,传统的MOS晶体管性能会劣化,例如泄漏电流和静态功耗会显著增加,严重影响IC的正常工作.     

Tradeoff between threshold voltage and breakdown in high-voltage double-diffused MOS transistors

The design of junction isolated DMOS transistors suitable for monolithic integration has been studied. The purpose of this correspondence is to describe one of the key tradeoffs when designing these devices for high breakdown voltages (200 V for our example). It is a tradeoff primarily between threshold voltage and the punchthrough voltage of the channel diffusion, however, the avalanche breakdown voltage, on-resistance, and source-to-substrate punchthrough voltage are also affected. As an example, the design of a device for 200-V operation is described. The discussion is, however, general and can be applied to other DMOS designs as well.     

A simple model for scaled MOS transistors that includes field-dependent mobility

A simple MOS model that is suitable for hand calculations, but which includes the effect of normal and tangential electric fields on carrier mobility, is described. This device model is derived from semiphysical models for the field dependence of carrier mobility to accurately predict the effect of reduced dimensions. Fitting parameters for n-channel transistors were extracted. The model is used to examine the effect of reduced mobility at high electric fields on logic switching speed and device transconductance.     

Experimental characterization of power VDMOS transistors incommutation and a derived model for computer-aided design

The authors present an experimental method for the characterization of MOS power switching transistors that does not involve technological parameters that are not available to designers. The method is based on the time-domain analysis of the commutation performance of the transistor when constant current are injected into its terminals. The analysis of the time-domain waveforms and the knowledge of the internal structure of the MOS devices are sufficient for the evaluation of the transistor capacitances. It is then possible to introduce a simple large-signal model for power MOSFETs that is particularly well suited to the analysis of circuits using the MOS transistor in commutation (e.g., switching power converters or high-efficiency power amplifiers). The authors also present the model implementation in the SPICE 2 program. Comparison between results obtained experimentally and by computer simulation for several circuits confirms the accuracy of the proposed method     

Depletion V-groove MOS (VMOS) power transistors

A new depletion MOS transistor is proposed. The structure uses anisotropic etching to define the channel in an n/p epitaxial silicon slice. A simple planar model is developed to explain the characteristics of the devices and is verified by measurements on experimental structures.Power devices are fabricated to illustrate the power capability of the structure. Parameters measured for this structure include: junction temperature, d.c. power dissipation, distortion, ac output power, efficiency. The devices were found to be capable of delivering up to 12W with a cutoff frequency of 80 MHz.     

The temperature dependence of ideal gain in double diffused silicon transistors

Theoretical treatments predict higher injection efficiency for double diffused silicon transistors than the experimentally observed values. This paper shows that the discrepancy can be partly explained by the difference in the effective energy gaps in the emitter and base regions. Coulomb interaction of the free carriers results in lower energy gap in the heavily doped emitter than in the rest of the transistor. The difference in the energy gaps is experimentally determined from the activation energy difference of the emitter-current and the ideal component of the base Current. It is concluded that too much doping in the emitter lowers the transistor gain, increases the temperature dependence of the gain, and results in a higher excess noise.     

BSIM: Berkeley short-channel IGFET model for MOS transistors

The Berkeley short-channel IGFET model (BSIM), an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design are described. Both the strong-inversion and weak-inversion components of the drain current expression are included. In order to speed up the circuit-simulation execution time, the dependence of the drain current on the substrate bias has been modeled with a numerical approximation. This approximation also simplifies the transistor terminal-charge expressions. The charge model was derived from its drain-current counterpart to preserve consistency of device physics. Charge conservation is guaranteed in this model.     

A two-dimensional model of the avalanche effects in MOS transistors

A two-dimensional self consistent MOS transistor model accounting for the avalanche effect is described. The classical semiconductor equations—Poisson's equation and the two carrier equations—are solved with the finite difference method. The pair production rate is evaluated at any mesh point and dominates the inhomogeneity term of the carrier continuity equations in case of avalanche. Calculated and measured current-voltage characteristics are in good agreement and thus support our model. For a 3 μm device the electrical potential, the carrier densities, and the generation rates are shown in quasi three-dimensional plots from which the avalanche generation in the pinch-off region becomes apparent. Furthermore, hole storage close to the interface is seen to take place in the channel up to the vicinity of the source region. The corresponding barrier lowering leads to increased electron injection from the source and enhanced avalanche. The barrier lowering is supported by the influence of the parasitic bulk resistance.     

A CMOS model for computer-aided circuit analysis and design

An equivalent circuit model to simulate the current-voltage behavior of CMOS transistors is discussed. This model can simulate the full range of complementary MOSFET operation and can handle latchup at the circuit analysis level. Using effective injection efficiencies a switching criterion and a method of solution for a four parasitic bipolar transistor system have been developed and incorporated. The configuration of the CMOS device is computed from data submitted by the user. This includes well depth, MOSFET separation, doping levels, minority-carrier lifetime, substrate bypass resistors, the option to float either or both substrates, and bias conditions. The model can be used alone or incorporated into existing computer-aided-design programs for analysis of circuits which contain CMOS components     

A new VLSI memory cell using DMOS technology (DMOS cell)

A high-density dynamic memory cell using DMOS technology (DMOS cell) is proposed. A DMOS cell consists of an n-channel DMOSFET as a read gate and a p-channel MOSFET as a write gate with extensive node sharing. Since n-DMOSFET threshold state is nondestructively detected, the readout signal voltage is almost invariant to scaling. The cell area, which is made small by using two polysilicon layers and self-aligned structure, is about 50 percent of the conventional one-transistor memory cell area. An analytic model for DMOS cell readout voltage is proposed. From this model, the optimum DMOS cell structure, which gives more than 0.7-V readout voltage with 2-µm channel length, is found for 5-V power supply operation. Experimental data support this model. A 7-µA readout current per 1-µm channel width is obtained for 400-Å gate oxide test cell. The complete memory operation is confirmed with a 2 × 2 test cell array.