Radiation damage effects on bipolar and MOS devices in X-Ray lithography

Radiation damage effects of bipolar and MOS transistors have been investigated using the vacuum ultraviolet (VUV) storage ring of the national synchrotron light source (NSLS). The devices under investigation were exposed to x-ray radiation and electrical measurements were performed to determine the radiation effects on device parameters. It was found for bipolar devices that the current gain is the parameter that is most sensitive to x-ray irradiation. The current gain decreases as the dose increases and the degradation reaches saturation at 1000 mJ/cm². Upon annealing in forming gas at 400° C for 30 min, the current gain recovered its pre-irradiation value and stress test did not show any reliability problem. Bothn-channel andp-channel MOS devices with polysilicon gates were investigated. Host of the relevant device parameters were measured before and after irradiation and after annealing. Upon irradiation the threshold voltage shows the most obvious shift, which was more negative in both cases. However, thep- channel devices experienced a much larger shift than then-channel ones. The transconductance of the devices also experienced a shift.     

MOS-bipolar monolithic integrated circuit technology

A technique for the fabrication of p-channel MOS transistors and bipolar transistors within monolithic integrated circuits is described. Total process compatibility has been achieved without compromising either the n-p-n bipolar or p-channel MOS characteristics. The technology developed is similar to that used for conventional integrated circuits until the channel oxidation step, A low temperature oxidation followed by a high temperature anneal process that produces negligible changes in preceding diffusion profiles was used to form this oxide. Bias temperature tests of MOS capacitors have shown the oxide to be reproducibly free of contamination. A high slew rate MOS bipolar operational amplifier has been designed and fabricated on 0.045- by 0.045-in chip using the new technology. Typical characteristics are slew rate =80 V/µs voltage gain = 70 dB. The MOS transistors are used as active loads and level shifters in this circuit and provide a much improved frequency response over conventional circuits using p-n-p lateral transistors.     

Radiation resistant MOS devices

A detailed study indicates that the radiation resistance of MOS transistors is controlled by the details of technology. It has been found that an MOS structure can be created that remains operational for gamma doses above 10⁷rad. It will be shown how the radiation resistance varies with gate oxidation and the metals employed. Two metals were used in the experiments: aluminum and chromium. The interrelationship between radiation and thermal stability will also be discussed. It will be shown that there is some connection between the two as long as the same basic technology is used. It is possible however, that combinations that result in thermal stability can still show a low radiation resistance. The radiation generates positive-charge centers in the oxide and these centers are related to "minor" bonds in the oxide. In this respect, the oxide-metal interactions have been considered. It follows from our studies that the greatest radiation resistance will be found forp-enhancement devices and for certainn-depletion structures. The measurements will show results forP-enhancement units with radiation resistance one-hundred times greater than previously reported figures, both for MOS and bipolar transistros.     

Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO₂-dominated high-k gate dielectrics is like mobile defect; while that with SiO₂-dominated ones is similar to the near-interface/border trap.     

Effects of wet N2O oxidation on interface properties of6H-SiC MOS capacitors

Oxynitrides were grown on n- and p-type 6H-SiC by wet N₂O oxidation (bubbling N₂O gas through deionized water at 95°C) or dry N₂O oxidation followed by wet N₂O oxidation. Their oxide/SiC interfaces were investigated for fresh and stressed devices. It was found that both processes improve p-SiC/oxide but deteriorate n-SiC/oxide interface properties when compared to dry N₂O oxidation alone. The involved mechanism could be enhanced removal of unwanted carbon compounds near the interface due to the wet ambient, and hence a reduction of donor-like interface states for the p-type devices. As for the n-type devices, incorporation of hydrogen-related species near the interface under the wet ambient increases acceptor-like interface states. In summary, wet N ₂O oxidation can be used for providing comparable reliability for nand p-SiC MOS devices, and especially for obtaining high-quality oxide-SiC interfaces in p-type MOS devices     

集成双极晶体管基区表面电势的二维模型及其应用

基区表面电特性对双极器件影响很大,本文建立了集成双极npn晶体管基区表面电势的二维模型。文中还通过对采用SiO_2膜和Si_3N_4-SiO_2双层膜一次钝化的电容(MOS和MNOS)和栅控npn晶体管的表面电特性的研究,发现SiO_2-Si_3N_4一次钝化膜能有效地减小基区表面电势。     

Nonoverlapping super self-aligned device structure forhigh-performance VLSI

The nonoverlapping super self-aligned structure (NOVA) is reported. Because of its nonoverlapping nature, this structure can be applied equally well to bipolar, CMOS, or BiCMOS processes. This structure effectively minimizes parasitic capacitance and resistance for both the MOS and bipolar devices. CMOS and bipolar devices are integrated into a high-performance BiCMOS technology. CMOS and emitter-coupled logic (ECL) ring oscillators with 1.5-μm lithography are reported to have delays of 128 and 87 ps/stage, respectively     

SiC field-effect devices operating at high temperature

Field-effect devices based on SiC metal-oxide-semiconductor (MOS) structures are attractive for electronic and sensing applications above 250°C. The MOS device operation in chemically corrosive, high-temperature environments places stringent demands on the stability of the insulating dielectric and the constituent interfaces within the structure. The primary mode of oxide breakdown under these conditions is attributed to electron injection from the substrate. The reliability of n-type SiC MOS devices was investigated by monitoring the gate-leakage current as a function of temperature. We find current densities below 17 nA/cm² and 3 nA/cm² at electric field strengths up to 0.6 MV/cm and temperatures of 330°C and 180°C, respectively. These are promising results for high-temperature operation, because the optimum bias point for SiC MOS gas sensors in near midgap, where the field across the oxide is small. Our results are valid for n-type SiC MOS sensors in general and have been observed in both the 4H and 6H polytypes.     

Chemical reaction concerns of gate metal with gate dielectric in Tagate MOS devices: an effect of self-sealing barrier configurationinterposed between Ta and SiO2

Chemical reaction of gate metal with gate dielectric for Ta gate MOS devices has been experimentally investigated both by electrical and physical measurements: capacitance-voltage (C-V), current-voltage (I-V), transmission electron microscopy (TEM), energy dispersive X-ray (EDX), electron diffraction measurements. In spite of the chemical reaction of Ta with SiO₂ consuming ~1-nm-thick in gate oxide, the interface trap densities of ~2×10¹⁰ cm^-2 eV ^-1 at midgap and ideal channel mobility characteristics have been observed in the Ta gate MOS devices with 5.5-nm-thick thermal oxide gate dielectric. Considering the experimental data with theoretical calculation based on thermodynamics together, a barrier layer model has been developed for the Ta gate MOS systems. The physical mechanism involved is probably self-sealing barrier layer formation resulting from the chemical reaction kinetics in the free-energy change of Ta-Si-O system     

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate–drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.      

Limitations in microelectronics — II. Bipolar technology

The physical phenomena which will ultimately limit miniaturization of planar bipolar integrated circuits are examined. The maximum packing density is obtained by minimizing the supply voltage and the size of the devices. The minimum transistor size is determined by junction breakdown, punch through and doping fluctuations. For circuits that are fully active the maximum number of circuit functions per chip is determined by power dissipation. The packing density of read-only memories becomes limited by the area occupied by devices and interconnections. The limitations of MOS and bipolar technologies are compared. It is concluded that read-only memories will reach approximately the same performance and packing density with MOS and bipolar technologies, while fully active circuits will reach the highest levels of integration with dynamic MOS or complementary MOS technologies.     

The Physics of Failure of MIS Devices Under Radiation

Unlike the solar cell and the NPN transistor, the MOS device does not sustain a degradation as the principal effect of exposure to nuclear radiation. Instead, the MOS device undergoes a change of operating region, the change being in the nature of a parallel shift of the characteristic curve of the device, produced by the trapping of radiation-excited holes within the 2000-? insulator and the consequent buildup of a fixed bulk space charge in the insulator. Less significant changes under radiation are variations in the shape of the characteristic curve and increased leakage current. These are genuine degradation effects and are closely analogous to the strong effects of ionizing radiation in planar-passivated junction devices such as bipolar transistors, SCRs, diodes, etc. In the latter cases, the devices are acting as MIS devices and hole trapping in the oxide is again responsible for their degradation. A consideration of the case of simple MIS devices under radiation is thus found helpful in elucidating some other important types of failure under radiation of silicon junction devices.     

Monolithic integration of 5 V CMOS and high-voltage devices

A fully CMOS-compatible HVIC technology has been developed that features 5 V high-performance digital CMOS with high-voltage devices of more than 400 V. This technology uses only one or two masks in addition to standard p-well CMOS technology. Design optimization has been achieved to meet the needs of both CMOS and high-voltage devices. A large number of different devices are available in this technology, including bipolar transistors, lateral MOS gate power devices, and high-voltage p-channel power devices     

Entirely gate-surrounded MOS capacitor to study the intrinsic oxidequality

The intrinsic dielectric strength of gate oxides is investigated by MOS capacitors which are designed so that the gate poly does not cross the field oxide edge. Using the charge to breakdown in the high-injection regime as a sensitive indicator, it is shown that poly-surrounded capacitors are required to measure the intrinsic oxide quality, whereas conventional devices may be sensitive to process variations in the MOS isolation sequence and oxide thinning at the field oxide edge     

Emitter resistance of arsenic- and phosphorus-doped polysilicon emitter transistors

Measurements of emitter resistance have been made on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors, fabricated with or without an interfacial oxide layer. It is found that the emitter resistance of phosphorus-doped transistors is considerably lower than that of arsenic-doped transistors. In addition the presence of a deliberately grown interfacial oxide layer leads to a significant increase in emitter resistance for both arsenic- and phosphorus-doped devices.     

Short-channel MOS transistors in the avalanche-multiplication regime

Short-channel MOS transistors have been analyzed in the avalanche-multiplication regime. Ionization integrals, internal body effect, and parasitic bipolar turn-on have been investigated in dependence of channel doping profile and substrate doping level. Results of a two-dimensional numerical analysis offer a better understanding of the breakdown mechanisms. For devices with shallow channel doping and high-resistivity substrate, an avalanche-current-induced barrier lowering at the source junction edge is observed. Electron injection via this locally lowered barrier triggers parasitic bipolar action. A deep channel implant improves the source barrier and lower substrate resistivity shifts the parasitic bipolar trigger voltage to higher drain voltage (1-1.5 V).     

用1／f噪声表征MOSFET的负温偏不稳定性

负温偏不稳定性是ＭＯＳ顺件最重要的可靠问题之一。本文实验上发现ＭＯＳＦＥＴ的Ａ／ｆ噪声与其负温偏不稳定性相关，初始１／ｆ噪声谱密度正比于负温偏应力下的跨导退化量。     

Designing the power-handling capabilities of MOS power devices

The considerations involved in the design of soft solder power MOS devices for the industry are described in this study. Numerical models for thermal resistance and thermal fatigue are described with acceptable experimental agreement. An accurate method for the measurement of thermal resistance directly applicable to MOS power devices is described. It has been demonstrated that an optimized die contact geometry will result in rugged MOS devices outperforming, in most cases, their bipolar counterpart.     

Silicon-on-insulator approach for power IC's integrating verticalDMOS and polycrystalline silicon CMOS thin-film transistors

A novel approach for the monolithic integration of low-voltage logic and analog control circuits with vertical-current flow power transistors is described. This is achieved by fabricating a CMOS device family, using polycrystalline-silicon thin-film transistors (TFTs), on the field oxide of a single-crystal power device. Parasitic interactions between the control and power devices are eliminated in a simple, inexpensive, and easily manufacturable process. The technology is capable of supporting both MOS and bipolar power devices and the presence of the TFT circuits places no restriction on the maximum voltage or current of the power device. The TFTs exhibit good electrical characteristics and the power devices are not compromised by the addition of the TFT control circuits. This concept is demonstrated by the fabrication of a vertical DMOS power transistor with >100-V, >45-A capability, monolithically integrated with current-limiting and temperature-limiting functions