A back-wafer contacted silicon-on-glass integrated bipolar process. Part II. A novel analysis of thermal breakdown

Analytical expressions for the electrothermal parameters governing thermal instability in bipolar transistors, i.e., thermal resistance R/sub TH/, critical temperature T/sub crit/ and critical current J/sub C,crit/, are established and verified by measurements on silicon-on-glass bipolar NPNs. A minimum junction temperature increase above ambient due to selfheating that can cause thermal breakdown is identified and verified to be as low as 10-20/spl deg/C. The influence of internal and external series resistances and the thermal resistance explicitly included in the expressions for T/sub crit/ and J/sub C,crit/ becomes clear. The use of the derived expressions for determining the safe operating area of a device and for extracting the thermal resistance is demonstrated.     

Embedded benzocyclobutene in silicon: An integrated fabrication process for electrical and thermal isolation in MEMS

This paper reports a novel fabrication process to develop planarized isolated islands of benzocyclobutene (BCB) polymer embedded in a silicon substrate. Embedded BCB in silicon (EBiS) can be used as an alternative to silicon dioxide in fabrication of electrostatic micromotors, microgenerators, and other microelectromechanical devices. EBiS takes advantage of the low dielectric constant and thermal conductivity of BCB polymers to develop electrical and thermal isolation integrated in silicon. The process involves conventional microfabrication techniques such as photolithography, deep reactive ion etching, and chemical mechanical planarization (CMP). We have characterized CMP of BCB polymers in detail since CMP is a key step in EBiS process. Atomic force microscopy (AFM) and elipsometry of blanket BCB films before and after CMP show that higher polishing down force pressure and speed lead to higher removal rate at the expense of higher surface roughness, non-uniformity, and scratch density. This is expected since BCB is a softer material compared to inorganic films such as silicon dioxide. We have observed that as the cure temperature of BCB increases beyond 200 °C, the CMP removal rate decreases drastically. The results from optical microscopy, scanning electron microscopy, and optical profilometry show excellent planarized surfaces on the EBiS islands. An average step height reduction of more than 95% was achieved after two BCB deposition and three CMP steps.     

A low-capacitance bipolar/BiCMOS isolation technology. I. Concept,fabrication process, and characterization

A device isolation structure for low-parasitic bipolar transistor integration is presented. The concept involves two selective epitaxial growth steps (SEG) and two polishing cycles which replace the collector-epitaxy and the deep/shallow trench formation in conventional device isolation. With an optimum device layout, the collector-substrate capacitance is reduced to ≃30%, the collector-base capacitance to ≃70%, and the extrinsic base contact resistance to <50% compared to trench isolation. The combination of SEG and polishing makes it possible to form SOI regions with locally different SOI thicknesses on the same wafer, so that fully depleted CMOS and vertical bipolar transistors can be combined in a SOI-BiCMOS technology     

A 1-μm polysilicon self-aligning bipolar process for low-powerhigh-speed integrated circuits

A double-poly-Si self-aligning bipolar process employing 1-μm lithography is developed for very-high-speed circuit applications. Epilayer doping and thickness are optimized for breakdown voltages and good speed-power performance. Shallow base-emitter profiles are obtained by combining low-energy boron implantation and rapid thermal annealing (RTA) for the emitter drive-in. A transit frequency f_T =14 GHz at V_BC=-1 V and a current-mode-logic (CML) gate delay of 43 ps at 30 fJ are achieved. For an emitter size of 1.0×2.0 μm² a minimum power-delay product of 15 fJ is calculated. Circuit performance capability is demonstrated by a static frequency divider operating up to 15 GHz     

A low-capacitance bipolar/BiCMOS isolation technology. II. Circuitperformance and device self-heating

For pt. 1 see ibid., vol. 41, no. 8, p. 1379-87 (1994). Device and circuit results from transistors fabricated with a novel bipolar isolation technology are presented and discussed. The isolation structure, called sequentially planarized interlevel isolation technology (SPIRIT), is fabricated by using a combination of selective epitaxial growth of silicon and a preferential polishing technique as the key process elements. This structural concept aims for reduced collector-substrate and collector-base capacitances, as well as a lower extrinsic base contact resistance, in a partial-SOI structure without significantly increasing the device temperature during operation. The feasibility of the isolation structure is demonstrated through ECL ring oscillators with gate delays of 23.6 ps at 0.72 mA and 47 ps at 0.23 mA. The temperature contours for SPIRIT and other bipolar isolation structures are simulated by using a finite-element method. It is shown that the capacitance versus self-heating tradeoff of SPIRIT is significantly improved over that of conventional trench or SOI isolation structures     

Thermalelectro-feedback model for multi-emitter finger power heterojunction bipolar transistor. Part I: Temperature profile

Poor thermal conductivity of GaAs, a self-heating phenomenon which results in the rapid rise of device temperature, is the major factor that limits and even degrades the electrical performance of GaAs-based heterojunction bipolar transistor (HBT) operated at high power densities. On the basis of this consideration, a numerical model is presented to study the interaction mechanism between the thermal and electrical behavior of AlGaAs/GaAs HBT with multiple-emitter fingers. The model mainly comprises a numerical model applicable for multi-finger HBT that solves the three-dimensional heat transfer equation. The device design parameters that influence the temperature profile and current distribution of the device are identified, and optimization concerning the device performance is made.     

The electrical century. I. Introduction and overview

A little bit of close inspection reveals that not only the beginning and end of our century but every decade in between has been underpinned by electrical, electronic, or computing technologies of monumental importance. No one would deny that even the technologies we associate most closely with our nuclear and space ages are themselves dependent on electronics and computing. In all, this truly has been the century of electrical and computing engineering. To celebrate the accomplishments of the Electrical Century, the IEEE History Center have launched a series of articles looking back at 100 years of electrical history and pointing the way to the future     

A calculus for network delay. I. Network elements in isolation

A calculus is developed for obtaining bounds on delay and buffering requirements in a communication network operating in a packet switched mode under a fixed routing strategy. The theory developed is different from traditional approaches to analyzing delay because the model used to describe the entry of data into the network is nonprobabilistic. It is supposed that the data stream entered into the network by any given user satisfies burstiness constraints. A data stream is said to satisfy a burstiness constraint if the quantity of data from the stream contained in any interval of time is less than a value that depends on the length of the interval. Several network elements are defined that can be used as building blocks to model a wide variety of communication networks. Each type of network element is analyzed by assuming that the traffic entering it satisfies bursting constraints. Under this assumption, bounds are obtained on delay and buffering requirements for the network element; burstiness constraints satisfied by the traffic that exits the element are derived     

A compact physical large-signal model for high-speed bipolar transistors at high current densities—Part I: One-dimensional model

A compact physical large-signal transistor model is presented that is suited for simulating high-speed bipolar IC's even if the transistors are operated deeply within the high-current region (including quasi-saturation). Like the well-known and currently used Gummel-Poon model, it is based on the integral charge-control relation (ICCR) proposed by Gummel. However, in the high-current region it shows much better accuracy, especially for high-frequency and switching operation. This is mainly a result of the fact that the transit time (and thus the minority-carrier charge) is chosen as a basic model parameter, which is carefully measured and accurately approximated by analytical expressions throughout the total interesting operating range. In Part I of the work, presented here, the model and its parameters are described for the one-dimensional case. Its validity is verified by comparison with exact numerical transistor simulations of both the dc characteristics and the switching behavior. The simulations are based on doping profiles that are typical of transistors in high-speed IC's. Methods for determination of the model parameters are presented. In Part II [1], the model is extended to the two-dimensional case, i.e., to real transistors. It is experimentally verified by measuring the dc characteristics and the switching behavior of very fast transistors with high transit frequency (fT≈ 7 GHz) and small emitter stripe width. The complete model, which is called HICUM (from "high-current model"), was already implemented in the circuit analysis program SPICE 2.     

A tutorial on wavelets from an electrical engineering perspective.I. Discrete wavelet techniques

The objective of this paper is to present the subject of wavelets from a filter-theory perspective, which is quite familiar to electrical engineers. Such a presentation provides both physical and mathematical insights into the problem. It is shown that taking the discrete wavelet transform of a function is equivalent to filtering it by a bank of constant-Q filters, the non-overlapping bandwidths of which differ by an octave. The discrete wavelets are presented, and a recipe is provided for generating such entities. One of the goals of this tutorial is to illustrate how the wavelet decomposition is carried out, starting from the fundamentals, and how the scaling functions and wavelets are generated from the filter-theory perspective. Examples (including image compression) are presented to illustrate the class of problems for which the discrete wavelet techniques are ideally suited. It is interesting to note that it is not necessary to generate the wavelets or the scaling functions in order to implement the discrete wavelet transform. Finally, it is shown how wavelet techniques can be used to solve operator/matrix equations. It is shown that the “orthogonal-transform property” of the discrete wavelet techniques does not hold in numerical computations     

Hetero-emitter-like characteristics of phosphorus doped polysiliconemitter transistors. Part I: band structure in the polysilicon emitterobtained from electrical measurements

This paper reports on the cause of hetero-emitter-like characteristics recently discovered for a phosphorus doped poly-Si emitter transistor, the poly-Si emitter of which is crystallized from an in-situ phosphorus doped amorphous Si film. The band structure in the poly-Si emitter is investigated using (1) the transistor characteristics and (2) the I-V characteristics of the interface between the poly-Si emitter layer and the Si substrate. As a result, a new kind of potential barriers are observed on the conduction band and the valence band at the interface. The potential barrier on the valence band is proved to be the origin of the hetero-emitter-like characteristics. According to the I-V characteristics of the interface, the formation of the barriers is probably due to band discontinuity at the interface     

A review of ULSI failure analysis techniques for DRAMs. Part II: Defect isolation and visualization

In this paper the basic techniques for defect isolation and visualization used in physical failure analysis of trench technique dynamic random access memories (DRAMs) are reviewed. The methods described are state-of-the-art for DRAM failure analysis down to 0.14 μm feature size and beyond. In addition to defect isolation and defect visualization from the front side of a die, the backside preparation approach is reviewed. Beginning with basic sample preparation techniques including mechanical polishing, wet and dry etching and focused ion beam (FIB) applications advantages and disadvantages of various techniques are discussed. In the second section of the paper different types of optical microscopes are covered as well as scanning and transmission electron microscopes. The imaging capabilities of the FIB systems are included in this section. Finally, some applications of scanning probe techniques especially for dopant measurements and thin oxide characterization are described.     

Analysis of LPCVD process conditions for the deposition of low stress silicon nitride. Part I: preliminary LPCVD experiments

A wide range of process conditions were investigated to optimize conditions for the deposition of low stress silicon nitride films by low-pressure chemical vapor deposition. Experiments carried out in a standard, multi-wafer batch system generated films with an index of refraction ranging from about 2.04 to 2.82 and residual stress ranging from about 700 MPa tensile to –90 MPa compressive. The relationship between residual stress and index of refraction was characterized and results compared to those presented in the technical literature. Increase in the index of refraction beyond about 2.3 by means of increasing the gas flow did not reduce the residual stress appreciably but had a significant detrimental impact on the thickness uniformity and deposition rate. In contrast to results reported by other researchers, uniformity was not observed to increase with increasing DCS/NH₃ ratio in this study. Efforts to minimize thickness non-uniformity by suppressing deposition rate at the gas inlet region of the deposition system while increasing deposition rate at the rear were not successful. While increasing the temperature at the exhaust end of the system was intended to improve thickness non-uniformity, significant thickness and index of refraction uniformity was not realized. The reduction in deposition rate and corresponding increase in index of refraction at the exhaust end of the system indicated a variation in gas species from inlet to exhaust of the system. These experimental results revealed that the index of refraction decreased while the deposition rate decreased with increasing partial pressure of DCS. This suggests that the inhomogeneity observed within the repeatability runs is due to ammonia depletion along the length of the load.     

A study of photoelectronic-digital radiology—Part I: The photoelectronic-digital radiology department

A three-part study presents the concepts, costs, and basic considerations involved in photoelectronic-digital radiology. This new approach to diagnostic radiology eliminates film as the primary image acquisition medium. It provides an attractive opportunity to develop new diagnostic procedures, be cost effective, and improve on diagnostic accuracy. Part I explores the concept as applied to our thirteen-room radiology department. Part II deals with cost effectiveness, and Part III is concerned with engineering of photoelectronic-digital radiology systems. Part I identifies five organizational units requiring individual attention. They are: 1) examination rooms and their analog image acquisition devices, 2) a computer facility incorporating digital image acquistion, processing, and archival storage, 3) a reading room, 4) offices and clinics, and 5) a possible control center. Features desired for each unit's components are identified and discussed. Areas of strength and weakness, as well as those attractive for new activity in research and development, are delineated.     

Process modeling and simulation for Hg1-xCdxTe. Part I: Status of stanford university mercury cadmium telluride process simulator

Details are provided concerning the basic point defect parameter set of the Stanford University mercury cadmium telluride process simulator (SUMerCad). The Hg interstitial and vacancy parameters are presented and justified for x = 0.2 material. In particular, values for the thermodynamic limits, diffusion coefficients, recombination rates, generation rates, and boundary conditions are specified and their determination methodology is reviewed. The parameters have been determined for overall consistency with a specific pool of experimental results which include studies of Hg self-diffusion, type-conversion, and the existence region. Our presentation will review the current state of the Hg_1-xCd_xTe modeling effort, and outline the future direction of the simulator, providing examples and discussion. Finally, some issues related to the future development of SUMerCad are discussed, including electric field effects, general boundary conditions, alternative junction formation processes, extended defects, and interdiffusion.     

In situDiagnostics of Plasma Processes in Microelectronics: The Current Status and Immediate Prospects. Part I.

The necessity of in situmonitoring plasma processes in present-day microelectronics stems from the fact that they must provide high precision. New-generation micro- and nanodevices, which will have sharp interfaces and atomic-level sizes, demand continuous monitoring of process stages. Preference should be given to built-in monitoring facilities, which exploit highly sensitive physical effects and do not disturb particle fluxes from a plasma to a substrate. Part I covers advanced diagnostic and monitoring methods, as applied to plasmochemical processes used in microelectronics, with emphasis to optical spectral techniques. They are based on in-process measuring volume (nonlocal) parameters of a reactive plasma. Processes monitored may include etching and deposition of semiconductor, metal, and insulating layers, as well as resist stripping and surface cleaning.     

Bistatic LIDAR: A Tool for Characterizing Atmospheric Particulates: Part I?The Remote Sensing Problem

The bistatic, Light Detection And Ranging, LIDAR technique for sensing atmospheric particulates is outlined, and analytical formulations are presented for characterizing both the intensity and polarization of the bistatic signals. Methods are presented on how to handle the remote sensing problem of extracting the particulate angular scattering parameters from the bistatic measurements. Examples are also presented which demonstrate that these methods can be practically applied at least for atmospheric conditions typical of Tucson, AZ.     

A tutorial on wavelets from an electrical engineering perspective.2. The continuous case

The wavelet transform is described from the perspective of a Fourier transform. The relationships among the Fourier transform, the Gabor (1946) transform (windowed Fourier transform), and the wavelet transform are described. The differences are also outlined, to bring out the characteristics of the wavelet transform. The limitations of the wavelets in localizing responses in various domains are also delineated. Finally, an adaptive window is presented that may be optimally tailored to suit one's needs, and hence, possibly, the scaling functions and the wavelets