基于CPLD和多处理器结构的控制网络节点设计

节点是控制网络系统的基本构成单元。论文提出了一种基于CPLD和多处理器结构的控制网络节点设计方法。它能够提高单节点的并行处理能力,其模块化结构增强了节点的可靠性;不同处理器之间的连接形式可以通过VHDL等软件在线改变,使得节点柔性与扩展性提高。同时,其软件可按照不同处理器模块分步开发,软件结构也得以简化,有利于节点的调试。遵循该方法,成功开发出一种多功能LonWorks控制网络节点。     

Modeling and evaluating the time overhead induced by BER in COMA multiprocessors

Designing multiprocessors based on distributed shared memory (DSM) architecture considerably increases their scalability. But as the number of nodes in a multiprocessor increases, the probability of encountering failures in one or more nodes of the system raises as a serious problem. Thus, every large-scale multiprocessor should be equipped with mechanisms that tolerate node failures. Backward error recovery (BER) is one of the most feasible strategies to build fault tolerant multiprocessors and it can be shown that among various DSM-based architectures, cache only memory architecture (COMA) is the most suitable for implementing BER. The main reason is the existence of built-in mechanisms for data replication in COMA memory system. BER is applicable to COMA multiprocessors with minor hardware redundancy, but it will obviously cause some other kinds of overheads. The most important overhead induced by BER is the time required to produce and store recovery data. This paper introduces an analytical model for predicting the amount of this time overhead and then verifies the correctness of the model through comparing the results predicted from this model with the previously published simulation results. Both the analytical model and simulation results show that the overhead is nearly independent of the number of nodes. The immediate result is that BER is a cost-effective strategy for tolerating node failures in large-scale COMA multiprocessors with large numbers of nodes.     

一种用于VoIP的负载平衡对等网络架构

针对VoIP应用,提出了一种负载平衡的对等网络架构。该架构基于Chord对等网络,采用动态更改节点标识的方法平衡各个节点上的注册用户负载。根据两个阈值,监测节点的注册用户负载量,根据负载量使用两种方法实现节点间负载的平衡,以减少节点间负载的转移对网络带宽的额外占用。仿真实验结果表明,单个节点的最大注册用户负载量和节点负载量均方差均小于Chord对等网络。基于该架构实现的对等网络,单个节点资源占用少,适于在资源受限的嵌入式VoIP终端上实现。     

基于MC13213的无线多跳信报箱告知系统设计

为了实现对多层住宅信报箱报件到达的自动检测,提出了一种基于MC13213的无线多跳信报箱告知系统,并完成系统的软硬件设计。该系统的硬件部分主要包括报箱内的检测节点和用户住宅的用户节点,二者直接或以多跳方式通信。软件部分采用ColdWarrior进行编程,分别完成对报件到达检测并发送无线信号、接收报件到达数据或为上层楼层转发数据。设计实现了多层住宅信报箱报件到达检测与告知,避免了报件和信息延误。     

Performance evaluation of transaction processing couplingarchitectures for handling system dynamics

As the demand for high volume transaction processing grows, coupling multiple computing nodes becomes increasingly attractive. This paper presents a comparison on the resilience of the performance to system dynamics of three architectures for transaction processing. In the shared nothing (SN) architecture, neither disks nor memory is shared. In the shared disk (SD) architecture, all disks are accessible to all nodes while in the shared intermediate memory (SIM) architecture, a shared intermediate level of memory is introduced. A transaction processing system needs to be configured with enough capacity to cope with the dynamic variation of load or with a node failure. Three specific scenarios are considered: 1) a sudden surge in load of one transaction class, 2) varying transaction rates for all transaction classes, and 3) failure of a single processing node. We find that the different architectures require different amounts of capacity to be reserved to cope with these dynamic situations. We further show that the data sharing architecture, especially in the case with shared intermediate memory, is more resilient to system dynamics and requires far less contingency capacity compared to the SN architecture     

SUPRENUM: A trendsetter in modern supercomputer development

The designer of a numerical supercomputer is confronted with fundamental design decisions stemming from some basic dichotomies in supercomputer technology and architecture. On the side of the hardware technology there exists the dichotomy between the use of very high-speed circuitry or very large-scale integrated circuitry. On the side of the architecture there exists the dichotomy between the SIMD vector machine and the MIMD multiprocessor architecture. In the latter case, the ‘nodes’ of the system may communicate through shared memory, or each node has only private memory, and communication takes place through the exchange of messages. All these design decisions have implications with respect to performance, cost-effectiveness, software complexity, and fault-tolerance.

In the paper the various dichotomies are discussed and a rationale is provided for the decision to realize the SUPRENUM supercomputer, a large ‘number cruncher’ with 5 Gflops peak performance, in the form of a massively parallel MIMD/SIMD multicomputer architecture. In its present incorporation, SUPRENUM is configurable to up to 256 nodes, where each node is a pipeline vector machine with 20 Mflops peak performance, IEEE double precision. The crucial issues of such an architecture, which we consider the trendsetter for future numerical supercomputer architecture in general, are on the hardware side the need for a bottleneck-free interconnection structure as well as the highest possible node performance obtained with the highest possible packaging density, in order to accommodate a node on a single circuit board. On the side of the system software the design goal is to obtain an adequately high degree of operational safety and data security with minimum software overhead. On the side of the user an appropriate program development environment must be provided. Last but not least, the system must exhibit a high degree of fault tolerance, if for nothing else but for the sake of obtaining a sufficiently high MTBF.

In the paper a detailed discussion of the hardware and software architecture of the SUPRENUM supercomputer, whose design is based upon the considerations discussed, is presented. A largely bottleneck-free interconnection structure is accomplished in a hierarchical manner: the machine consists of up to 16 ‘clusters’, and each cluster consists of 16 working ‘nodes’ plus some organisational nodes. The node is accommodated on a single circuit board; its architecture is based on the principle of data structure architecture explained in the paper. SUPRENUM is strictly a message-based system; consequently, the local node operating system has been designed to handle a secured message exchange with a considerable degree of hardware support and with the lowest possible software overhead. SUPRENUM is organized as a distributed system—a prerequisite for the high degree of fault tolerance required; therefore, there exists no centralized global operating system. The paper concludes with an outlook on the performance limits of a future supercomputer architecture of the SUPRENUM type.     

An adaptive associative memory system based on autonomous reaction between image memories

To construct a “thinking-like” processing system, a new architecture of an adaptive associative memory system is proposed. This memory system treats “images” as basic units of information, and adapts to the environment of the external world by means of autonomous reactions between the images. The images do not have to be clear, distinct symbols or patterns; they can be ambiguous, indistinct symbols or patterns as well. This memory system is a kind of neural network made up of nodes and links called a localist spreading activation network. Each node holds one image in a localist manner. Images in high-activity nodes interact autonomously and generate new images and links. By this reaction between images, various forms of images are generated automatically under constraints of links with adjacent nodes. In this system, three simple image reaction operations are defined. Each operation generates a new image by combining pseudofigures or features and links of two images. This work was presented, in part, at the Fourth International Symposium on Artificial Life and Robotics, Oita, Japan, January 19–22, 1999     

Token-ordered LRU: an effective page replacement policy and its implementation in Linux systems

Most computer systems use a global page replacement policy based on the LRU principle to approximately select a Least Recently Used page for a replacement in the entire user memory space. During execution interactions, a memory page can be marked as LRU even when its program is conducting page faults. We define the LRU pages under such a condition as false LRU pages because these LRU pages are not produced by program memory reference delays, which is inconsistent with the LRU principle. False LRU pages can significantly increase page faults, even cause system thrashing. This poses a more serious risk in a large parallel systems with distributed memories because of the existence of coordination among processes running on individual node. In the case, the process thrashing in a single node or a small number of nodes could severely affect other nodes running coordinating processes, even crash the whole system. In this paper, we focus on how to improve the page replacement algorithm running on one node.

After a careful study on characterizing the memory usage and the thrashing behaviors in the multi-programming system using LRU replacement. we propose an LRU replacement alternative, called token-ordered LRU, to eliminate or reduce the unnecessary page faults by effectively ordering and scheduling memory space allocations. Compared with traditional thrashing protection mechanisms such as load control, our policy allows more processes to keep running to support synchronous distributed process computing. We have implemented the token-ordered LRU algorithm in a Linux kernel to show its effectiveness.     

异构集群节点与作业特性感知资源分配算法

为了避免多应用间的资源争用,Spark采用了FIFO、FAIR等作业调度策略,辅以SpreadOut和非SpreadOut两种资源调度算法,但是这些算法没有充分考虑用户作业类型和集群节点性能的相互关系。用户作业类型及节点性能偏向感知的资源调度算法ATNPA提出了对该问题的解决方案。ATNPA根据作业运行所需的内存量和CPU核数将用户作业分为CPU密集型和内存密集型。节点的性能偏向性由节点的静态因素和动态因素决定。静态因素包括CPU速度、内存大小、CPU核数和磁盘容量等;动态因素包括CPU剩余率、内存剩余率、磁盘剩余率和磁盘读写速度等。ATNPA算法在进行资源分配时,能够将作业分配到最适合其类型的节点上。仿真实验表明,与未考虑节点和作业匹配的算法相比较,ATNPA能够有效缩短作业的执行时间、提高集群的性能。     

Quantitative characterization and analysis of the I/O behavior of acommercial distributed-shared-memory machine

This paper presents a unified evaluation of the I/O behavior of a commercial clustered DSM machine, the HP Exemplar. Our study has the following objectives: 1) To evaluate the impact of different interacting system components, namely, architecture, operating system, and programming model, on the overall I/O behavior and identify possible performance bottlenecks, and 2) To provide hints to the users for achieving high out-of-box I/O throughput. We find that for the DSM machines that are built as a cluster of SMP nodes, integrated clustering of computing and I/O resources, both hardware and software, is not advantageous for two reasons. First, within an SMP node, the I/O bandwidth is often restricted by the performance of the peripheral components and cannot match the memory bandwidth. Second, since the I/O resources are shared as a global resource, the file-access costs become nonuniform and the I/O behavior of the entire system, in terms of both scalability and balance, degrades. We observe that the buffered I/O performance is determined not only by the I/O subsystem, but also by the programming model, global-shared memory subsystem, and data-communication mechanism. Moreover, programming-model support can be used effectively to overcome the performance constraints created by the architecture and operating system. For example, on the HP Exemplar, users can achieve high I/O throughput by using features of the programming model that balance the sharing and locality of the user buffers and file systems. Finally, we believe that at present, the I/O subsystems are being designed in isolation, and there is a need for mending the traditional memory-oriented design approach to address this problem     

Weapon-target assignment in unreliable peer-to-peer architecture based on adapted artificial bee colony algorithm

It is of great significance for headquarters in warfare to address the weapon-target assignment(WTA)problem with distributed computing nodes to attack targets simultaneously from different weapon units.However,the computing nodes on the battlefield are vulnerable to be attacked and the communication environment is usually unreliable.To solve the WTA problems in unreliable environments,this paper proposes a scheme based on decentralized peer-to-peer architecture and adapted artificial bee colony(ABC)optimization algorithm.In the decentralized architecture,the peer computing node is distributed to each weapon units and the packet loss rate is used to simulate the unreliable communication environment.The decisions made in each peer node will be merged into the decision set to carry out the optimal decision in the decentralized system by adapted ABC algorithm.The experimental results demonstrate that the decentralized peer-to-peer architecture perform an extraordinary role in the unreliable communication environment.The proposed scheme preforms outstanding results of enemy residual value(ERV)with the packet loss rate in the range from 0 to 0.9.     

开放式环境下一种基于信任度的RBAC模型

在开放式环境中,用户和资源的高流动性会导致基于角色的访问控制(RBAC)模型在角色指派和权限控制方面异常复杂。为此,提出一种基于信任度的弹性RBAC模型。利用评价机制确定用户与资源间的直接信任度及资源之间的推荐信任度,综合2种信任度计算用户的信任度和资源的权威度,结合用户的访问记录,为用户分配合理的角色和权限,并采用加性增、乘性减算法动态调整实体的信任度,从而防止恶意行为。基于Query Cycle Simulator的实验结果证明,该模型可以保证评价的合理性和准确性。     

Key management in wireless sensor networks

ABSTRACT

We refer to a distributed architecture consisting of sensor nodes connected by wireless links and organized in a tree-shaped hierarchy. We present a paradigm for the management of the cryptographic keys used by nodes to communicate, and we consider the problems connected with key generation, distribution, and replacement. In our paradigm, names are assigned to nodes by using a uniform scheme, which is based on the position of the given node in the node hierarchy. Each node holds a hierarchical key to communicate with its ancestors, and a level key to communicate with its siblings. A single, publicly known parametric one-way function is used to assign hierarchical keys to nodes, in an iterative procedure that starts from the key of the root of the node hierarchy, and proceeds downwards to the lowest hierarchical levels. A similar procedure is used to generate the level keys. The total memory requirements for key storage are extremely low. The number of keys exchanged in a key replacement process is kept to a minimum. Dynamic access control is fully supported, whereby new nodes can be added to the node hierarchy, and existing nodes can be evicted from the hierarchy.     

Prospects for Optical Interconnects in Distributed,Shared-Memory Organized MIMD Architectures

The antipodes of the class of sequential computers, executing tasks with a single CPU, are the parallel computers containing large numbers of computing nodes. In the shared-memory category, each node has direct access through a switching network to a memory bank, that can be composed of a single but large or multiple but medium sized memory configurations. Opposite to the first category are the distributed memory systems, where each node is given direct access to its own local memory section. Running a program in especially the latter category requires a mechanism that gives access to multiple address spaces, that is, one for each local memory. Transfer of data can only be done from one address space to another. Along with the two categories are the physically distributed, shared-memory systems, that allow the nodes to explore a single globally shared address space. All categories, the performances of which are subject to the way the computing nodes are linked, need either a direct or a switched interconnection network for inter-node communication purposes. Linking nodes and not taking into account the prerequisite of scalability in case of exploiting large numbers of them is not realistic, especially when the applied connection scheme must provide for fast and flexible communications at a reasonable cost. Different network topologies, varying from a single shared bus to a more complex elaboration of a fully connected scheme, and with them the corresponding intricate switching protocols have been extensively explored. A different vision is introduced concerning future prospects of an optically coupled distributed, shared-memory organized multiple-instruction, multiple-data system. In each cluster, an electrical crossbar looks after the interconnections between the nodes, the various memory modules and external I/O channels. The clusters itself are optically coupled through a free space oriented data distributing system. Analogies found in the design of the Convex SPP1000 substantiate the closeness to reality of such an architecture. Subsequently to the preceding introduction also an idealized picture of the fundamental properties of an optically based, fully connected, distributed, (virtual) shared-memory architecture is outlined.     

一种适用于数据网格环境的节点管理策略

针对数据网格的需求,将系统中的节点根据管理域以及网络邻近特性进行组织,同时,根据管理的需求以及节点自身的处理能力,将其组织成为一个分层同构的体系结构.加入系统中的节点粒度可以任意调整,而粗粒度的节点内部对于系统中其他节点是透明的,提高了系统的灵活性,并提高了系统的可扩展性与可管理性.系统中的节点之间根据不同的数据访问规则构成一个多层次、跨管理域的分布式合作缓存,从而降低了主干网带宽的压力.     

DataScalar: A memory-centric approach to computing

Commodity microprocessors contain more on-chip memory with each successive generation, and will contain tens of megabytes within the decade. We describe a novel architecture that runs an unmodified uniprocessor program across multiple nodes, each of which contains a processor tightly integrated with a sizable memory. The execution of instructions is replicated, while the access of operands is distributed across the nodes. Each node accesses operands in its fast local memory and broadcasts them to the other nodes. This architecture exploits out-of-order execution and the fact that each chip has integrated processor and memory, to run memory-intensive, hard-to-parallelize programs more efficiently. In this paper, we describe an implementation with specific solutions to the unique problems that this architecture poses. Finally, we conclude by comparing simulation results of our implementation to more traditional equivalent systems. In our simulated implementation, five unmodified SPEC95 binaries ran – in most cases – considerably faster than in systems with more traditional memory systems.     

Memory and Network Architecture Interaction in an Optically Interconnected Distributed Shared Memory System

This paper develops a performance model of an optically interconnected parallel computer system operating in a distributed shared memory environment. The performance model is developed to reflect the impact of low level optical media access protocol and optical device switching latency on high level system performance. This enables the model to predict the performance impact of supporting distributed shared memory with different address allocation schemes and media access protocols. The passive star-coupled photonic network operates through wavelength division multiple access. Two media access protocols are examined for this WDM network, both are designed to operate in a multiple-channel multiple-access environment and require each node to possess a wavelength tunable transmitter and a fixed (or slow tunable) receiver. A semi-Markov model has been developed to study the interaction of the distributed shared memory architecture and the two access protocols of the photonic network. This analytical model has been validated by extensive simulation. The model is then used to examine the system performance with varying numbers of nodes and wavelength channels and varying, memory and channel access times.     

传感器网络结点OS内存管理的设计与实现

传感器网络的结点是基于嵌入式设备的计算机系统,该系统对功能、可靠性、成本、体积、功耗有严格要求,系统中的每个任务、设备以及网络的连接都要求有足够的存储空间,因此选择适合的内存管理算法,高效地利用存储空间,是提高系统性能的一个重要方面。该文以自主开发的传感器结点操作系统SNNEOS为背景,重点讨论了传感器网络结点操作系统内存管理的分配算法与回收算法,为传感器结点的内存管理提供了一个有效的解决方案。     

节能无线传感网络系统设计

Wireless sensor networks have already enabled numerous embedded wireless applications such as military, environmental monitoring, intelligent building, etc. Because micro-sensor nodes are supposed to operate for months or even years with very limited battery power source, it is a challenge for researchers to obtain long operating hour without scarifying original system performances. In this paper, the energy consumption sources of the wireless sensor networks are firstly analyzed, with the digital processing and radio transceiver units being emphasized. Then, we introduce the design scheme of our energy-aware wireless sensor network (GAINS). In GAINS, techniques to conserve the energy are exploited including the energy optimization node, software and energy-efficient communication protocol. The design architecture of our ultra low power wireless sensor network (WO-LPP) is specially presented.     

Real-Time Image Processing with a MIMD Computer

Image processing applications require both computing and communication power. The aim of the GFLOPS project was to study all aspects concerning the design of such computers. The projects' aim was to develop a parallel architectures well as its software environment to implement those applications efficiently. The proposed architecture supports up to 512 processor nodes, connected over a scalable and cost-effective network at a constant cost per node. The first prototype implementation, running since the beginning of 1995, has shown that a parallel system can be both scalable and programmable through the use of a virtually shared memory paradigm, physically implemented with atomic message passing. GFLOPS-2 is a single-user machine which is designed to be used as a low-cost parallel co-processor board in a desk-top work station. In this paper we discuss the design of the GFLOPS-2 machine and evaluate the effectiveness of the mechanisms incorporated. The analysis of the architecture behaviour has been conducted with image processing and general purpose algorithms, written in C and assembler languages, through execution driven simulations. A development environment, especially a C data-parallel language, has been built for this purpose.