一种欠采样应用的高精度低功耗采样/保持电路

设计了一种可用于欠采样情况的高精度、低功耗采样/保持电路。在40 MHz时钟频率下,采样90 MHz输入信号时可达11位以上精度。采用电容翻转结构的采样/保持电路,以消除电容失配的影响;使用栅压自举开关,以提高线性度,实现欠采样输入;并设计了一种高增益、大带宽、低功耗的增益自举套筒式共源共栅(telescopic cascode)运算放大器。电路采用SMIC 0.35μmCMOS工艺实现,电源电压为3.3 V,功耗仅为7.6 mW。     

一种用于12位250MSPS流水线ADC的中频采样前端

设计了一种具有中频采样功能的流水线ADC采样保持前端电路.采样保持前端电路采用基于开关电容的底板采样翻转式结构,运算放大器采用了米勒补偿型两级结构以提高信号摆幅,采样开关采用了消除衬底偏置效应的自举开关以提高中频采样特性.该采样保持前端电路被运用于一种12位250 MSPS流水线ADC,电路采用0.18μm lP5M 1.8 V CMOS工艺实现,测试结果表明该ADC电路在全速采样条件下对于20 MHz的输入信号得到的SNR为69.92 dB,SFDR为81.17 dB,-3 dB带宽达700 MHz以上,整个前端电路的功耗为58 mW.     

5 Msample/s两倍增益差分采样/保持电路的设计和分析

设计和分析了一种用于10位分辨率,5 MHz采样频率流水线式模数转换器中的差分采样/保持电路.该电路是采用电容下极板采样、开关栅电压自举、折叠式共源共栅技术进行设计,有效地消除了开关管的电荷注入效应、时钟馈通效应引起的采样信号的误差,提高了采样电路的线性度,节省了芯片面积、功耗.电路是在0.6 μm CMOS工艺下进行模拟仿真,当输入正弦波频率为500 kHz,采样频率为5 MHz时,电路地无杂散动态范围(SFDR)为75.4 dB,能够很好的提高电路的信噪比,因此该电路适用于流水线式模数转换器.     

一种具有采样带宽补偿的高性能采样/保持电路

针对中频采样模数装换器中的宽带采样/保持电路,提出了一种新颖的电荷交换补偿（CEC）技术.该技术通过消除采样开关有限导通电阻的影响,补偿了采样带宽,并避免了时钟馈通和电荷注入的加剧.同时设计了具有AB类输出的低功耗两级运放,在1.8V电源下为该采样/保持提供了3V峰-峰值的输入范围.该采样/保持电路在100Ms/s的采样率下,对于200MHz输入信号达到了94dB的无杂散动态范围.在5.5pF的负载下,功耗仅为26mW.     

一种具有采样带宽补偿的高性能采样/保持电路

针对中频采样模数装换器中的宽带采样/保持电路,提出了一种新颖的电荷交换补偿(CEC)技术.该技术通过消除采样开关有限导通电阻的影响,补偿了采样带宽,并避免了时钟馈通和电荷注入的加剧.同时设计了具有AB类输出的低功耗两级运放,在1.8V电源下为该采样/保持提供了3V峰-峰值的输入范围.该采样/保持电路在100Ms/s的采样率下,对于200MHz输入信号达到了94dB的无杂散动态范围.在5.5pF的负载下,功耗仅为26mW.     

一种采用双采样技术的高性能采样保持电路

介绍了一种高性能的采样保持电路。他采用双采样结构,使得在同样性能的运算放大器条件下,采样速率成倍提高,降低对运放的要求;使用补偿技术的两级运算放大器有较高增益和输出摆幅;采用栅压自举电路,消除开关导通电阻的非线性,减小电荷注入效应和时钟溃通。在SMIC 0.25μm标准工艺库下仿真,该采样保持电路可试用于高速高精度流水线ADC。     

一种用于14bit 50MHz流水线模数转换器的CMOS采样开关

分析了影响CMOS采样开关性能的非理想因素,针对14bit 50MHz A/D转换器对采样开关特性的要求,提出了一种新型的时钟馈通补偿结构.该结构通过增加dummy开关管能够有效消除时钟馈通对采样值的影响,打破了开关设计中速度和精度之间的制约关系.基于SMIC 0.25μm标准CMOS数模混合工艺,采用Hspice对电路进行了模拟.模拟结果显示,在输入信号为23.3MHz正弦波,峰峰值为2V,采样时钟频率为50MHz,时钟上升/下降时间为0.1ns时,无杂散动态范围达到92dB,信噪失真比达到83dB;同时时钟馈通效应造成的保持误差由5.5mV降为90μV.这种具有时钟馈通补偿结构的采样开关特别适用于高速高分辨率模数转换器.     

一种具有高线性度MOS采样开关的采样保持电路

通过采样保持电路中运放的复用,提出了一种具有高线性度MOS采样开关的模数转换器前端采样保持电路结构。这种结构可以显著降低采样开关导通电阻变化引入的非线性,从而在不增加开关面积和功耗的情况下,实现了高性能的采样保持电路。基于0.13?m的标准CMOS工艺,对提出的采样保持电路进行了仿真。在采样时钟频率为100MHz,输入信号频率1MHz时,仿真结果显示,无杂散动态范围(SFDR)达到了116.6dB,总谐波失真(THD)达到了112.7dB,信号谐波噪声比（SNDR）达到103.7dB,可以满足14比特流水线ADC对采样保持电路的要求。     

一种用于14bit 50MHz流水线模数转换器的CMOS采样开关

分析了影响CMOS采样开关性能的非理想因素,针对14bit 50MHz A/D转换器对采样开关特性的要求,提出了一种新型的时钟馈通补偿结构.该结构通过增加dummy开关管能够有效消除时钟馈通对采样值的影响,打破了开关设计中速度和精度之间的制约关系.基于SMIC 0.25μm标准CMOS数模混合工艺,采用Hspice对电路进行了模拟.模拟结果显示,在输入信号为23.3MHz正弦波,峰峰值为2V,采样时钟频率为50MHz,时钟上升/下降时间为0.1ns时,无杂散动态范围达到92dB,信噪失真比达到83dB;同时时钟馈通效应造成的保持误差由5.5mV降为90μV.这种具有时钟馈通补偿结构的采样开关特别适用于高速高分辨率模数转换器.     

一种10位100MHz采样/保持电路的设计

描述了一种采用0.35μmBicmos工艺设计的全差分采样/保持电路,该电路采用全差分结构和辅助时钟设计以及在采样/保持电路中增加两个小电容,有效地减小了电荷注入的影响,同时通过时钟提升电路的设计,提高了采样速度.在Cadence的SPECTRE下仿真,结果表明该电路在3.3V电源电压、100MHz的采样频率下能稳定工作.     

A high-speed sample-and-hold circuit based on CMOS transmission lines

We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS TLs exhibit filter properties, which cause attenuation and deformation of signal pulses. Nevertheless, the dispersion effects on clock pulse propagation are minimal since clock lines are short, much shorter than the meandered input-signal line. Design considerations on clock pulse generator, sampling switches, and charge amplifiers are presented. Compared with other CMOS approaches, the proposed SHC generates clock pulses on chip and avoids clock jitter difficulties. The SHC is implemented in a 0.13 μm digital CMOS process with standard on-chip coplanar waveguides (CPW) as signal and clock pulse propagation TLs, silicon N-type field effect transistors (NFET) as sampling switches, and high-frequency charge amplifiers for charge amplification. Clock pulse signals of ~50 ps width with ~17 ps fall edge are generated on-chip. Simulation analysis with Cadence Spectre shows that a sampling rate of 20 Giga-sample/s with a 25 dB spurious free dynamic range (SFDR) can be achieved. With shorter clock pulses, both sampling rate and SFDR can be improved in future design.     

3.5 GHz operation of a superconducting packet switch element

The paper introduces a prototype model of a superconducting packet switch which is composed of an input buffer, a contention solver, and a distribution network. The input buffer and the contention solver enable contention-free distribution of data packets. The total design of the prototype has been completed and the total operation has been numerically simulated and confirmed. A 2×2 switching element which controls the paths of two packets is the key component of the prototype. The basic switching element with 1-b data-width is fabricated by a standard Nb trilayer process. Three-junction SQUIDs driven by a three-phase powering clock are used in the switch. The correct operation up to 3.5 GHz, limited by the measurement setup, is confirmed. The margin evaluation shows there remains enough margin at GHz operations     

A 1.5 V 10-b 30-MS/s CMOS pipelined analog-to-digital converter

A 1.5 V 10-b 30MS/s CMOS pipelined analog-to-digital converter (ADC) is described. Low-voltage techniques are proposed for pipelined analog-to-digital converter that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough and enhance the dynamic performance of the pipelined ADC. Multiplying digital-to-analog converter (MDAC) with cross-coupled configuration also provides an effective common-mode feedback to overcome the problem of common-mode accumulation. The prototype chips have been fabricated and experimental results confirm the feasibility of this new technique.     

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20MS/s and 54-dB S/N at 30 MS/s

A new video-speed current-mode CMOS sample-and-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feed through, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6-μm MOS devices with normal threshold voltages (V_th) of +0.7 V (nMOS) and -0.7 V (pMOS)     

All optical signal regularizing/regeneration using a nonlinearfiber Sagnac interferometer switch with signal-clock walk-off

All-optical signal regularizing/regeneration using a nonlinear fiber Sagnac interferometer switch (NSIS) that employs signal-clock walk-off is investigated. The NSIS realizes all-optical signal regeneration, including timing and amplitude regularizing, by switching clock pulses with amplified input signals using a walk-off-induced, wide, square switching window and intensity-dependent transmittance of the device. First, characteristics (in both the temporal and spectral domains) of the all-optical signal regeneration achieved with the NSIS are investigated theoretically and experimentally. They certify that if clock pulses are within the square switching window obtained with signal-clock walk-off, the clock pulses can be modulated according to the data that the input signals carry and retain their temporal and spectral profiles. This means that if clock pulses can be prepared that meet the system requirements, the NSIS can convert input signals that may not satisfy system requirements into high-quality output signals. Limitations on the switching contrast due to the cross-phase modulation of counterpropagating reference pulses is also discussed. Second, two possible applications of NSIS-based all-optical signal regularizing/regeneration, 1) an all-optical multiplexer with an optical clock and 2) an all-optical regenerative repeater, are discussed. Preliminary experiments with ~10-ps pulses at bit rates of ~5 Gb/s that use locally prepared optical clock pulses, show that the NSIS provides an error-free regeneration function with a certain tolerance for pulse-period irregularity if a proper optical clock is obtained     

Wide Dynamic Range All-Optical Clock and Data Recovery From Preamble-Free NRZ-DPSK Packets

We demonstrate an all-optical circuit that simultaneously performs packet-by-packet clock recovery (CR) and data demodulation from 10-Gb/s nonreturn-to-zero differential-phase-shift-keying packets. It includes a novel power equalizer based on a nonlinear self-polarization switch in a semiconductor optical amplifier that enables operations within 15-dB input power level fluctuations. Data demodulation is realized by a Gaussian narrow filter that simultaneously seeds a stage performing CR. CR is performed by a Fabry-Peacuterot filter-based circuit. By using the input packets as a gating signal, the circuit is able to extract clock packets with 0-bit rise and fall times. The circuit can operate asynchronously and with arbitrary packet length     

A Novel Integrated CMOS Switch Circuit for High Precision Sample-and-Hold Technique

A new CMOS switch circuit is proposed for the implementationof high precision sample-and-hold. The switch includes a currentmirror and switching action is controlled by current pulses.This reduces charge injection due to clock feedthrough and thecharge injection is input signal independent, resulting in agreatly improved sample-and-hold accuracy.     

A novel low distortion high linearity CMOS bootstrapped switch

This paper proposes a novel low distortion high linearity CMOS bootstrapped switch, and the proposed switch can alleviate the nonlinear distortion of the on-resistance by eliminating first order signal-dependent variation of the overdrive voltage. Based on a 0.18 μm standard CMOS process, the simulation results show that at 100 MHz sampling clock frequency and 49 MHz input signal with 2 Vpp, the proposed switch in differential mode has a Spurious-Free Dynamic Range （SFDR） of 90.1 dB.     

A low-voltage CMOS switch with a novel clock boosting scheme

There is a strong demand for an input switch in switched-capacitor circuits, covering rail-to-rail signal swing when low power-supply voltages are used. This brief proposes a novel clock-boosting scheme. The generated clock voltages of this new circuit are applied to a regular CMOS transmission gate to implement a simple and robust sampling switch when the supply voltages are very low. In this new approach, during the sampling phase, the gate-voltage of an nMOS switch is boosted up to V/sub dd/+k/spl middot/V/sub dd/, and the gate voltage of a pMOS switch is lowered to V/sub gnd/-k/spl middot/V/sub dd/, where k can be made programmable, and is usually smaller than 1. This allows sampling of the full signal swing, even when supply voltages are lower than |V/sub th/,p|+V/sub th/,n without applying extreme stress to the gate oxide of a transistor.     

Logic drive circuit for 3-phase charge-coupled devices

A simple logic circuit is escribed which acts as a modulo-3 ring counter and provides three driving phases suitable to operate a 3-phase c.c.d. The circuit is driven by a clock, the rate of which corresponds to three times the desired element rate in the c.c.d. The pulsewidth of the clock determines the amount of mutual overlap between subsequent phases. An additional gating input permits stopping the counter in a predetermined state, such as would be required to switch a c.c.d. into the integration mode. The circuit contains only 12 gates, and when implemented with a t.t.l. high-speed logic component runs up to input clock rates of 50 MHz.