ODAM: An optimized distributed association rule mining algorithm

Association rule mining is an active data mining research area. However, most ARM algorithms cater to a centralized environment. In contrast to previous ARM algorithms, we have developed a distributed algorithm, called optimized distributed association mining, for geographically distributed data sets. ODAM generates support counts of candidate itemsets quicker than the other DARM algorithms and reduces the size of average transactions, data sets, and message exchanges.     

Variable-size interleaver design for parallel turbo decoder architectures

In this paper, we propose two techniques to design good S-random interleavers, to be used in parallel and serially concatenated codes with interleavers. The interleavers designed according to these algorithms can be shortened, in order to support different block lengths in such a way that all the permutations obtained by pruning, when employed in a parallel turbo decoder, are collision-free. The first technique, suitable for short and medium interleavers, guarantees the same performance of nonparallel interleavers in terms of spreading properties, simulated frame-error probabilities, and obtainable minimum distance of the actual codes. The second algorithm, to be used for large block lengths, permits achieving high degrees of parallelism at the price of a slight degradation of the spread properties, and also to change the degree of parallelism on-the-fly. The operations of a parallel turbo decoder employing these interleavers are described, and an example of the advantages of the proposed techniques is provided in a realistic system framework.     

Design and implementation of a distributed evolutionary computing software

Although evolutionary algorithm is a powerful optimization tool, its computation cost involved in terms of time and hardware resources increases as the size or complexity of the problem increases. One promising approach to overcome this limitation is to exploit the inherent parallelism of evolutionary algorithms by creating an infrastructure necessary to support distributed evolutionary computing using existing Internet and hardware resources. This paper presents a Java-based distributed evolutionary computing software (Paladin-DEC), which enhances the concurrent processing and performance of evolutionary algorithms by allowing inter-communications of subpopulations among various computers over the Internet. Such a distributed system enables individuals to migrate among multiple subpopulations according to some patterns to induce diversity of elite individuals periodically, in a way that simulates the species evolve in natural environment. The Paladin-DEC software is capable of keeping data integrity throughout the computation, and is incorporated with the features of robustness, security, fault tolerance, and work balancing. The effectiveness and advantages of the Paladin-DEC are illustrated upon two case studies of drug scheduling in cancer chemotherapy and searching probe sets of yeast genome.     

Hardware-accelerated design space exploration framework for communication systems

The efficient hardware implementation of signal processing algorithms requires a rigid characterization of the interdependencies between system parameters and hardware costs. Pure software simulation of bit-true implementations of algorithms with high computational complexity is prohibitive because of the excessive runtime. Therefore, we present a field-programmable gate array (FPGA) based hybrid hardware-in-the-loop design space exploration (DSE) framework combining high-level tools (e.g. MATLAB, C++) with a System-on-Chip (SoC) template mapped on FPGA-based emulation systems. This combination significantly accelerates the design process and characterization of highly optimized hardware modules. Furthermore, the approach helps to quantify the interdependencies between system parameters and hardware costs. The achievable emulation speedup using bit-true hardware modules is a key enabling the optimization of complex signal processing systems using Monte Carlo approaches which are infeasible for pure software simulation due to the large required stimuli sets. The framework supports a divide-and-conquer approach through a flexible partitioning of complex algorithms across the system resources on different layers of abstraction. This facilitates to efficiently split the design process among different teams. The presented framework comprises a generic state of the art SoC infrastructure template, a transparent communication layer including MATLAB and hardware interfaces, module wrappers and DSE facilities. The hardware template is synthesizable for a variety of FPGA-based platforms. Implementation and DSE results for two case studies from the different application fields of synthetic aperture radar image processing and interference alignment in communication systems are presented.     

Design and Implementation of Web-Based Control Laboratory for Test Rigs in Geographically Diverse Locations

This paper compares current remote laboratories and describes the design and implementation of the Networked Control System Laboratory (NCSLab) in the University of Glamorgan on http://www/ncslab.net, which provides a unified and flexible Web-based interface to access test rigs located in different countries of the world. All the test rigs are connected and managed together by the NCSLab system. They are well cataloged by their characteristics, and their geographical locations are not necessarily known to the users. A three-layer structure, which consists of the main server, subservers, and test rigs, is adopted to organize the distributed facilities. All the control algorithms for the test rigs are generated by using the Matlab Real-time Workshop. Users can design and implement their own control algorithms for the test rigs. The Web interface is designed using Java JSP/Servlet technology which gives the users great flexibility, including remote tuning, remote monitoring (both data and videos), and remote control logics. In order to manage the massive information and support concurrent access, MySQL database is also integrated into the system.     

利用硬件抽象机模拟执行技术设计JAVA处理器

提出了一个基于硬件抽象机的流水线微处理器设计框架,创造性地使用了一种基于标签结构的模拟执行技术.基于这一框架,描述了一个堆栈抽象机的工作原理,实现了一个Java指令级并行处理器.利用堆栈硬件抽象机和堆栈指令折叠技术的组合解决了Java处理器中的堆栈依赖瓶颈问题.软件模拟证明了该处理器能够最大限度地挖掘出Java程序中的指令级并行,并且拥有更高的处理能力.     

Noise properties of chord-image reconstruction

Recently, there has been much progress in algorithm development for image reconstruction in cone-beam computed tomography (CT). Current algorithms, including the chord-based algorithms, now accept minimal data sets for obtaining images on volume regions-of-interest (ROIs) thereby potentially allowing for reduction of X-ray dose in diagnostic CT. As these developments are relatively new, little effort has been directed at investigating the response of the resulting algorithm implementations to physical factors such as data noise. In this paper, we perform an investigation on the noise properties of ROI images reconstructed by using chord-based algorithms for different scanning configurations. We find that, for the cases under study, the chord-based algorithms yield images with comparable quality. Additionally, it is observed that, in many situations, large data sets contain extraneous data that may not reduce the ROI-image variances.     

Wise-ShopFloor: An Integrated Approach for Web-Based Collaborative Manufacturing

This paper presents an integrated approach for Web-based collaborative manufacturing, including distributed process planning, dynamic scheduling, real-time monitoring, and remote control. It is enabled by a Web-based integrated sensor-driven e-ShopFloor (Wise-ShopFloor) framework targeting distributed yet collaborative manufacturing environments. Utilizing the latest Java technologies (Java 3D and Java Servlet) for system implementation, this approach allows users to plan and control distant shop floor operations based on runtime information from the shop floor. The objective of this research is to develop methodology and algorithms for Web-based collaborative planning and control, supported by real-time monitoring for dynamic scheduling. Details on the principle of the Wise-ShopFloor framework, system architecture, and a proof-of-concept prototype are reported in this paper. An example of distributed process planning for remote machining is chosen as a case study to demonstrate the effectiveness of this approach toward Web-based collaborative manufacturing.     

基于回溯的最大频繁项集挖掘算法

针对Apriori类算法多次扫描数据库和FP-tree类算法需要构建大量条件模式树的问题,文中提出了挖掘最大频繁项集的GBMFI算法。采用垂直格式存储事务数据库,以枚举树为基础,利用子集非频繁性质和父子节点支持度信息在搜索过程中对枚举树进行剪枝,最终得到最大频繁项集。通过实验对比,结果证明了算法的有效性,尤其适用于稀疏数据集。     

分布式存储结构的频繁闭合模式挖掘并行算法

研究分布式存储结构下频繁闭合模式挖掘的并行化问题,针对频繁闭合模式的特点,提出了两阶段并行判断频繁模式闭合性的方法,基于串行算法FPclose和两种FP-tree的并行构造方式,分别给出了两个频繁闭合模式挖掘并行算法DP-FP和DL-FP,性能分析表明,这两个算法具有较大的并行化,较小的I/O开销与良好的负载平衡。     

基于位运算与海明距离的Apriori算法改进

关联规则现在已成为数据挖掘领域中非常重要的研究课题,用于发现隐藏在大型数据集中的令人感兴趣的联系。Apriori算法作为第一个关联规则挖掘算法,开创性地使用了基于支持度的剪枝技术,系统地控制了候选项集的指数增长。但是,Apriori算法仍然存在着频繁扫描数据库和产生大量候选项集的缺点。鉴于此,提出了用一个整型或整型数组来代替一项事务集和一项候选项集,通过数据压缩,可以一次性将海量数据载入内存,减少了磁盘I/O负载,并通过位运算与计算海明距离达到计算支持度的目的,同时使用了若干优化方法。     

A scalable mediator approach to process large biomedical 3-D images

The Edinburgh Mouse Atlas is a spatial-temporal framework to store and analyze biological data including three-dimensional (3-D) images that relate to mouse embryo development. The purpose of the system is the analysis and querying of complex spatial patterns, in particular the patterns of gene activity during embryo development. The framework holds large 3-D gray level images and is implemented in part as an object-oriented database. In this paper, we propose a dynamic layered architecture, based on the mediator approach, for the design of a transparent and scalable distributed system which can process objects that can exceed 1 GB in size. The system's data are distributed and/or declustered across a number of image servers and are processed by specialized mediators.     

Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers

This paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband processing operations in wireless base-station receivers for CDMA. Future wireless base-station receivers will need to use sophisticated algorithms to support extremely high data rates and multimedia. Current DSP implementations of these algorithms are unable to meet real-time requirements. However, there exists massive parallelism and bit level arithmetic present in these algorithms than can be revealed and efficiently implemented in a VLSI architecture. We re-design an existing channel estimation algorithm from an implementation perspective for a reduced complexity, fixed-point hardware implementation. Fixed point simulations are presented to evaluate the precision requirements of the algorithm. A dependence graph of the algorithm is presented and area-time trade-offs are developed. An area-constrained architecture achieves low data rates with minimum hardware, which may be used in pico-cell base-stations. A time-constrained solution exploits the entire available parallelism and determines the maximum theoretical data processing rates. An area-time efficient architecture meets real-time requirements with minimum area overhead.     

分布式并行数据挖掘计算框架及其算法研究

为了提供一个灵活可扩展的计算平台进行高效的挖掘计算，提出了一种应用于分布和并行环境的数据挖掘计算框架和相应的算法。通过分析关联规则挖掘理论和以往算法的优缺点，建立一种分布式并行数据挖掘的计算框架，并给出相应的求解算法。实例分析表明该计算框架能够减少节点问的通信开销，保持了良好的可扩展性：挖掘算法则利用本地节点动态有序集合枚举树生成方法代替数据库节省了本地空间的占用．大大提高了查找的计算效率。     

Mobile Java Objects

This paper gives an overview of the design of a mobile Java object infrastructure. It describes why it is helpful to group objects for mobility and how, when clusters represent untrusted pieces of code (for example mobile agents), they must be encapsulated both to control their access to other objects and to control access to them. The difficulties of managing large numbers of mobile objects in an open environment are discussed, together with a solution based on the management of large distributed name spaces. The mobile object system described has been implemented, and is currently being used to support development of mobile agent-based applications within another project. The paper also explains how the infrastructure described meets the requirements of mobile agents better than other approaches.     

FFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm,Architecture and Design Automation

Fast Fourier transform algorithms on large data sets achieve poor performance on various platforms because of the inefficient strided memory access patterns. These inefficient access patterns need to be reshaped to achieve high performance implementations. In this paper we formally restructure 1D, 2D and 3D FFTs targeting a generic machine model with a two-level memory hierarchy requiring block data transfers, and derive memory access pattern efficient algorithms using custom block data layouts. These algorithms need to be carefully mapped to the targeted platform’s architecture, particularly the memory subsystem, to fully utilize performance and energy efficiency potentials. Using the Kronecker product formalism, we integrate our optimizations into Spiral framework and evaluate a family of DRAM-optimized FFT algorithms and their hardware implementation design space via automated techniques. In our evaluations, we demonstrate DRAM-optimized accelerator designs over a large tradeoff space given various problem (single/double precision 1D, 2D and 3D FFTs) and hardware platform (off-chip DRAM, 3D-stacked DRAM, ASIC, FPGA, etc.) parameters. We show that Spiral generated pareto optimal designs can achieve close to theoretical peak performance of the targeted platform offering 6x and 6.5x system performance and power efficiency improvements respectively over conventional row-column FFT algorithms.     

Secure computing with the MPEG RVC framework

Recently, ISO/IEC standardized a dataflow-programming framework called Reconfigurable Video Coding (RVC) for the specification of video codecs. The RVC framework aims at providing the specification of a system at a high abstraction level so that the functionality (or behavior) of the system become independent of implementation details. The idea is to specify a system so that only intrinsic features of the algorithms are explicitly expressed, whereas implementation choices can then be made only once specific target platforms have been chosen. With this system design approach, one abstract design can be used to automatically create implementations towards multiple target platforms. In this paper, we report our investigations on applying the methodology standardized by the MPEG RVC framework to develop secure computing in the domains of cryptography and multimedia security, leading to the conclusion that the RVC framework can successfully be applied as a general-purpose framework to other fields beyond multimedia coding. This paper also highlights the challenges we faced in conducting our study, and how our study helped the RVC and the secure computing communities benefited from each other. Our investigations started with the development of a Crypto Tools Library (CTL) based on RVC, which covers a number of widely used ciphers and cryptographic hash functions such as AES, Triple DES, ARC4 and SHA-2. Performance benchmarking results on the RVC-based AES and SHA-2 implementations in both C and Java revealed that the automatically generated implementations can achieve a comparable performance to some manually written reference implementations. We also demonstrated that the RVC framework can easily produce implementations with multi-core support without any change to the RVC code. A security protocol for mutual authentication was also implemented to demonstrate how one can build heterogeneous systems easily with RVC. By combining CTL with Video Tool Library (a standard library defined by the RVC standard), a non-standard RVC-based H.264/AVC encoder and a non-standard RVC-based JPEG codec, we further demonstrated the benefits of using RVC to develop different kinds of multimedia security applications, which include joint multimedia encryption-compression schemes, digital watermarking and image steganography in JPEG compressed domain. Our study has shown that RVC can be used as a general-purpose implementation-independent development framework for diverse data-driven applications with different complexities.     

Object Detection, Tracking and Recognition for Multiple Smart Cameras

Video cameras are among the most commonly used sensors in a large number of applications, ranging from surveillance to smart rooms for videoconferencing. There is a need to develop algorithms for tasks such as detection, tracking, and recognition of objects, specifically using distributed networks of cameras. The projective nature of imaging sensors provides ample challenges for data association across cameras. We first discuss the nature of these challenges in the context of visual sensor networks. Then, we show how real-world constraints can be favorably exploited in order to tackle these challenges. Examples of real-world constraints are a) the presence of a world plane, b) the presence of a three-dimiensional scene model, c) consistency of motion across cameras, and d) color and texture properties. In this regard, the main focus of this paper is towards highlighting the efficient use of the geometric constraints induced by the imaging devices to derive distributed algorithms for target detection, tracking, and recognition. Our discussions are supported by several examples drawn from real applications. Lastly, we also describe several potential research problems that remain to be addressed.      

A method for Handling Inconsistencies in Rule-based Classifiers

Researches on distributed data mining have as the main interest the development of algorithms and approaches that make possible the analysis of large and physically distributed datasets proposing better solutions in terms of costs and computational complexity. In such a scenario, the handling of inconsistent classification rules, generated from distributed data sets is an important task, because inconsistencies can compromise the performance of the classifiers. The aim of this work is the development of a new methodology for knowledge integration based on Paraconsistent Logic. The method is capable to take reliable decisions in occurrence of inconsistent rules generated from a set of rule-based classifiers. The advantage of the proposed method is to avoid high flow of messages and data between distributed processors throughout the rules analysis generated from distributed data sets, because only local information is used for the generation of a global ruleset. Then, Paraconsistent Logic is used as a certainty management approach to infer the class for a test example. We could observe in the experiments done over different datasets that the method generates quite good results.     

A four-processor building block for SIMD processor arrays

A four-processor chip, for use in processor arrays for image computations, is described. The large degree of data parallelism available in image computations allows dense array implementations where all processors operate under the control of a single instruction stream. An instruction decoder shared by the four processors on the chip minimizes the pin count allocated for global control of the processors. The chip incorporates an interface to an external SRAM (static RAM) for memory expansion without glue chips. The full-custom 2-μm CMOS chip contains 56669 transistors and runs instructions at 10 MHz. Five hundred and twelve 16-b processors and 4 Mbyte of distributed external memory fit on two industry standard cards to yield 5-billion instructions per second peak throughout. As image I/O can overlap perfectly with pixel computation, an array containing 128 of these chips can provide more than 600 16-b operations per pixel on 512×512 images at 30 Hz