SMT再流焊接工艺预测与仿真技术研究现状

综述了电子电路表面组装技术（ＳＭＴ）再流焊焊接工艺仿真与预测研究的必要性、重要意义及其研究现状，并对其应用现状及其发展趋势进行了评述。     

P18-T200台式再流焊机研制成功

Ｐ１８—Ｔ２００台式再流焊机研制成功郝应征电子工业部第二研究所在广泛吸取国外再流焊机最新技术的基础上新近推出了新一代全新结构的红外再流焊机———Ｐ１８—Ｔ２００台式再流焊机。Ｐ１８—Ｔ２００台式再流焊机可焊接单面、双面各种密度的表面组装组件（ＳＭＡ）...     

国外工艺文献导读

20 0 2 0 6 0 1　焊接技术—ＫａｒｅｎＷａｌｔｅｒｓ .ＳＭＴ ,2 0 0 2 ,16(8) :4 0～ 4 4(英文 )今天 ,电子元器件除向着越来越小的方向发展以外 ,也正向着多种多样的封装形式发展 ,同时随着无铅焊料的使用 ,再流焊工艺的工艺窗将进一步缩小 ,为此再流焊工艺将面临着新的严峻挑战。监控焊膏的再流温度曲线是保证焊膏合适润湿的基本要求。粘贴热电偶到ＰＣＢ上可保证获得准确的温度 ,使板子通过再流焊炉时 ,形成良好的引线和焊盘之间的连接。一般焊膏再流温度曲线参数包括加热速率、预热温度保持时间、合金熔点温度以上保持时间、峰值温度…     

回流焊温度分布曲线图

在ＳＭＴ回流焊的整个流程中，为组装电路板合适的温度分布曲线是十分重要的一个环节。该文集中在讨论焊膏在回流焊不同阶段中会发生些什么，产生的温度分布及其对焊接组成材料的影响等。     

选择再流焊炉的最佳方案

简要介绍再流焊接技术，介绍了选择再流焊炉必须考虑的主要因素，提出组建适用于中小批量生产的ＳＭＴ生产线再流焊炉的最佳方案。     

重视每个工艺环节 提高SMT质量

文章从多年的ＳＭＴ工艺研究与生产实践中，总结了如何从ＰＣＢ焊盘图形设计，材料及元器件选择，涂敷焊这，贴装ＳＭＤ，检验等工艺方面提高了ＳＭＴ的组装质量。     

SMT无铅再流焊工艺技术现状与探讨

再流焊是表面组装技术的重要手段，随着ROHS（the restriction of the use of certain hazardous substances in electrical and electronic equipment） 的实施，对无铅再流工艺现状的分析和探讨是有必要的。主要对双面组装的无铅工艺流程、回流焊接温度曲线的设置、粘接剂的应用等其他相关的问题进行了探讨。     

SMT焊盘设计中关键技术的分析

主要针对表面组装技术（ＳＭＴ）焊盘设计技术的原则，以及易造成失误的实质性问题开展分析，为相关设计者提供参考。     

细节距SMD的焊接技术

人们乐于采用整体再流焊技术，以焊接装有细节距器件的ＳＭＴ印制电路板。但是，对于产量较低而成本又非主要考虑的场合，采用某些局部再流焊工艺会更有效。     

国外工艺文献导读

PCB组装的热温度曲线优化 热温度曲线在PCB组装中是关键的。本文描述了在EMS供应商Axiom电子公司使用的热温度曲线硬件和工艺管理软件解决方案,满足了今天的微电子组装所面临的热温度曲线挑战要求。再流焊的挑战包括高层数电路板的热不均匀性,这些电路板具有质量分布不均匀、元件尺寸变化,含有微BGA、高球数BGA、LGA等。     

无铅焊料十温区回流焊过程的仿真研究

通过对回流焊接工艺参数传输带速度、各个炉区温度设定和焊膏熔化温度曲线的关系研究,建立了大尺寸PCB组件传热过程的数学模型。基于ANSYS平台,模拟了无铅焊料PCB组件在十温区回流焊接过程中的温度场,从而确定了合适的焊接参数。     

芯片级尺寸封装返修技术工艺评定

与传统表面安装器件（SMD）方形扁平封装（QFP）相比,芯片规模封装（CSP）及焊球阵列封装（BGA）在元件尺寸方面显著缩减。回流后在芯片下方形成焊点的位置表明,目检是不可能的。对有缺陷的芯片而言,返修的唯一方法就是除去并替换该芯片。虽然元件拆除易于完成,但替换过程也许更复杂。比较两种PCB焊盘清洗方法并从最后的焊盘抛光得出结论,在第一个工艺技术中,采用热氮气脱焊技术回流焊盘上的任何残余焊料,并通过液化真空除去。第二个技术工艺涉及到使用网状焊料芯吸法及有刀片尖的焊接烙铁来除去PCB焊盘上的残余焊料。评定的四个淀积技术工艺,包括最小型模板、浸渍传递、接触及非接触模压技术。最小型模板用于把焊膏淀积到返修的元件部位的电子制造业的传统方法。     

表面贴装生产工艺过程及分析

介绍表面贴装产品生产的工艺流程。论述了元器件入检、印制板入检、元器件选用与印制板设计之间的关系;涂覆与丝网印刷;SMD贴装;回流焊接中各个阶段温度控制等方面内容。     

表面贴装立式模块二次回流缺陷预防模型研究

立式表面贴装模块作为单板高密度布局的一种解决方案,已在业界相关产品中应用,布局在立式表面贴装模块上的表面贴装器件种类也会越来越多,这些表面贴装器件二次回流时是否会由于重力等作用产生缺陷,在业界尚未发现有相关研究。介绍了一个理论模型,该模型给出了立式模块上元器件在第二次回流是否掉件/偏位的关键值,采用试验设计(DOE)对立式表面贴装FR4模块上表面贴装陶瓷电容、SOT/SOP器件及MLF器件缺陷进行分析,对仿真模型验证回归,确定立式模块二次回流焊不发生掉件/偏位缺陷的质量面积比。     

SMT回流焊温度测试仪的设计

在表面组装技术中，炉温测试对于检测和监控回流焊质量是极其重要的，回流焊温度测试仪就是检测温度变化曲线的设备。本文设计的回流焊温度测试仪由现场单片机控制的测试系统和上位微机组成。现场单片机控制的测试系统对温度进行采集和处理，并通过串口发送给微机，由微机实现数据分析、曲线显示和打印。实验结果表明，该测试仪能够准确地测出回流焊温度。     

Numerical simulation of self-alignment of chip resistor components for different silver content during reflow soldering

Three-dimensional simulation and experimental investigation of self-alignment phenomena during the reflow soldering process were presented. The multiphase flow model was developed using ANSYS Fluent to investigate the self-alignment effect of laminar melted lead-free solder during the reflow phase on board. User-defined function with c-code was integrated into the model, Volume of Fluid (VOF) method was applied to the melt front tracking, and solidification model was used for the phase change solder material. The material used in the study was SAC 105, SAC 305 and SAC 405. The specific heat, latent heat, solidus temperature, liquidus temperature of the lead-free solder and geometrical data for model input was determined experimentally. The model was validated experimentally. The self-alignment capability of different lead-free solder was presented. It has been observed that higher silver content solder (SAC 405) have higher self-alignment capability during reflow soldering compare to SAC 305 and SAC 105. Moreover, all cases show self-alignment in perpendicular to the longer sides of chip resistor travelled more towards the central position. The experimental and simulation results are in good conformity and can be extended for different cases.     

Integrated vapor pressure, hygroswelling, and thermo-mechanical stress modeling of QFN package during reflow with interfacial fracture mechanics analysis

In this paper, a comprehensive and integrated package stress model is established for quad flat non-lead package with detailed considerations of effects of moisture diffusion, heat transfer, thermo-mechanical stress, hygro-mechanical stress and vapor pressure induced during reflow. The critical plastic materials, i.e., moldcompound and die attach are characterized for hygroswelling and moisture properties, which are not easily available from material suppliers. The moisture absorption during preconditioning at JEDEC Level 1, and moisture desorption at various high temperatures are characterized. The moisture diffusivity is a few orders higher at reflow temperature than moisture preconditioning temperature. Due to coefficient of moisture expansion mismatch among various materials, hygro-mechanical stress is induced. The concept is analogous to coefficient of thermal expansion mismatch which results in thermo-mechanical stress. Thermal diffusivity is much faster than the moisture diffusivity. During reflow, the internal package reaches uniform temperature within a few seconds. The vapor pressure can be calculated based on the local moisture concentration after preconditioning. Results show that the vapor pressure saturates much faster than the moisture diffusion, and a near uniform vapor pressure is reached in the package. The vapor pressure introduces additional strain of the same order as the thermal strain and hygrostrain to the package. Subsequently, the interfacial fracture mechanics model is applied to study the effect of crack length on die/mold compound and die/die attach delamination.     

Aluminum-germanium-copper multilevel damascene process usinglow-temperature reflow sputtering and chemical mechanical polishing

A low-temperature multilevel aluminum-germanium-copper (Al-Ge-Cu) damascene technology was developed using reflow sputtering and chemical mechanical polishing (CMP). The maximum processing temperature for the fabrication of multilevel interconnections could be reduced to 420°C using Al-1%Ge-0.5%Cu, whereas the conventional reflow temperature was not less than 500°C. No degradation due to reflow heat cycles was observed in terms of Al-Ge-Cu wiring resistance. Electromigration test results indicated that the mean time to failure (MTTF) of Al-1%Ge-0.5%Cu was longer than 10 years at the operating condition, which was equivalent to that of Al-1%Si-0.5%Cu. The Al-1%Ge-0.5%Cu triple-level interconnection was fabricated using reflow sputtering to fill vias and wiring trenches and subsequent CMP for Al-Ge-Cu films     

粉浆法制备平面荧光粉涂层白光LED的技术改进

基于粉浆法制备白光LED能得到厚度可控的荧光粉层,改善了白光LED的均匀性.由于芯片长时间工作时表面的发热以及回流焊时的瞬间高温环境,聚乙烯醇(PVA)感光胶的颜色容易发生改变,影响了白光LED光效的稳定性.本文采用等离子体去胶,实验结果表明,通过该方法能有效去除感光胶,处理后的LED不会因为长时间工作荧光粉表面涂层的...     

Rework techniques process evaluation for chip scale packages

The packaging formats, chip scale package (CSP) and ball grid array (BGA) have allowed significant reductions in component size compared to conventional surface mount devices (SMD) such as quad flat packs (QFP). However, the position of the solder joints formed (underneath the chip) after reflow means that visual inspection is impossible. For the defective chip, the only realistic method of rework is to remove and replace it. Component removal can be easily achieved, however replacement may be more complex. Difficulties in the procedure may arise from loss of terminations during the removal process, and high component population densities on printed circuit boards (PCB) may also inhibit access to the component pad site. The typical rework process consists of a number of steps including; component removal, PCB pad clean-up, flux or solder paste application, component placement and reflow. In this paper, we evaluate the pad clean up stage of the CSP rework process, including the design and analysis of a variety of solder paste or flux deposition techniques. Two PCB pad-cleaning methods have been compared and conclusions drawn from the resultant pad finish. Four deposition techniques have been assessed; these include mini-stencil, dip transfer, on- and off-contact stamping. Mini-stencil is the traditional method used in the electronics manufacturing industry for the deposition of solder paste onto reworked component sites. The remaining deposition techniques have been developed in order to overcome access restrictions that might exist on densely populated PCB's