High-swing cascode MOS current mirror

A high-swing cascode triode-region MOS current mirror, basically comprising a triode-region translinear loop, is proposed. A translinear analysis and measurement results are presented     

Low power high output impedance high bandwidth QFGMOS current mirror

Current mirror is a basic block of any mixed-signal circuit for example in an analog-to-digital converter. Its precise performance is the key requirement for analog circuits where offset is a measure issue. The key parameter which defines the performance of current mirror is its input/output impedance, input swing, and bandwidth. In this paper, a low power design of current mirror using quasi-floating gate MOS transistor is presented. The proposed current mirror boosts its output impedance in range of giga-ohm through use of regulated cascode structure followed by super-cascode. Another improvement is done in reduced input compliance voltage limits with the help of level shifter. The proposed current mirror operates well for input current range 0–700 $\mathrm{\mu }A$ with an input and output impedance of 160 $\Omega$ and 8.55 $\mathrm{G}\Omega$ respectively and high bandwidth of 4.05 $\mathrm{GHz}$. The total power consumption of the proposed current mirror is about 0.84 mW. The low power consumption with enhanced output impedance and bandwidth suits proposed current mirror for various high-speed analog designs. Performance of the presented current mirror circuit is verified using HSpice simulations on 0.18 $\mathrm{\mu }m$ mixed-mode twill-well technology at a supply voltage of ±0.5 V.     

A high output resistance current source

A current source based upon a pair of transistors in a cascode connection is discussed. The emitter-referenced cascode current source can offer as much as two orders of magnitude improvement in output resistance when compared to other current sources.     

A new low voltage level-shifted FVF current mirror with enhanced bandwidth and output resistance

This paper proposes a new high-performance level-shifted flipped voltage follower (LSFVF) based low-voltage current mirror (CM). The proposed CM utilises the low-supply voltage and low-input resistance characteristics of a flipped voltage follower (FVF) CM. In the proposed CM, level-shifting configuration is used to obtain a wide operating current range and resistive compensation technique is employed to increase the operating bandwidth. The peaking in frequency response is reduced by using an additional large MOSFET. Moreover, a very high output resistance (in GΩ range) along with low-current transfer error is achieved through super-cascode configuration for a wide current range (0–440 µA). Small signal analysis is carried out to show the improvements achieved at each step. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology. In the proposed CM, a bandwidth of 6.1799 GHz, 1% settling time of 0.719 ns, input and output resistances of 21.43 Ω and 1.14 GΩ, respectively, are obtained with a single supply voltage of 1 V. The layout of the proposed CM has been designed and post-layout simulation results have been shown. The post-layout simulation results for Monte Carlo and temperature analysis have also been included to show the reliability of the CM against the variations in process parameters and temperature changes.     

A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror

In this paper a novel ultra-high compliance, low power, very accurate and high output impedance current mirror/source is proposed. Deliberately composed elements and a good combination (for a mutual auto control action) of negative and positive feedbacks in the proposed circuit made it unique in gathering ultra-high compliances, high output impedance and high accuracy ever demanded merits. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3 and Level49 technology. Simulation results with 1 V power supply and 8 μA input current show an input and output minimum voltages of 0.058 and 0.055 V, respectively, which interestingly provide the highest yet reported compliances for current mirrors implemented by regular CMOS technology. Besides an input resistance of 13.3 Ω, an extremely high output resistance of 34.3 GΩ and −3 dB cutoff frequency of 210 MHz are achieved for the proposed circuit while it consumes only 42.5 μW and its current transfer error (at bias point) is the excellent value of 0.02%.     

Incremental output resistance of a Wilson-current mirror

The use of the 'Early' voltage parameter facilitates the derivation of simple limit expressions for the low-frequency incremental output resistance of a Wilson-current source in which the constituent bipolar devices are assumed to have characteristics that are not necessarily identical.     

Designing a very high output resistance current source for medical applications

A new technique is proposed for the design of a current source, in bipolar technology, with a very high output resistance and low output capacitance. Such a technique is useful in electrical impedance tomography applications. The DC relationships of the basic topology are established. Then, based on the analysis of a simplified equivalent circuit, an expression is formulated for the output resistance and tested against simulation results for both ideal and practical biasing circuits. The effect of circuit capacitances, and in particular, the role of the collector-base capacitance of the output transistor, in determining the output impedance as a function of frequency is considered. Finally, a new circuit is shown to have an incremental output resistance exceeding 200?GΩ.     

Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements

This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output stage to achieve low input resistance and very high output resistance. It can be used as a high-precision current mirror in analog and mixed signal circuits with a power supply close to a transistor's threshold voltage. The proposed current mirror has been simulated and a bandwidth of 40 MHz has been obtained. An experimental chip prototype has been sent for fabrication and has been experimentally verified, obtaining 0.15-V input-output voltage requirements, 100-/spl Omega/ input resistance, and more than 200-M/spl Omega/ (G/spl Omega/ ideally) output resistance with a 1.2-V supply in a standard CMOS technology.     

Degradation of MOS tunnel structures at high current density

The stability of tunneling-thin (2–3 nm) SiO₂ films during prolonged flow of high-density currents (10²–10³ A/cm²) was investigated. A sharp increase in the charge which a tunneling MOS structure is capable of transmitting without degradation on switching from Fowler-Nordheim injection to direct tunneling (10³ C/cm² and 10⁷ C/cm², respectively) was observed. The degradation of SiO₂ films was investigated using Al/SiO₂/n-Si/p ⁺-Si thyristor structures with a positive bias on the semiconductor, i.e., with reverse bias of the MOS structure. The use of these devices accounted for the uniformity of the current distribution over the area and made it possible to monitor the state of the insulator layer by measuring the device gain in the phototransistor mode. Fiz. Tekh. Poluprovodn. 32, 743–747 (June 1998)     

高电压输入大电流输出恒流源

为了提高现有路灯的供电效率,开发设计了单灯恒流的供电模式,在每个路灯上安装一个体积很小的的恒流源,以保障给LED灯提供稳定、高效的恒流供电.在恒流源模块中,恒流源芯片HV9910B可以实现了高于70 V的电压的输入,在不同的输入电压下,恒流源芯片工作在恒定关断模式下,控制输出BUCK电路中的开关MOSE的占空比,以输出恒定2.2 A的电流,LED灯串联起来作为负载,效率达到了91％以上.     

A very high performance compact CMOS current mirror

This paper proposes a very high performance current mirror (CM), where output current accurately copies the input current without carrying any offset component. Compact implementation of Garimella et al. CM structure has been combined with super cascode configuration to achieve the proposed very high performance CM. The proposed CM offers extremely high output resistance, very low input resistance and high degree of copying accuracy over a wide operating current range. Small signal analysis is carried out to validate the performance characteristics of the circuit. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology, using a single supply voltage of 1.5 V. The circuit is shown to have high current copying accuracy for a range of (0–500 µA) with an error less than 0.0016 % and has no offset current at the output side. The robustness of the proposed CM against the variations in device parameters and temperature changes has been reflected in simulations by carrying Monte Carlo and temperature analysis. The simulation results show that the proposed circuit provides very high output resistance of 55.76 GΩ and a very low input resistance of 0.07 Ω.     

MOS cascode-mirror biasing circuit operating at any current levelwith minimal output saturation voltage

A cascode biasing circuit is proposed which fixes the source voltage of the cascode transistor equal to the saturation voltage of the mirror transistor. The mirror can operate at any current level from weak to strong inversion. The design is based on ratios, and is technology-independent. Since the circuit ensures the smallest possible output saturation voltage, it has potential applications in all fields of low-voltage micropower design     

Low-voltage high performance compact all cascode CMOS current mirror

A high performance and compact current mirror with extremely low input and high output resistances (R/sub in//spl sim/0.01/spl Omega/, R/sub out//spl sim/10 G/spl Omega/), high copying accuracy, very low input and output voltage requirements (V/sub in/, V/sub out//spl ges/V/sub DSsat/), high bandwidth (200 MHz using a 0.5 /spl mu/m CMOS technology) and low settling time (25 ns) is proposed. Simulations and experimental results are shown that validate the circuit.     

A high current drive CMOS output stage with a tunable quiescent current limiting circuit

A CMOS output stage based on a complementary common source with an original quiescent current limiting circuit is presented. The quiescent current can be varied over a wide range by means of a control current with no need to modify the transistor aspect ratios. The output stage has been coupled to a conventional complementary input stage to form a rail-to-rail buffer. A prototype with the inclusion of auxiliary pins for biasing and current monitoring purposes has been designed using the 1-/spl mu/m double-polysilicon BCD3S process of STMicroelectronics. On a single 5-V power supply, the maximum output current is 20 mA. The amplifier, biased for a total power dissipation of 1 mW, exhibits a total harmonic distortion of -58 dB at 1 kHz with 4-V peak-to-peak on a 330-/spl Omega/ load. Correct operation of the quiescent current limiting circuit has been demonstrated for a minimum supply voltage of 2.2 V.     

高频下保持高输出阻抗的双极电流源

基于仪器和运算放大器的传统电流源和电压/电流转换器在低频下提供很高的输出阻抗,这是因为放大器具有良好的低频CMRR(共模抑制比)。在较高频率下,降低的CMRR、固有的输出电容、转换率的局限性阻止了高质量电流源的实现。     

Flexible air-stable three-dimensional polymer field-effect transistors with high output current density

Flexible air-stable short-channel polymer organic field-effect transistor (OFET) arrays with high saturated output current density are demonstrated by utilizing a novel solution-processed naphthobisthiadiazole (NTz) based donor–acceptor semiconducting polymer (PNTz4T) and designing a three-dimensional vertical channel structure with an extremely large ratio of channel width to channel length. The saturated mean field-effect mobility of 0.16 cm²/V s of the short-channel polymer devices remains over one month resulting in air-stable OFET arrays with high on/off ratio over 10⁶ and powerful current–density exceeding 0.3 A/cm² under low operation voltage, both of which meet the requirements for such applications as driving organic light-emitting diodes in active-matrix displays.     

A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate–source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18 μm CMOS technology parameters. Under supply voltage of ±0.7 V and bias current of 5 μA, it can deliver output currents as high as 14 mA with THD better than ?53 dB and extremely high output impedance of 320 MΩ while consuming only 29 μW. This makes the proposed COS to have ultra large current drive ratio (I_outmax/I_bias or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to ±0.9 V, it can deliver extremely large output current of ±24 mA corresponding to 3200 current drive ratio while consuming only 42.9 μW and exhibiting high output impedance of 350 MΩ. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than ?45 dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only ±3.29 mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR?) of 125 dB and 130 dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.     

A very high performance self-biased cascode current mirror for CMOS technology

This paper presents a novel high performance self-biased cascode current mirror (CM) for CMOS technology. The proposed circuit shows a resistance compensated high bandwidth CM operating at low voltages. This circuit uses super cascode configuration to obtain high output impedance required for high performance of CM. Active implementation of passive resistances of the proposed circuit is shown. The simulations of proposed CM are carried out by Mentor Graphics Eldospice based on TSMC 0.18 μm CMOS technology, for input current range of 0–500 μA. A bandwidth of 2.26 GHz, input and output resistances of 679 Ω and 482 MΩ respectively, are obtained with a single supply voltage of ?1 V.     

A Schmitt trigger with current mirror feedback

The circuit of a simple trigger with positive feedback via the current mirror (with gain) and the resistive divider is proposed. The circuit operation is described and the hysteresis voltage is obtained. The basic design limitations are introduced. Both versions (CMOS and bipolar) are considered.