The role of electron traps on the post-stress interface trapgeneration in hot-carrier stressed p-MOSFETs

The generation of interface traps in p-MOSFETs subjected to hot-electron injection is found to proceed even after the stress has been terminated. The extent of post-stress interface trap generation is strongly dependent on the magnitude of the preceding hot-electron stress, as well as the magnitude and polarity of the gate voltage during relaxation. Trap generation is enhanced for negative gate voltage anneal, but suppressed for positive gate voltage anneal. For a given stress-induced damage, the corresponding trap generation kinetics can be completely described by a single characteristic, which is shifted in time according to the magnitude of the applied gate voltage. Existing interface trap generation models are discussed in the light of the experimental results. A new model involving the tunneling of holes from the inversion layer to deep-level electron traps is proposed. Similar post-stress effect observed for hot-electron stressed n-MOSFETs provides additional support for the model. Our work suggests that near-interface electron traps, apart from the well-known hole traps, may also significantly affect the long-term stability of the Si-SiO₂ interface     

超薄栅MOS器件热载流子应力下SILC的产生机制

通过测量界面陷阱的产生,研究了超薄栅nMOS和pMOS器件在热载流子应力下的应力感应漏电流(SILC).在实验结果的基础上,发现对于不同器件类型(n沟和p沟)、不同沟道长度(1、0.5、0.275和0.135μm)、不同栅氧化层厚度(4和2.5nm),热载流子应力后的SILC产生和界面陷阱产生之间均存在线性关系.这些实验证据表明MOS器件减薄后,SILC的产生与界面陷阱关系非常密切.     

A study of hot carrier degradation in NMOSEET's by gate capacitanceand charge pumping current

Hot carrier degradation in n-channel MOSFET's is studied using gate capacitance and charge pumping current for three gate stress voltages: V_g~V_b, V_d/2, V_d. The application of these two sensitive techniques reveals new information on the types of trap charges and the modes of degradation. At low V_g stress near threshold voltage, the fixed charge is attributed to holes. For high V_g stress, the fixed charge is predominantly electrons. Data for mid V_g stress suggest little net fixed charge trapping. Interface traps are observed for all stress conditions and are demonstrated from differential gate capacitance spectra to exhibit both donor and acceptor trap behavior. Mid V_g stress is shown to result in the highest density of interface traps. These traps can be annealed to a large extent for temperatures up to 300°C. A post-stress generation of interface traps is observed at low V_g stress, in agreement with recent observation. Further, a linear relation is found to exist between the change in overlap gate capacitance and the increase in peak charge pumping current, and suggests spatial uniformity in the degradation of the interface     

新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs

The effects of intermittent low-bias annealing on NBT stress-induced threshold voltage shifts in p-channel VDMOSFETs are analysed in terms of mechanisms responsible for underlying changes in the densities of gate oxide-trapped charge and interface traps. Negative bias annealing after an initial NBT stress appears to freeze the initial degradation. Alternatively, either positive or zero bias removes the portion of stress-generated oxide-trapped charge and creates new reversible component of interface traps, while each repeated NBT stress regenerates the oxide-trapped charge and removes the reversible component of interface traps. The post-stress generation of interface traps under positive oxide field is ascribed to the processes at SiO₂/Si interface arising from the reversed drift direction of positively charged species, which are not likely to occur under negative gate bias. Despite all these phenomena, intermittent annealing does not seem to affect the device lifetime.     

A study of interface trap generation by Fowler-Nordheim andsubstrate-hot-carrier stresses for 4-nm thick gate oxides

The generation of interface traps by different stresses to 4-nm thick SiO₂ gate oxide is studied. Four different kinds of constant current stresses were applied. The interface-trap density (D _it) generation due to hot holes under V_G<0 Fowler-Nordheim (FN) stress was characterized using quantum-yield measurement and substrate-hot-hole (SHH) stress. The interface-trap density (D_it) generated by SHH stress increases as gate-oxide field increases. Substrate-hot-electron (SHE) stress generates much less interface-trap density (D_it) than SHH stress. It is also observed that N₂O-grown gate-oxide has smaller hole-injection probability but larger electron-injection probability than O₂-grown oxide. N₂O-grown gate oxide is shown to have less SHH stress-induced interface traps than O₂-grown oxide in p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) devices     

HfO_2高k栅介质漏电流机制和SILC效应

利用室温下反应磁控溅射的方法在 p- Si(1 0 0 )衬底上制备了 Hf O2 栅介质层 ,研究了 Hf O2 高 k栅介质的电流传输机制和应力引起泄漏电流 (SIL C)效应 .对 Hf O2 栅介质泄漏电流输运机制的分析表明 ,在电子由衬底注入的情况下 ,泄漏电流主要由 Schottky发射机制引起 ,而在电子由栅注入的情况下 ,泄漏电流由 Schottky发射和 Frenkel-Poole发射两种机制共同引起 .通过对 SIL C的分析 ,在没有加应力前 Hf O2 / Si界面层存在较少的界面陷阱 ,而加上负的栅压应力后在界面处会产生新的界面陷阱 ,随着新产生界面陷阱的增多 ,这时在衬底注入的情况下 ,电流传     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

Analysis of the DCIV peaks in electrically stressed pMOSFETs

This paper presents the effects of Fowler-Nordheim (FN) and hot-carrier (HC) stress in the direct-current current voltage (DCIV) measurements. The effect of interface trapped charge on DCIV curves is reported. Stress-induced oxide charge shifts the DCIV peaks, while stress-induced interface trapped charge causes a spread in the DCIV peaks. It is found that under HC stress, when the absolute value of stress gate voltage changes from low to high, the interface trap spatial location moves from the drain region to the channel region. It is inferred that the generation of oxide charge in the drain region is a two-step process. For short stress times, electrons mainly fill the process-induced neutral oxide traps, while for long stress times, electrons fill the stress created electron traps     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with direct-tunneling SiON gate dielectrics was studied in detail. By investigating the effects of applying positive gate bias on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBTI was clearly demonstrated. In particular, it was found that a positive charge generated by negative bias temperature stress (NBT stress) can be neutralized and that the neutralized site can return to the positive state. We consider that the bulk trap is due to hydrogen atoms released from the interface between the SiON gate dielectric and the Si substrate (and this is what has conventionally been considered a positive fixed charge). Moreover, the bulk trap generation was shown to give rise to stress-induced leakage current.     

Studies of the quality of GdSiO-Si interface

In this paper nMOS transistors with GdSiO gate dielectric are studied using electrical methods (C-V, I-V and charge pumping) in order to assess the quality of the dielectric-semiconductor interface. Mobility is estimated using the split C-V technique and the influence of voltage stress on interface trap generation and charge build-up in the oxide is investigated. Generation of additional interface traps is observed during negative voltage stress only, which may be attributed to hole tunneling from the semiconductor to electron traps. Multi-frequency charge pumping measurements reveal the presence of border traps.     

The relationship between gate bias and hot-carrier-inducedinstabilities in buried- and surface-channel PMOSFETs

For accurate predictions of device reliability with respect to hot-carrier effects, it is necessary to establish worst-case stress bias conditions. Detailed measurements of hot-carrier-induced instabilities in short-channel PMOSFETs have revealed that stress gate bias conditions corresponding to peak gate currents result in maximum shifts in device parameters. However, for some parameters, notably those measured at low drain bias, comparable shifts are observed for stress gate bias conditions that correspond to peak substrate currents. These observations are valid for both buried-channel (n-type polysilicon gate) and surface-channel (p-type polysilicon gate) PMOSFETs. An interpretation of these results based on the generation of tapped oxide charge and interface traps is proposed     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%     

Analysis of hot-carrier-induced aging from 1/f noise in short-channel MOSFET's

The 1/f noise of short-channel n-type MOSFET's is measured in the weak inversion regime before and after an electrical stress. The noise increase which follows the aging is shown to be due to an electrically induced generation of traps in the gate oxide rather than fast interface states. Noise experiments prove that the degradation occurs in a narrow region (less than 50 nm) near the drain. Created traps also appear to have an inhomogeneous energy profile.     

The process dependence on positive bias temperature aginginstability of p+(B) polysilicon-gate MOS devices

During positive bias temperature (BT) aging, a large number of interface traps on p⁺(B) polysilicon MOS devices are generated in the upper half of the bandgap without an increase in the charges trapped in the gate oxide. The increase in interface traps can be reduced by processes which exclude the hydrogen included during fabrication. The increase in the interface-state density is explained as follows. The generation of the interface traps is caused by hydrogen ions reaching at the SiO₂/Si interface through the gate oxide from the polysilicon-gate electrode. The hydrogen ions combine with activated boron and are released from the boron under positive BT aging. The increase in interface traps is formulated by equations which are derived from the above model     

Characterization of oxide trap and interface trap creation duringhot-carrier stressing of n-MOS transistors using the floating-gatetechnique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I_g-V_g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I_g- V_g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I_g-V _g measurements     

Insights on trap generation and breakdown in ultra thin SiO2 and SiON dielectrics from low voltage stress-induced leakage current measurements

We review the advancements in the understanding of breakdown and trap generation that have been achieved using low voltage stress-induced leakage current as a probe of the interface states created during electrical stress of ultra thin SiO₂ and SiON gate dielectrics. The technique separates the effects of bulk and interface states on the post-stress I–V characteristics; senses interface traps at both contact interfaces, identifies the regime where interface rather than bulk state generation is the rate limiting step for breakdown, is useful for determining the operative trap creation processes, and reveals the role of trap generation mechanism in driving which stress-induced defect controls breakdown.     

Trapped charge distributions in thin (10 nm) SiO2 filmssubjected to static and dynamic stresses

Thin (10 nm) gate oxide MOS capacitors have been subjected to static and dynamic stress conditions. The evolution of the trapped charge distributions (characterized by average density and centroid) has been measured as a function of the stress time. The evolution of the average charge density for DC stresses shows that both polarities have identical trap generation rates and a constant average density of traps at breakdown. However, the final density of traps is much smaller for injection from the gate, so that the time-to-breakdown is also much shorter for this stress polarity. The evolution of the centroid shows that traps are always mainly generated near the cathodic interface. Unipolar dynamic stresses give results which are qualitatively very similar to those obtained under DC conditions and without a relevant frequency dependence. In contrast, bipolar stress experiments show significant qualitative differences, the frequency dependence being very important. In general, the trap generation and trapping rates are reduced in comparison to the DC and unipolar cases, this reduction being more important at high frequencies. In addition, the average density of trapped electrons at the breakdown is larger than that obtained in DC experiments. Both observations explain the tremendous increase in the mean-time-to-breakdown obtained under high-frequency stress conditions. The presented results are qualitatively explained in terms of microscopic degradation models     

Linear cofactor difference method of MOSFET subthresholdcharacteristics for extracting interface traps induced by gate oxidestress test

A new subthreshold analysis technique, the linear cofactor difference method, is presented in this brief for extraction of the MOSFET interface traps induced by the gate oxide stress test. This technique relies on new linear cofactor difference extreme spectral characteristics of MOSFET gate voltage in the subthreshold region. It is shown that this method enables reliable extraction of the increased interface traps with a rise of the accumulated gate oxide stress test time to be obtained and that its validity is also verified by the extraction experiments on an n-channel MOSFET (nMOST) device