A new type of transistor: CBT

A transistor called the channel-base transistor (CBT), which is constructed by making channels through the base of the conventional bipolar junction transistors (BJTs), is proposed. In principle, a CBT can be treated as a combination of a BJT and a normally-off junction-type field-effect transistor (E-JFET). Silicon planer CBTs have been fabricated with BJTs on the same wafer for comparison. The electrical characteristics of CBTs are similar to those of a conventional BJTs, but the variations of current gain with temperature and emitter current in CBTs are much less than those in the BJTs. In addition, the magnitude of current gain of CBTs is higher than that of comparable BJTs. Transistor-transistor-logic (TTL) NAND-gate ICs implemented with CBTs have been fabricated. The temperature variations of parameters in CBT ICs are less than those in BJT ICs. Experiments have shown that silicon CBT discrete devices and ICs can be used over a wide range of temperatures from -60°C to 200°C. Experimental and theoretical analysis results for CBTs are presented     

A compact efficient Schottky collector transistor switch

A vertical Schottky collector transistor switch with merged vertical n-p-n load is described which is useful in both memory and logic applications. The device has been fabricated in an infant oxide isolated bipolar technology with Schottky collector area of 3.8 /spl mu/m/spl times/5.0 /spl mu/m (0.15 mil/spl times/0.2 mil). The intrinsic n-p-n load transistor directly below the Schottky collector requires no additional surface area. Contact location to extrinsic device regions is not restricted, providing wiring flexibility. Current gains of 3 and 4 have been obtained for prototype Schottky collector and n-p-n transistors, respectively. A power-delay product of 60 fJ/V has been observed on a 25-state (fan-out=1) closed-loop inverter chain using 5 /spl mu/m metal lines and spaces. A 5.0 ns delay at 15 /spl mu/A/stage (power-delay product=75 fJ/V) reveals potential for fast, low power VLSI application. The intrinsic speed limit of 2.76 ms is attained at 60 /spl mu/A/stage.     

Modeling of Schottky coupled transistor logic

The SCTL gate which promises increased speed and reduced power is discussed. It involves the use of a single lowly doped collector incorporating Schottky diodes to decode the output. A complete electrical model is formulated and compared with experimental results. The model is then used to optimize this structure with respect to extrinsic and intrinsic base doping and collector doping, and it resulted in an 8.5 ns fanout four device on a 2.5 /spl mu/m epilayer. Finally, the model is used to study the possibility of Schottky clamping the base collector, and it was found that higher collector doping was needed for a minimum delay.     

Hybrid Schottky injection MOS-gated power transistor

A modified Schottky injection field effect transistor (SINFET) which offers lower on-resistance and a switching speed comparable to conventional n-channel LDMOSTs is described. The fabrication process is similar to that of an LDMOS transistor but with the high-low (n+n-) `ohmic? contact at the drain replaced by a parallel combination of a Schottky barrier and a pn junction diode. This hybrid anode injects minority carriers into the n- drift region, which in turn provides conductivity modulation. A current handling capability 3.5 times larger than that of the LDMOST is achieved. With the minority carrier injection level limited by the Schottky barrier, the total amount of minority carriers injected by the hybrid anode is much lower than that injected by the pn junction diode alone. Thus, the device speed is comparable to the conventional n-channel LDMOST. By minimising the shunting resistance in the p-channel region, devices with a latch-up current density of 400 A/cm2 are obtained.     

The SINFET—A Schottky injection MOS-gated power transistor

A new MOS-gated power device, the Schottky injection FET (SINFET), is described in this paper. The device offers 6 times higher current handling capability than conventional n-channel power LDMOS transistors of comparable size and voltage capability and still maintains a comparable switching speed. The low on-resistance is obtained by conductivity modulation of the high-resistivity n- drift region using a Schottky injector. Since only a small number of minority carriers are injected, the speed of the device is not degraded substantially and high latchup resistance is achieved. Breakdown voltages and specific on-resistance observed on typical devices are 170 V and 0.01 Ω . cm², respectively. Gate-turn off times are of the order of 30 ns. Two-dimensional simulation and experimental results comparing the SIN-FET with the LDMOST and lateral insulated gate transistor (LIGT) are presented.     

A new high breakdown voltage lateral Schottky collector bipolar transistor on SOI: design and analysis

Using two-dimensional process and device simulation, we present for the first time, a new high breakdown voltage two-zone base extended buried oxide (BOX) lateral Schottky Collector Bipolar Transistor (SCBT) on silicon-on-insulator with a breakdown voltage as high as 12 times that of the conventional lateral Schottky collector bipolar transistor. We have explained the new design features of the proposed Schottky collector structure and the reasons for its significantly improved breakdown performance. The proposed structure is expected to be suitable in the design of the new generation scaled high voltage Schottky collector bipolar transistors for low power high speed analog applications.     

Lateral MIS tunnel transistor

A new device structure called the Lateral MIS Tunnel Transistor (LMISTT) is proposed, and its basic features and characteristics are presented. In this device, effects related to the lateral conduction in MIS tunnel structures are implemented. The device is featured by very simple processing, and shows promise in a variety of applications, including very large scale integration high speed IC's.     

Vertical tunnel field-effect transistor

The realization of a novel vertically grown tunnel field-effect transistor (FET) with several interesting properties is presented. The operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations. This device consists of a MBE-grown, vertical p-i-n structure. A vertical gate controls the band-to-band tunneling width, and hence the tunneling current. Both n-channel and p-channel current behavior is observed. A perfect saturation in drain current-voltage (I/sub D/--V/sub DS/) characteristics in the reverse-biased condition for n-channel, an exponential and nearly temperature independent drain current-gate voltage (I/sub D/--V/sub GS/) relation for both subthreshold, as well as on-region, and source-drain off-currents several orders of magnitude lower then the conventional MOSFET are achieved. In the forward-biased condition, the device shows normal p-i-n diode characteristics.     

A new lateral PNM Schottky collector bipolar transistor (SCBT) onSOI for nonsaturating VLSI logic design

The novel characteristics of a new lateral PNM Schottky collector bipolar transistor (SCBT) on silicon-on-insulator (SOI) are explored using two-dimensional (2D) simulation. The collector-base junction of the proposed lateral PNM transistor consists of a Schottky junction between n-base (N) and metal (M). The characteristics of this structure are compared with that of lateral PNP transistors on SOI. We demonstrate that the proposed structure has a superior performance in terms of reduced collector resistance, high current gain, negligible base widening, and very low reverse recovery time compared to the compatible lateral PNP transistors. A simple fabrication procedure is also suggested providing the incentive for experimental verification     

A high-conductivity insulated gate bipolar transistor with Schottky hole barrier contact

This letter proposes a high-conductivity insulated gate bipolar transistor (HC-IGBT) with Schottky contact formed on the p-base, which forms a hole barrier at the p-base side to enhance the conductivity modulation effect. TCAD simulation shows that the HC-IGBT provides a current density increase by 53% and turn-off losses decrease by 27% when compared to a conventional field-stop IGBT (FS-IGBT). Hence, the proposed IGBT exhibits superior electrical performance for high-efficiency power electronic systems.     

A new hybrid VDMOS-LIGBT transistor

A p-channel vertical DMOSFET structure coupled with a lateral IGBT (insulated-gate bipolar transistors) path is described. External resistors are placed in series with either the collector terminal (the bipolar-enhanced MOSFET (BIENFET) mode) or the drain terminal (the substrate collector-shorted (SCOSH) LIGBT mode) to vary the degree of minority-carrier injection. This creates the opportunity to obtain a device with externally programmable forward-drop/switching speed tradeoff. The device is shown experimentally to have forward drops close to those of vertical and lateral IGBTs and turn-off times close to that of MOSFETs. Typical forward drops at 93 A/cm² range from 3-4 V and corresponding turn-off times from 4.3 to 0.22 μs when the drain resistor is varied. This device is considered particularly attractive as a high-frequency and high-voltage power switch     

A new higher ambient transistor

Interest in high speed transistor switching circuits whose operation is unaffected by large changes in ambient temperature led to an investigation of silicon-germanium alloy point-contact transistors because of the larger forbidden energy gap of silicon-germanium alloys. In germanium transistors, as far as temperature stability is concerned, Ic0is particularly poor. Ic0is the value of collector current, at a given collector voltage, with no emitter current. The Ic0of germanium units tested rose rather linearly from 20°C. to about 65°C., with a gradient of 25 µa/°C. but then entered a region of run away. A number of point-contact transistors have been manufactured using 3 per cent silion-germanium (10 ohm-cm, n-type), and the parameters r11, r12, r22, α, fc0and Ic0at room temperature, and values of Ic0as a function of temperature have been measured. Results show that 3 per cent silicon-germanium transistors are as good as germanium transistors in all respects and better in temperature stability. The values of Ic0for silicon-germanium transistors rose linearly from 18° to about 95°C., with a gradient comparable to that of the germanium units below 65°C.     

A 2-D Semi-Analytical Model of Double-Gate Tunnel Field-Effect Transistor Xu Huifang (许会芳), Dai Yuehua*(代月花), Li Ning(李宁), Xu JianBin(徐建斌)

文中提出了一种双栅隧穿场效应晶体管(DG TFET)的二维半解析模型。通过在栅绝缘层和沟道区引入两个矩形源,运用半解析法和特征函数展开法求解二维泊松方程,得到电势的二维半解析解。解的结果是一个特殊函数,为无穷级数表达式。基于电势模型,求出最短隧穿长度( )和平均电场( ),运用Kane模型得到漏极电流。新模型考虑了移动电荷对电势的影响以及漏源电压对隧穿参数 和 的影响。文中计算了不同漏源电压,不同硅膜厚度,栅介质层厚度和栅介质层常数下的表面势和漏极电流。结果表明,新模型与仿真结果吻合。这将有助于DG TFET的优化设计,同时,也加深了DG TFET器件对电路结构设计的规划。     

A new complementary monolithic transistor structure

A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process a pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure.     

A new trench base-shielded bipolar transistor

In this paper, a new power bipolar transistor structure called the trench base-shielded bipolar transistor (TBSBT) Is proposed and experimentally demonstrated. This structure incorporates deep p⁺ poly-Si trenches into the base of a conventional bipolar transistor. With the base shielded effectively by the p⁺ trenches, the base of the TBSBT can be made very narrow to achieve high current gain h_FE and high cut-off frequency f_T without compromising on the breakdown voltage. Experimental results show that the on-state anti switching characteristics of the TBSBT are significantly better than those of the existing power bipolar transistors     

A new bottom-gated poly-Si thin-film transistor

We have proposed and fabricated the new bottom-gated poly-Si TFT with a partial amorphous-Si (a-Si) region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the reverse leakage currents are decreased significantly in the new poly-Si TFT compared with conventional one. This reduction is due to the suppression of field emission currents by local a-Si region like that of a-Si TFTs while the ON currents are kept almost the same due to the considerable inducement of electron carriers in the short a-Si channel by the positive gate bias     

A new complementary bipolar transistor structure

A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process, a complementary pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure. Novel low-voltage (1.3 V) complementary digital circuits have been fabricated by this new process.     

Parasitic SCR between a Schottky diode and an adjacent transistor

A Schottky diode and an adjacent transistor in integrated circuits may show parasitic silicon controlled rectifier (SCR) latching. This parasitic effect must be taken into account by circuit designers. If the SCR latches, an undesirable electrical short is formed between the Schottky diode and the emitter of the transistor. In this paper the conditions are investigated under which the parasitic SCR can switch. Experimental data are presented which show the validity of the theoretical considerations. Recommendations are given on how to suppress parasitic SCR latching.     

A lateral metal—insulator—p-Si tunnel transistor

We report the fabrication of a lateral MIS tunnel transistor whose emitter and collector are Al/SiO2/p-Si tunnel junctions. All processing is carried out at room temperature except for the growth of the passivating field oxide. The small signal common emitter current gain is 20. Two coupled gain mechanisms exist for such a lateral MIS tunnel transistor. The first mechanism relies on a high minority-carrier injection ratio of the emitter junction. Second, the minority carriers injected into the reverse-biased collector junction may produce additional gain through multiplication of majority-carrier current. Lateral MIS tunnel transistors on n-Si make use of the second mechanism. Our device takes advantage of the high minority-carrier injection ratio achievable with Al/SiO2/p-Si tunnel junctions.     

A new five-parameter MOS transistor mismatch model

A new five-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation regions, including short-channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch Δ&thetas; into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short-channel transistors