Fabrication and optical-switching results on the integrated light-triggered and quenched static induction thyristor

An integrated structure of the light-triggered and light-quenched (LTQ) static induction (SI) thyristor is introduced and is fabricated by the combination of the SI thyristor and SI transistor process technology. The device consists of a buried-gate light triggered (LT) SI thyristor and a p,channel surface gate static induction photo-transistor (SIPT). An anode voltage VAKof 500 V at an anode current IAKof 1 A (600 A/cm²: channel current density) is optically switched with a triggering power ofP_{LT} = 11mW/cm²(92 µW) and a quenching power ofP_{LQ} = 11mW/cm²(110 µW) in a turn-on time of 0.7 µs and a turnoff delay time of 1.0 µs. The integrated LTQ SI thyristor is a novel type of self-turn-off power device that is turned on and off by optical means.     

Fabrication and characterization of fin SONOS flash memory with separated double-gate structure

In this work, we have fabricated and characterized the 3-dimensional fin SONOS flash memory. This device has two independent gates on both sides of Si-fin and each of them governs two side-channels. Fabrication flow and array structure are described as well as operation schemes. The 4-bit/cell operation is demonstrated with the multi-bit concept in fabricated devices. Some fabrication issues related with device characteristics and reliabilities are delivered.     

Fabrication and characterization of field-plated buried-gate SiC MESFETs

Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the "buried-channel" and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-/spl mu/m gate periphery SiC MESFET. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz /spl plusmn/ 100 kHz indicate an optimum FP length for high linearity operation.     

Fabrication and field emission characteristics of a novel planar-gate electron source with patterned carbon nanotubes for backlight units

This paper describes the fabrication of backlight units(BLUs) for a liquid crystal display(LCD) based on a novel planar-gate electron source with patterned carbon nanotubes(CNTs) formed by electrophoretic deposition. The electric field distributions and electron trajectories of this triode structure are simulated according to Ansys software.The device structure is optimized by supporting numerical simulation.The field emission results show that the emission current depends strongly on the cathode-gate gap and the gate voltage.Direct observation of the luminous images on a phosphor screen reveals that the electron beams undergo a noticeable expansion along the lateral direction with increasing gate voltage,which is in good agreement with the simulation results.The luminous efficiency and luminance of the fabricated device reaches 49.1 lm/W and 5500 cd/m2,respectively.All results indicate that the novel planar-gate electron source with patterned CNTs may lead to practical applications for an electron source based on a flat lamp for BLUs in LCD.     

A high-voltage light-activated thyristor with a novel over-voltageself-protection structure

A high-voltage self-protected thyristor with a well structure formed in its p-base layer whose operation is based on avalanche breakdown is described. The device structure is simple and easy to fabricate compared to other avalanche-type devices. Numerical analyses and experiments demonstrate that the breakover voltage can be controlled by varying the well diameter and/or its depth. The breakdown voltage fluctuation of the device is 10% when the junction temperature is varied from 23 to 100°C. The device is turned on safely at 7300 V     

An overvoltage self-protected thyristor with a structure to predictbreakover voltage

A new concept for an overvoltage self-protected thyristor was theoretically analyzed and the thyristor manufactured. Its breakover operation is basically a combination of punchthrough and avalanche phenomena. Temperature dependence of the original structure in this thyristor is 5% from 20 to 125°C. A second device which has a function to predict breakover voltage was also produced. The difference in temperature dependence of breakover voltage for both devices was investigated by an analytical model. Structures offering improved characteristics were proposed. The breakover voltage decrease of the developed structures at high temperature could be made equal to that of the original structure by a slight modification of the breakover region     

A new MOS-gated power thyristor structure with turn-off achieved bycontrolling the base resistance

A new MOS-gated power thyristor structure, called the base-resistance-controlled thyristor (BRT), is described. In this structure, the turn-off of a thyristor with an N-drift region is achieved by reducing the resistance of the P-base region under MOS-gate control. In contrast with previous devices, a P-channel MOSFET integrated in the N-drift region is used for this purpose. It has been shown, by two-dimensional numerical simulations and experimental measurements on devices fabricated using a seven-mask process, that devices with 600-V forward blocking capabilities can be achieved with a forward drop close to that for a thyristor. The ability to turn off the thyristor current flow has been verified over a broad range of current densities     

双材料嵌套全抗反射膜的设计

从非均匀介质出发,首先从理论上设计了一种适用于整个可见光与0-80°入射角范围的多层全抗反射膜;然后根据有效介质理论,结合实际提出了用嵌套结构来代替每层薄膜的思想,并利用优化算法改进和提高了这种嵌套结构全抗反射膜的有效性。     

Enhancement of charge storage performance in double-gate silicon nanocrystal memories with ultrathin body structure

We propose double-gate silicon nanocrystal memories (NCMs) with ultrathin body structure. Double-gate NCMs experimentally show larger threshold voltage shift (/spl Delta/V/sub th/) and longer charge retention time than single-gate NCMs. These superior behaviors in double-gate NCMs are explained by the increase in the body potential due to electrons in one side nanocrystals that prevent electrons in the other side nanocrystals from escaping. Thinner transistor body enhances the mutual influence between electrons in both sides. It is also found that the endurance characteristics are also improved by the reduced potential difference in the tunnel oxide.     

Design aspects of MOS-controlled thyristor elements: technology,simulation, and experimental results

2.5-kV thyristor devices have been fabricated with integrated MOS controlled n⁺-emitter shorts and a bipolar turn-on gate using a p-channel DMOS technology. Square-cell geometries with pitch variations ranging from 15 to 30 μm were implemented in one- and two-dimensional arrays with up to 20000 units. The impact of the cell pitch on the turn-off performance and the on-state voltage was studied for arrays with constant cathode area as well as for single-cell structures. By realizing MOS components with submicrometer channel lengths, scaled single cells are shown to turn off with current densities of several kiloamperes per square centimeter at a gate bias of 5 V. In the case of multi-cell ensembles, turn-off performance is limited due to inhomogeneous current distribution. Critical process parameters as well as the device behavior were optimized through multidimensional numerical simulation     

具有侧面柱状结构的高压LED芯片制备

设计制作了一种具有侧面柱状结构的高压发光二极 管(HV-LED)芯片,与未作侧面柱状结构的HV-LED芯片相比, 在正向电流20mA下,其光功率提高了7.6%,而正向电压和波长基 本维持不变。对这两种HV-LED 芯片的电流和电压以及电流和光功率的关系进行研究。封装白光后的测试结果表明,在色温 4500K、 驱动 电流20mA下, 具有侧面柱状结构的HV-LED芯片光效达 125. 6lm/W。在标准测试温度为20℃、正向电流为20mA驱动下,具有侧面柱状结构的HV-LED芯片封装老化测试1000h后,光衰仅为2%。     

A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure

This paper presents a compact two-dimensional analytical device model of surface potential, in addition to electric field of triple-material double-gate (TMDG) tunnel FET. The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source. The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage, lateral and vertical electric field. Because the TMDG TFET has a simple compact structure, the surface potential is computationally efficient and, therefore, may be utilized to analyze and characterize the gate-controlled devices. Furthermore, using Kane's model, the current across the drain can be modeled. The graph results achieved from this device model are close to the data collected from the technology computer aided design (TCAD) simulation.     

Fabrication and characteristics of A Te-Se-CdO structure

A Te-Se-CdO layer structure has been fabricated by epitaxial growth of a selenium film on a monocrystalline tellurium substrate, followed by deposition of the counterelectrode by reactive sputtering from a cadmium target in the presence of a trace of air. Examination by RHEED has shown the counterelectrode to be CdO in polycrystalline form and the selenium film to be monocrystalline. The structures were found to give a maximum photovoltaic responsivity near 550 nm, at which wavelength the quantum efficiency was around 60% for a CdO thickness of 0.2 micron. The responsivity was affected by the CdO film thickness and the contacts to it but was insensitive to conditions relating to the selenium film, with variations in the thickness up to 10 microns, in the orientation between the (0001) and planes and in the polishing conditions of the tellurium stustrate. Values of equivalent series and shunt resistance were determined from output current-voltage results by curve fitting and the shunt resistance was found to vary inversely with illuminance.     

NbO电解电容器的结构及制造工艺新进展

较之钽电解电容器,NbO电解电容器电性能更好且价格较低.介绍了NbO电解电容器的结构和制造工艺.从材料及器件制备工艺两方面综述了国内外最近关于NbO电解电容器的研究新进展:通过镁蒸气两步还原法制备流动性较好的NbO粉体;对NbO粉进行掺杂和改性处理;在石墨层和银层中加入导电聚合物层,改善漏电流性能.最后对NbO电解电容...     

InP/空气隙结构的制作与特性

研究了采用不同溶液制作InP/空气隙的侧向腐蚀工艺,对腐蚀速率、晶向选择性、表面形貌进行了分析;研究了粘附释放工艺;在上述基础上制作完成了InP/空气隙结构,并采用微拉曼光谱来分析其应力分布情况,证实了制作工艺的可靠性.     

Evaluation of some algorithms and programs for the computation ofinteger-order Bessel functions of the first and second kind with complexarguments

The efficiency and accuracy of a few available algorithms for the computation of integer-order Bessel functions are considered. First, the computation of integer-order Bessel functions of the first kind, using the fast Fourier transform (FFT) algorithm as opposed to recurrence techniques, is investigated. It is shown that recurrence techniques are superior to the FFT technique, both in accuracy and speed. An algorithm suggested in the literature and used in commercially available software, specifically MATLAB 3.5 and MATHEMATICA 1.2, for computing integer-order Bessel functions of the second kind is revealed to be erroneous by comparing these routines with an algorithm developed by the author. It is shown that catastrophic errors result from using the erroneous algorithm to compute high-order Bessel functions with nonreal arguments     

Physical fundamentals and technical aspects of the lateral thyristor

Different types of the lateral thyristor as well as their way of functioning and their properties with various modes of operation are described and compared. Particular attention has been paid to the problem of turning off the thyristor operated with direct voltage. In the comparative reflections, a type of the lateral thyristor is included which is not available commercially, but which as a turn-off thyristor offers some advantages in comparison to other types. This epitaxial lateral thyristor was produced at our laboratory and thoroughly examined—including the component structures it contains (epitaxial lateral transistor, P⁺NN⁺ diode).     

Simultaneous estimation of first and second derivatives of a cost function

A correlation method for estimating the second derivative, as well as the first derivative, of a cost function which is quadratic in an input parameter is described. The method, using a 3-level msequence perturbation signal, enables the cost-function minimum to be reached in a single step in a noisefree system. The effects of noise, and the extension of the method to multiparameter cost functions, are discussed.