ICS1523型高性能可编程行同步时钟发生器的原理及应用

ICS1523是一种高性能可编程行同步信号发生器,它带有一个I2C串行总线接口,可以方便地对内部寄存器进行配置,能产生用户需要的同步信号.详细介绍该电路的工作原理和寄存器格式,给出ICS1523与S1D13806的实际接口电路及程序设计.     

A programmable clock generator that uses noise shaping and itsapplication in switched-capacitor filters

A programmable digital clock generator that produces a wide range of clock frequencies with fine resolution is described. The clock generator consists of a noise-shaping control loop and a number-controlled oscillator. The generated clock has a time-varying period. When this clock is used as the sampling clock in a switched-capacitor filter (SCF) to set its frequency response, the time-varying period causes nonuniform sampling, which is acceptable under certain conditions that are described. Measured performance of a 2-μm CMOS implementation of the clock generator is presented. Also, measured data for the clock generator driving two SCF's are reported     

一种基于分频链的时钟校准方法

针对晶体振荡器的温漂特性,设计了一种基于分频链的时钟校准算法。在不改变晶体振荡器的情况下可调节时钟频率,校准精度达±0.25ppm,校准范围±32ppm,通过多次实验分析,用Verilog-HDL语言编写全部模块,在modelsim6.2b软件中实现模块仿真。全部功能正常实现,符合设计要求。     

A high-speed four-phase clock generator for low-power on-chip SerDes applications

In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for on-chip SerDes applications. The device utilizes a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 μm². With a power supply of 1.1 V the complete circuit consumes 89.56 μW at room temperature.     

控制激光的可编程脉冲信号发生器

用可编程脉冲信号发生器控制激光脉冲的频率、脉宽和功率,使激光脉冲在微机控制下可组成各种激光脉冲序列。     

Emitter-coupled pair chaotic generator circuit

An emitter-coupled pair chaotic generator is proposed with a control parameter that can be tuned for distinct chaotic behaviors. The proposed circuit is a compact, high-speed implementation of the chaotic map based on the hyperbolic tangent function. It is demonstrated that the circuit and map parameters are analytically related. As an application, we design a random number generator that passes all NIST statistical tests by applying a post-processing to the balanced bit sequence generated by a quantization of the circuit output.     

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.     

A synthesizable pseudo fractional-N clock generator with improved duty cycle output

A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle output is presented by the pseudo fractional-N frequency synthesizer unit for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated by following the design flowchart. It has been fabricated in a 0.13 μm CMOS technology and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed synthesizable pseudo fractional-N clock generator is from 12.5 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rate of the output clock frequency is 1.5% and the measured power dissipation of the pseudo fractional-N frequency synthesizer unit is 146 μW at 304 MHz.     

基于DP标准发射端扩频时钟发生器电路设计

在优化各模块电路性能及相关参数,综合考虑电路功耗、性能等方面因素的基础上．设计符合DisplayPort接口标准的发射端扩频时钟发生器。通过整体的电路级仿真验证,表明该设计达到了降低电磁干扰的目的。     

一种高精度时钟同步电路

本文提出了一种基于交错延迟单元和动态补偿电路的高精度时钟同步电路结构,HPSC,并 可用在对时钟要求较高的大规模分布网络中。此电路采用了基于SMD的粗调结构和动态补偿 电路的细调结构,可在两个时钟周期内完成粗调并在接下来三个时钟周期内完成细调,其误 差小于3.8 ps。本电路使用SMIC 0.13 μm 1P6M 工艺设计并实现,供电电压1.2 V。其输入 频率为200MHz-800MHz,占空比为20%-80%,有效面积 245μm×134μm,功耗为1.64 mW@500MHz     

一种频率可调时钟产生电路的研究

研究了一种用于微机械加速度计的CMOS时钟产生电路.该电路可以方便地实现片内时钟的精确产生,集成了具有高电源抑制比的基准电压源,振荡频率可根据需要调节.实际电路采用1.2 μm双层多晶硅、双层金属N阱CMOS工艺实现.在5 V电源电压、800 kHz振荡频率下,该电路功耗约为1.5 mW.     

A low noise 0.9 GHz FBAR clock

A low noise 0.9 GHz FBAR clock consisting of an oscillator and divider circuit for single-sided-to-differential conversion for a high-speed interleaved pipeline A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 μm CMOS process, and tested. The circuit showed very good jitter and phase noise performance. A temperature coefficient of –47 ppm/K was measured.     

Current mode read-out circuit for InGaAs photodiode applications

Infrared focal plane arrays have many military, industrial, medical, and scientific applications that require high-resolution and high-performance read-out electronics. In applications involving InGaAs sensor arrays, data read-out can be carried out by circuits implemented with CMOS technology. In this paper we propose a dynamically regulated cascode current mirror for pixel read-out. From simulation results, we expect this circuit to achieve a better trade-off between silicon area, signal-to-noise ratio, and output dynamic range than the trade-off that is currently achieved by current mode CMOS read-out circuits.     

A universal programmable driving circuit for spatial light modulators

ea of only 65 × 65μm2.     

通用可编程多量子阱空间光调制器驱动电路

A universal programmable multi-quantum-well（MQW） spatial light modulator（SLM） driving circuit is developed.With a twice scanning, it can generate programmable signals to drive a non-linear MQW SLM by using a software preprocessing unit.By adjusting the switching network of the driving circuit, this circuit can reduce the switching noise and improve the output precision.The chip test results show that the driving voltage can swing from 0 to VDD, and its resolution could be close to 256 with a pixel area of only 65 × 65 μm2.     

一种高效率的适合于低功耗应用的电荷泵电路

设计实现了一种高效率的电荷泵电路。利用电容和晶体管对电荷传输开关进行偏置来消除开关管阈值电压的影响。同时,通过对开关管的的衬底进行动态的偏置使得在电荷传输期间当开关管打开时其阈值电压较低,在开关管关断时其阈值电压较高。该电荷泵电路的效率得到了提高。基于0.18μm,3.3V标准CMOS工艺实现了该电路。在每级电容为0.5pF,时钟频率为780KHz,电源电压为2V的情况下,测得的8级电荷泵的输出电压为9.8V。电荷泵电路和时钟驱动电路从电源处总共消耗了2.9μA的电流。该电荷泵电路适合于低功耗的应用。     

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.     

静电放电模拟器电路建模分析

从实际的静电放电模拟器结构出发,根据接触放电时静电放电电流的主要特征,考虑到静电模拟器本身、连接线及回路电缆与地平面间产生的分布参数的影响,建立了一个新的静电放电模拟器等效电路模型,并用PSPICE软件对等效电路进行模拟分析,得到了与实测波形基本一致的电流波形.利用该模型讨论了各分布参数对放电电流的影响.结果表明:模拟器体电阻与地间的电感对电流波形影响不大,因此可以忽略,但其与地之间的分布电容对电流波形的低频段有重要影响;连接线分布参数对电流波形的第一峰值及波形光滑度都有影响;回路电缆分布参数主要影响了电流波形中第二个波峰峰值及其位置.     

一种用于光通信的新型时钟提取电路设计

提出了一种采用数据转换跟踪环的时钟提取电路设计方法,介绍了这种新环路的设计结构及工作原理,并对环路性能进行了理论分析和仿真.分析和仿真表明,该电路具有很好的跟踪性能,信噪比较低时可以保持锁定状态,有突发相位抖动出现时可快速进入锁定.可以用于光纤通信系统中.     

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Post-layout Monte Carlo analysis and characterization as function of temperature, process, and mismatch variations of a rail-to-rail full clock fully programmable differential rectifier and sample-and-hold amplifier (RSHA) for biomedical applications are presented in this paper. The RSHA is based on a class AB fully differential two-stage operational amplifier. It uses the Miller compensation capacitor to hold the output and a duplicate of the output stage to ensure proper offset cancellation and common-mode control. The circuit is designed and implemented using a 0.35 μm CMOS technology. Results show that the total harmonic distortion, for an almost rail-to-rail input swing at 10 kHz and at 100 kS/s is equivalent to more than 9 bits in worst case. The dc output offset is below 140 μV and the error introduced by the rectification with respect to the non rectified signal is less than −100 dB. The power consumption is 3 mW with ±1.25 V supplies. The RSHA provides an output valid for more than 85% of the clock cycle.