Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

Fully self-aligned tri-layer a-Si:H thin-film transistors withdeposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n⁺ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V_DS=0.1 V) and saturation region (V_DS=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10⁷     

Dependence of Threshold Voltage of a-Si:H TFT on a-SiN_x:H Film

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Exploiting In Situ Redox and Diffusion of Molybdenum to Enable Thin‐Film Circuitry for Low‐Cost Wireless Energy Harvesting

Direct additive fabrication of thin‐film electronics using a high‐mobility, wide‐bandgap amorphous oxide semiconductor (AOS) can pave the way for integration of efficient power circuits with digital electronics. For power rectifiers, vertical thin‐film diodes (V‐TFDs) offer superior efficiency and higher frequency operation compared to lateral thin‐film transistors (TFTs). However, the AOS V‐TFDs reported so far require additional fabrication steps and generally suffer from low voltage handling capability. Here, these challenges are overcome by exploiting in situ reactions of molybdenum (Mo) during the solution‐process deposition of amorphous zinc tin oxide film. The oxidation of Mo forms the rectifying contact of the V‐TFD, while the simultaneous diffusion of Mo increases the diode's voltage range of operation. The resulting V‐TFDs are demonstrated in a full‐wave rectifier for wireless energy harvesting from a commercial radio‐frequency identification reader. Finally, by using the same Mo film for V‐TFD rectifying contacts and TFT gate electrodes, this process allows simultaneous fabrication of both devices without any additional steps. The integration of TFTs alongside V‐TFDs opens a new fabrication route for future low‐cost and large‐area thin‐film circuitry with embedded power management.     

Dependence of Threshold Voltage of a-Si:H TFT on a-SiNx:H Film^①

The relation between threshold voltage for hydrogenated amorphous silicon thin film transistors(a-Si:HTFTs)and deposition conditions for hydrogenated amorphous silicon nitride(a-SiNx:H)films is investigated.It is observed that the threshold voltage,Vth,of a-Si:HTFT increases with the increase of the thickness of a-SiNx:H film,and the threshold voltage is reduced apparently with the increase of NH3/SiH4 gas flow rate ratio.     

Effects of oxygen on crystallization of amorphous silicon films and polysilicon TFT characteristics

Oxygen ions were implanted into the amorphous silicon film deposited at 540°C in order to study the effects of oxygen on the solid phase crystallization of silicon films. The resulting films were investigated using transmission electron microscopy, x-ray diffraction (XRD), and also by measuring the electrical characteristics of polycrystalline silicon thin film transistors (TFTs) fabricated in the crystallized films. The development of {111} texture as a function of annealing time is similar to films implanted with Si, with higher oxygen samples showing more texture. Transmission electron microscopy shows that the grain size of completely crystallized films varies little with oxygen concentration. The electrical performances of TFTs are found to degrade with increasing oxygen dose. The trap state density increases from 5.6 × 10¹²/cm² to 9.5 × 10¹²/cm² with increasing oxygen dose. It is concluded that for a high performance TFT, oxygen incorporation in the Si film should be kept to 10¹⁹/cm³ or less.     

Structural characteristics of as-deposited and crystallized mixed-phase silicon films

In this work, we report on the structural characteristics of as-deposited and crystallized mixed-phase silicon films prepared by thermal decomposition of silane in a low pressure chemical vapor deposition reactor. Mixed-phase films consist of crystallites embedded in an amorphous matrix. The size of these crystallites depends upon the surface diffusion length, a parameter quantitatively expressing the potential of adsorbed silicon atoms for surface diffusion. The density of the pre-existing crystallites can be related to the maximum density of critical nuclei, which develops during the deposition of the film. Both variables were quantitatively related to the deposition temperature and rate via physical models reflecting the experimental observations. Values for the parameters associated with these models were extracted by fitting the experimental data to the theoretical equations. Our theoretical analysis is the first to relate quantitatively the structural characteristics of as-deposited mixed-phase films to the prevailing deposition conditions. Mixed-phase films can crystallize in a much shorter time than as-deposited amorphous films, due to the combination of the growth of the pre-existing crystallites and the higher nucleation rate of new crystallites within the amorphous matrix of the mixed-phase film. The crystallization time and final grain size of crystallized mixed-phase films were found to decrease with increasing density of pre-existing crystallites. However, we showed that if composite films are deposited, consisting of a mixed-phase layer and an amorphous layer, the grain size after crystallization could be comparable to that of crystallized as-deposited amorphous films, with the crystallization time of such composite films about threefold shorter. The structure of both as-deposited and crystallized single and composite mixed-phase films was found to be identical for films deposited on both oxidized silicon and Corning Code 1735 glass substrates.     

High-performance thin-film transistors in large grain sizepolysilicon deposited by thermal decomposition of disilane

The characteristics of polycrystalline silicon thin-film transistors (TFTs), fabricated on films deposited in an LPCVD system using disilane, were investigated as a function of grain size. The grain size and its statistical distribution were correlated with processing conditions; optimum conditions to maximize grain size for device applications were determined. The dependence of the ON current and the OFF (leakage) current of polysilicon TFTs, as well as of their statistical distributions, on the grain size, the gate dielectric processing temperature, the channel length, and the device structure are reported and discussed. Larger grain size polycrystalline silicon films were found to yield devices with higher mobilities and lower leakage currents. TFTs, fabricated in polysilicon films with average grain sizes of 1.8 μm with thermally grown silicon dioxide as gate dielectric, had ON/OFF current ratio well above 10⁸, average effective mobility value of 170 cm²/V.s and subthreshold slope of 0.3 V/dec     

用于TFT有源层的Ar~+激光结晶a-Si:H的性质(英文)

This paper demonstrates the technological approach to the high performance a-Si:H thin film transistor (TFT) fabricated by the Ar+ laser-crystallization technique on the fused quartz substrates. The a-Si:H films for the active layer of TFT were prepared in a capacitively coupled glow-discharge deposition system. The films were crystallized by CW Ar+ laser scanning at low speeds (3-5 cm/s). The laser power ranges from 2.5W to 5.0W. The TEM cross-section micrograph illustrates that a liquid phase laser crystallization region (LP-LCR) has defect-free of structure with a grain size of the order of handreds of micron. In the Raman spectrum of LP-LCR, 475 cm-1 peak of a-Si:H disappears and 520 cm-1 peak of c-Si becomes stronger and sharper. The value of conductivity in the layer of LP-LCR is five orders of magnitude larger than the one in asepositedd a-Si:H film. We also discussed some problems to be overcome in application of a-Si : H TFTs in LCD.     

α-Si-H TFT及有源矩阵选址平板液晶显示

本文报道了用于平板液晶显示(LCD)的氢化非晶硅薄膜晶体管(α-Si:H TFT)的研制结果,此晶体管开态电流约10~(-6)A,关态电流<10~(-11)A,开启电压～15V.用此α-Si:H TFT矩阵已封装出具有20×20个有效象素单元的液晶显示平板,并成功地实现了有源选址与动态显示功能.同时,对如何进一步提高TFT性能作了一些分析与讨论.     

Influence of rapid thermal and low temperature processing on theelectrical properties of polysilicon thin film transistors

In this paper rapid thermal processing (RTP) is studied for the crystallization and oxidation of deposited silicon layers. The purpose is to present and compare the results obtained by RTP, low temperature processing (LTP), or a combination of both, for the fabrication of polycrystalline silicon thin film transistors (poly-TFT's). The polysilicon and polyoxide are obtained by low thermal annealing, oxidation (LTA, O) and/or rapid thermal annealing, oxidation (RTA, O) of amorphous silicon films deposited from disilane at a temperature of 465°C. For the Si films annealed at 750°C or higher, using RTA, the grain average sizes are reduced whereas the electron/hole mobilities are increased. We suggest that there is a correlation between the optical extinction coefficient k (at λ=405 nm), the potential barrier height Φ_B due to the grains, and the field-effect mobility, μ_n,p, of the polysilicon film. This correlation indicates that the polysilicon film electrical properties depend not only on the grain size, but also on the crystalline quality of the grains. Moreover, it appears that the large amount of crystalline defects remaining in the so-called “grains” of the films annealed at 600°C (LTA) are partially annihilated when the films are annealed at higher temperatures. With regards to the TFT's electrical characteristics, the work suggests combining RT and LT steps to obtain TFT's with improved electrical performance     

Amorphous-silicon thin-film transistor with liquid phase depositionof silicon dioxide gate insulator

The liquid phase deposition of silicon dioxide (LPD-SiO₂) at 50°C has been successfully applied as the gate insulator for inverted, staggered amorphous silicon thin-film transistors (TFTs). The maximum field-effect mobility of the TFTs, estimated from the saturation region, was 0.53 cm²/V-s, comparable to that obtained for conventional, silicon nitride (SiN_x ) gate transistors. The threshold voltage and subthreshold swing were 6.2 V and 0.76 V/decade, respectively. Interface and bulk characteristics are as good as those obtained for silicon nitride (SiN _x) films deposited by plasma enhanced chemical vapor deposition     

Investigation of structure and properties of nanocrystalline silicon on various buffer layers

A comparative study of deposition nanocrystalline silicon (nc-Si) on various buffer layers is investigated. The nc-Si films were deposited in a hot-wire chemical vapor deposition (CVD) system. Through Hall measurement, scanning electron microscopy (SEM), atomic force microscope (AFM), Raman, and x-ray diffraction (XRD) analyses, it was found that the columnar grain (CG) size, mobility, and volume fraction of crystalline-deposited nc-Si films increase with an increase of the buffer layers’ surface roughness. The nc-Si film deposited on the nc-Si buffer layer possesses the highest Xc (volume fraction of crystalline) of 84.32%, Hall mobility of 45.9 (cm²/V s), and CG size of 200–220 nm, and it shows the strongest intensity of the XRD diffraction peak in (111).     

Dependence of thin film transistor characteristics on thedeposition conditions of silicon nitride and amorphous silicon

The systematic relation between thin film transistors' (TFT's) characteristics and the deposition conditions of amorphous silicon nitride (a-SiN) films and hydrogenated amorphous silicon (a-Si:H) films is investigated. It is observed that field effect mobility μ_FE and threshold voltage V_th of the TFT's strongly depend on the deposition conditions of these films. The maximum μ_FE of 0.88 cm²/V·s is obtained for the TFT of which a-SiN film is deposited at a pressure of 85 Pa. This phenomenon is due to the variation of the interface states density between a-Si:H film and a-SiN film     

Performance and reliability of SLS ELA polysilicon TFTs fabricated with novel crystallization techniques

SLS ELA polysilicon TFTs fabricated in films crystallized with several novel techniques, yielding different film microstructure and texture, were investigated. The parameter statistics indicate that the TFT performance depends on film quality and asperities, in conjunction with the grain boundary trap density. The drain current transients, upon TFT switch from OFF to ON state, showed gate oxide polarization, related to film asperities and also confirmed the presence of extended defects in the TFTs of small mobilities. DC hot carrier stress was applied, indicating a reliability dependence on polysilicon structure and differences in degradation mechanisms for the various TFT technologies.     

Highly Robust Bendable Oxide Thin‐Film Transistors on Polyimide Substrates via Mesh and Strip Patterning of Device Layers

Advancement in thin‐film transistor (TFT) technologies has extended to applications that can withstand extreme bending or folding. The changes of the performances of amorphous‐indium‐gallium‐zinc‐oxide (a‐IGZO) TFTs on polyimide substrate after application of extreme mechanical bending strain are studied. The TFT designs include mesh and strip patterned source/drain metal lines as well as strip patterned a‐IGZO semiconductor layer. The robustness of the a‐IGZO TFTs with the strain of 2.17% corresponding to the radius of 0.32 mm is tested and no crack generation even after 60 000 bending cycles is found. The split of source/drain electrodes and semiconductor layer can improve the mechanical bending stability of the TFTs. This can be possible by using conventional TFT manufacturing process so that this technology can be easily applied to build robust TFT array for foldable displays.     

Thin-film transistors on plastic and glass substrates using silicon deposited by microwave plasma ECR-CVD

Thin-film transistors (TFTs) were fabricated on polyimide and glass substrates at low temperatures using microwave ECR-CVD deposited amorphous and nanocrystalline silicon as active layers. The amorphous Si TFT fabricated at 200 /spl deg/C on the polyimide foil had a saturation region field effect mobility of 4.5 cm/sup 2//V-s, a linear region mobility of 5.1 cm/sup 2//V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/decade, and an ON/OFF current ratio of 7.9 /spl times/ 10/sup 6/. This large mobility and high ON/OFF current ratio were attributed to the high-quality channel materials with less dangling bond defect states. Nanocrystalline Si TFTs fabricated on glass substrates at 400 /spl deg/C showed a saturation region mobility of 14.1 cm/sup 2//V-s, a linear region mobility of 15.3 cm/sup 2//V-s, a threshold voltage of 3.6 V, and an ON/OFF current ratio of 6.7 /spl times/ 10/sup 6/. TFT performance was mostly independent of substrate type when fabrication conditions were the same.     

Influence of substrate temperature on the performance of zinc oxide thin film transistor

Top-contact thin film transistors（TFTs） using radio frequency（RP） magnetron sputtering zinc oxide （ZnO） and silicon dioxide（SiO₂） films as the active channel layer and gate insulator layer,respectively,were fabricated.The performances of ZnO TFTs with different ZnO film deposition temperatures（room temperature, 100℃and 200℃） were investigated.Compared with the transistor with room-temperature deposited ZnO films, the mobility of the device fabricated at 200℃is improved by 94%and the threshold voltage shift is reduced from 18 to 3 V（after 1 h positive gate voltage stress）.Experimental results indicate that substrate temperature plays an important role in enhancing the field effect mobility,sharping the subthreshold swing and improving the bias stability of the devices.Atomic force microscopy was used to investigate the ZnO film properties.The reasons for the device performance improvement are discussed.     

高性能钆铝锌氧薄膜晶体管的制备

本文研究并制备了钆铝锌氧薄膜和以钆铝锌氧为有源层的薄膜晶体管。钆铝锌氧薄膜材料的光致发光光谱和透过率说明钆铝锌氧薄膜在透明显示方向的应用潜力。透射电子显微镜揭示了钆铝锌氧薄膜的非晶态微观结构。钆铝锌氧薄膜晶体管显示了良好的转移特性和输出特性。器件开关比大于10~5、饱和迁移率约为10cm~2·V~(-1)·s~(-1)。实验结果表明,钆铝锌氧薄膜可用作氧化物薄膜晶体管的有源层材料;钆铝锌氧薄膜晶体管可作为像素电路的驱动器件。     

Review of recent progresses on flexible oxide semiconductor thin film transistors based on atomic layer deposition processes

The current article is a review of recent progress and major trends in the field of flexible oxide thin film transistors (TFTs),fabricating with atomic layer deposition (ALD) processes.The ALD process offers accurate controlling of film thickness and composition as well as ability of achieving excellent uniformity over large areas at relatively low temperatures.First,an introduction is provided on what is the definition of ALD,the difference among other vacuum deposition techniques,and the brief key factors of ALD on flexible devices.Second,considering functional layers in flexible oxide TFT,the ALD process on polymer substrates may improve device performances such as mobility and stability,adopting as buffer layers over the polymer substrate,gate insulators,and active layers.Third,this review consists of the evaluation methods of flexible oxide TFTs under various mechanic al stress conditions.The bending radius and repetition cycles are mostly considering for conventional flexible devices.It summarizes how the device has been degraded/changed under various stress types (directions).The last part of this review suggests a potential of each ALD film,including the releasing stress,the optimization of TFT structure,and the enhancement of device performance.Thus,the functional ALD layers in flexible oxide TFTs offer great possibilities regarding anti-mechanical stress films,along with flexible display and information storage application fields.