激光热处理对化学沉积Ni-P合金薄膜性能的影响

用扫描电镜(SEM)观察了化学沉积Ni-P合金薄膜/单晶硅基体的结构与颗粒度,利用X射线衍射(XRD)技术测试了其化学沉积后的残余应力,测量了激光热处理后残余应力的变化规律,分析了残余应力对磨损性能及界面结合强度的影响。实验结果表明,化学沉积Ni-P合金薄膜/硅基体的残余应力均表现为拉应力,经过激光热处理后残余应力发生了变化,由高值的拉应力变为低值的拉应力或压应力;薄膜残余应力对其磨损性能有明显的影响,其磨损量随着残余应力的减小而减小;薄膜与基体结合强度随着残余应力的增大而减小,合理地选择激光热处理参数可以精确地控制薄膜残余应力,提高其结合强度。     

Preparation of silicon-on-gallium arsenide wafers for monolithicoptoelectronic integration

A process is described which combines silicon-on-insulator (SOI) and wafer bonding techniques to create thin (≈100 nm) single-crystal silicon layers on oxide coated gallium arsenide wafers for use in optoelectronic integration. Using a GaAs substrate for the integration eliminates the thermal expansion coefficient mismatch problems which have blocked monolithic integration of thick, stress sensitive optoelectronic devices on silicon, without compromising the performance of CMOS circuitry which can be fabricated in very thin, compressively strained silicon layers using SOT techniques     

Comparison of Phase Shifting Techniques for Measuring In-Plane Residual Stress in Thin, Flat Silicon Wafers

This paper reports on a comparison of the six- and ten-step phase shifting methods in digital transmission photoelasticity and the application of these methods to obtain the residual stresses in thin (200 μm), flat crystalline silicon wafers (156 mm square). The ten-step phase shifting technique is judged to be superior with reduced noise in the isoclinics and a resulting higher accuracy when dealing with the near-zero retardation prevalent in residual stress measurements of silicon wafers.     

磁控溅射制备Zr膜的应力研究

为了研究磁控溅射方法制备的Zr膜的应力分布情况,采用探针轮廓仪测量镀膜前后基片在1维方向上的形变,根据镀膜前后基片曲率半径的变化和Stoney公式,用自编应力计算软件计算出薄膜的内应力。结果表明,Zr膜中主要存在的是压应力,且分布不均匀;工作气压对Zr膜内应力影响不大,但膜厚对Zr膜内应力影响较大,且随膜厚的增加,Zr膜中压应力减小。     

Pattern transfer of microstructures between deeply etched surface for MEMS applications

Photolithography plays a vital role in micromachining process however; coating a thin and uniform resist layer on a non-planar surface is a challenging task for micro-electro-mechanical system (MEMS). Conventional spin coating of photoresist (PR) over an un-even surface would deliver streaks all over the wafer surface. Spray coating of PR is a promising technique when compared to other candidates. This paper presents an efficient pattern transfer of microstructures between the bulk micromachined cavities over silicon and glass wafers using an uncommon photoresist mixture being spray coated. The method is simple and highly cost effective. Finally we implemented this technique for a MEMS application to prove the feasibility of spray coating for microstructure fabrication.     

A New Method for Microlens Fabrication by a Heating Encapsulated Air Process

This letter reports a new method to fabricate thin microlens array on a silicon substrate by a heating encapsulated air process. We use silicon bulk micromachining, wafer-to-wafer bonding, and photoresist (PR) spin coating to achieve the air sealing process. Under a heating process, the PR filled in the micro-through-hole of cap wafer is compressed by the thermal expansion of the sealed air to form a thin microlens with out-of-plane sphere shape. By adjusting the heating temperature and the sealed air volume, the curvature and size of the lens are controllable. A typical microlens with a diameter of 1475 mum and sag height of 486 mum was fabricated. The calculated radius of curvature and focal length are about 800 and 1200 mum, respectively. The fabrication provides an alternative way to manufacture thin microlens or microlens mold serve as master elements for replication     

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

Given the trend towards wafers of a larger diameter, microelectronics circuits are driven by modern IC manufacturing technology. Silicon wafer breakage has become a major concern of all semiconductor fabrication lines because silicon wafer is brittle and high stresses are induced in the manufacturing process. Additionally, the production cost is increasing. Even a breakage loss of a few per cent drives up device costs significantly if wafers are broken near completion, but wafer breakage even near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength empolying a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.This work presents an approach for characterizing silicon wafer failure strength using a simple drop test, to improve our understanding of the stress accumulated in wafer bulk before failure. However, this work will describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unknown reasons. According to an analysis based on the material mechanical theory for the bevel lengths (A1, A2), the edge length and the bevel angle (θ) are optimized to design the edge profile of the produced wafer, to prevent wafer breakage. Restated, when proper material and process control techniques are utilized, silicon wafer breakage should be prevented. This work is the first to demonstrate the importance of understanding wafer strength using a simple mechanical approach.     

ZnS thin film deposition on Silicon and glass substrates by Thermionic vacuum Arc

In this study, Silicon (Si) and glass substrates were coated with Zinc sulfide (ZnS) using Thermionic Vacuum Arc (TVA) technique for the first time. With this technique, the coating time of the samples is very short and film thickness can be controlled during the coating process. Moreover, TVA provides many advantages to deposited thin films than other techniques such as compactness, low roughness, nanostructures, homogeneities as compared to other deposition techniques. This paper presents a different technique for deposition of high-quality ZnS thin films. Scanning electron microscopy (SEM), energy dispersive X-ray spectroscopy (EDX) and atomic force microscopy (AFM) were used to characterize the coated silicon and glass surface morphologies. Additionally, transmittances, thickness and refractive indices of coated glass samples with ZnS were measured by ultraviolet–visible spectrophotometer and interferometer to characterize their optical properties.     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

Investigations of the influence of dicing techniques on the strength properties of thin silicon

Thin silicon offers a variety of new possibilities in microelectronical, solar and micromechanical industries, e.g. for 3D-integration (stacked dies), thin microelectromechanical packages or thin single crystalline solar cells. The wafers in this investigation were thinned back by grinding and subsequent spin etching steps for stress relief followed by separation into single test dies by sawing or etching. In order to characterize and optimize relevant process steps in terms of quality and fabrication yield, the mechanical properties were investigated considering the defect formation and strength. In this paper the influence of three different dicing technologies on the mechanical strength of thin silicon samples was investigated by 3-point bending tests. Sawing, Dicing-by-Thinning with sawn grooves and Dicing-by-Thinning with dry-etched trenches were used as dicing technologies. Analytical and numerical calculations were performed to calculate fracture stresses from fracture forces in 3-point bending tests taking into account the non-linear relationship of force and displacement during testing. Thus the fracture stress as a parameter of strength could be calculated for all tested samples. The results were statistically evaluated by the Weibull distribution based on the weakest link theory. This approach allows a more comprehensive understanding of the influence of the process on strength properties independently of geometric factors. Samples, being separated by “Dicing-by-Thinning”, have much higher strength than simply sawed samples. If trenches are fabricated by dry-etched process the strength can be increased tremendously.     

Mechanical stability of PECVD silicon nitride protective films over bondwires, bonds and bondpads during thermal stress

PECVD silicon nitride thin films have potential application as protective diffusion barriers against water and aggressive ions which might corrode aluminum bondpads, bonds, and bondwires in packaged microelectronic assemblies. Test articles representing mounted and bonded devices were coated with silicon nitride films of thicknesses from 50 to 20,000 Å, then subjected to temperature and chemical stresses. These thin films exhibited less tendency to crack under temperature stress than would be predicted based on the physical properties of bulk silicon nitride. Films of less than one micron thickness over Al structures did not crack under standard industrial temperature cycling and showed good coverage near the bond interfaces and around the bondwires. The spread of Al metallization corrosion under these films proceeded at a slower rate beneath the thinner films due to their more favorable mechanical properties. Although the intrinsic stresses could not be measured, the decreased tendency for the thinner films to crack is primarily a result of higher ultimate strain and not initial compressive stresses.     

Microstructure and mechanical properties of ceramic/self-assembled monolayer bilayer coatings

Thin ceramic coatings/films find their applications in various electronic devices, sensors, and microelectromechanical systems (MEMS) as a protection/barrier layer as well as functional films. Ceramics are, however, susceptible to catastrophic failure due to their inherent brittleness. We have developed a strain-tolerant, bilayer coating consisting of a ceramic layer and a self-assembled monolayer (SAM). The top ceramic coating offers an inert, protective layer, while the underlying SAM acts as a “template” for the subsequent growth of a hard ceramic coating. In this study, we explore the ZrO₂/SAM coatings on Si substrates prepared in situ at 80°C in solution. The coatings exhibited good coverage on the silicon surface, but the hardness was rather low. Characterization tools including x-ray diffraction (XRD), atomic force microscopy (AFM), scanning electron microscopy (SEM), and nanoindentation were employed to achieve a better understanding of the synthesis and processing of the coatings and their relation to the mechanical properties.     

Laser recrystallised SOI with periodical seeding filled by selective epitaxial growth

A periodic seeding technique for obtaining thin silicon films on an insulator (SOI) by laser recrystallisation is described. Two types of seed structure as well as their orientations relative to the scan direction are discussed. Geometrical parameters are optimised to obtain 35?m-wide defect-free SOI stripes across 4in (101-6mm) silicon wafers.     

Non-destructive evaluation of residual stresses in thin films via x-ray diffraction topography methods

Quantitative x-ray diffraction topography techniques have been used to measure the residual strain magnitude and uniformity of deposition for Mo and W sputtered films on Si(100) substrates. High sensitivity rocking curve measurements were able to determine differential strains for films as thin as 2.5 nm; while Bragg angle contour mapping had similar sensitivity and was also able to assess coating uniformity and stress distribution over areas covering a whole wafer. Measurements of strain versus film thickness over a range of 2.5 nm to 80 nm showed that a critical thickness exists for maximum residual strain. Growth beyond this range produces stress relaxation. This non-destructive type of analysis could be employed on a wide range of film-substrate combinations.     

Influence of Ni-Doping in ZnO Thin Films Coated on Porous Silicon Substrates and ZnO|PS Based Hetero-Junction Diodes

Semiconductors - Ni2+-doped ZnO thin films were prepared for various Ni concentration on the porous silicon substrates. The residual stress in the ZnO thin film is relaxed with increase in the...     

Photoresist deposition without spinning

A technique for resist deposition using a novel fluid ejection method is presented in this paper. An ejector has been developed to deposit photoresist on silicon wafers without spinning. Drop-on-demand coating of the wafer reduces waste and the cost of coating wafers. Shipley 1400-21, 1400-27, 1805, and 1813 resists were used to coat sample 3- and 4-in wafers. Later, these wafers were exposed and developed. The deposited resist film was 3.5 /spl mu/m thick and had a surface roughness of about 0.2 /spl mu/m. The ultimate goal is to deposit resist films with a thickness of the order of 0.5 /spl mu/m and a surface roughness of the order of 30 /spl Aring/, which is currently achieved for 200-mm silicon wafers by using a spinning method. Such goals can be attained by using micromachined multiple ejectors or with better control over the deposition environment. In the micromachined configuration, thousands of ejectors are made into a silicon die, as presented by Percin et al. (2002), and thus allow for a full coating of a wafer in a few seconds. Coating in a clean environment will allow the lithography of circuits for microelectronic applications. Other potential applications for the technology in the semiconductor manufacturing are in deposition of low-k materials, wafer cleaning, manufacturing of organic LEDs and organic FETs, direct lithography, nanolithography, and coating for hard-disk drives.     

Mimicking Biological Phenol Reaction Cascades to Confer Mechanical Function

Phenol reaction cascades are commonly used in nature to create crosslinked materials that perform mechanical functions. These processes are mimicked by electrochemically initiating a reaction cascade to examine if the mechanical properties of a biopolymer film can be predictably altered. Specifically, thin films (≈ 30–45 μm) of the polysaccharide chitosan are cast onto gold‐coated silicon wafers, the chitosan‐coated wafers are immersed in catechol‐containing solutions, and the phenol is anodically oxidized. The product of this oxidation is highly reactive and undergoes reaction with chitosan chains adjacent to the anode. After reaction, the flexible chitosan film can be peeled from the wafer. Chemical and physical evidence support the conclusion that electrochemically initiated reactions crosslink chitosan. When gold is patterned onto the wafer, the electrochemical crosslinking reactions are spatially localized and impart anisotropic mechanical properties to the chitosan film. Further, deswelling of chitosan films can reversibly transduce environmental stimuli into contractile forces. Films patterned to have spatial variations in crosslinking respond to such environmental stimuli by undergoing reversible changes in shape. These results suggest the potential to enlist electrochemically initiated reaction cascades to engineer chitosan films for actuator functions.     

Easy-to-use surface passivation technique for bulk carrier lifetime measurements on silicon wafers

A novel, easily applicable surface passivation technique is presented, which, in combination with contactless photocoductance decay (PCD) measurements, allows a quick estimation of the bulk carrier lifetime of crystalline silicon wafers. The proposed passivation technique requires neither a chemical pre-cleaning of the silicon wafer nor expensive instrumentation. On both surfaces of the wafer a thin varnish film is deposited using a spinner. Subsequently, both surfaces of the coated silicon wafer are charged by means of a corona chamber. Using microwave-detected PCD measurements, we experimentally demonstrate that this novel surface passivation scheme provides differential surface recombination velocities in the 30–70 cm s⁻¹ range on p-as well as n-type silicon wafers. © 1998 John Wiley & Sons, Ltd.     

PECVD沉积双层SiNx对太阳电池性能的影响

提出了一种简单有效的制备双层SiNx薄膜的方法,其薄膜具有良好的减反射钝化特性。采用等离子体增强化学气相沉积(PECVD)的方法,通过控制SiH4和NH3气体流量比,在p型多晶硅衬底上生长单层及双层SiNx膜。随后使用薄膜测试分析仪测量了薄膜的厚度、折射率及反射率,并用Semilab WT-2000测量少数载流子寿命,通过测量量子效率,对单、双层膜电池进行了比较。实验结果表明:相比单层减反射钝化膜,采用双层SiNx膜,少数载流子寿命可以得到更好的改善,开路电压可提高约2 mV,短路电流可提高约40 mA,电池效率能提高0.15%。     

Preparation and properties of plasma-anodized silicon dioxide films

The preparation and properties of thin films of silicon dioxide formed at ～ 200°C by anodization in an RF plasma are described. A suitable procedure for obtaining good quality films is given along with information on the effects of film sputtering and internal stress build-up during anodization. Measurements on MOS capacitors utilising the plasma-grown oxide yielded information on oxide charges, Si/SiO₂ interface state density, oxide permittivity, leakage resistance and film breakdown strength. Additional measurements determined the physical properties of stochiometry, impurity content, refractive index and etching behaviour. The plasma-anodized films can be routinely grown to a quality comparable with the best thermally-grown oxides.