FPGA高性能查找表的设计与实现

从电路角度探讨了查找表(LUT)实现原理,基于双相不交叠时钟,设计实现了一种LUT,能高效地完成移位寄存器与RAM的功能扩展。基于SMIC0.25μmCMOS工艺优化设计了对应的版图,给出了相应的HSPICE仿真结果。此电路结构增强了逻辑块的性能,提高了FPGA的整体效率与灵活性,已被应用于FPGA的设计中。     

The effect of logic block architecture on FPGA performance

This authors explore the effect of logic block architecture on the speed of a field-programmable gate array (FPGA). Four classes of logic block architecture are investigated: NAND gates, multiplexer configurations, lookup tables, and wide-input AND-OR gates. An experimental approach is taken, in which each of a set of benchmark logic circuits is synthesized into FPGAs that use different logic blocks. The speed of the resulting FPGA implementations using each logic block is measured. While the results depend on the delay of the programmable routing, experiments indicate that five- and six-input lookup tables and certain multiplexer configurations produce the lowest total delay over realistic values of routing delay. The fine grain blocks, such as the two-input NAND gate, exhibit poor performance because these gates require many levels of logic block to implement the circuits and hence require a large routing delay     

Theoretical Analysis of Effect of LUT Size on Area and Delay of FPGA

Based on architecture analysis of island style FPGA,area and delay models of LUT FPGA are proposed.The models are used to analyze the effect of LUT size on FPGA area and performance.Results show optimal LUT size obtained by computation models is the same as that from experiments:a LUT size of 4 produces the best area results,and a LUT size of 5 provides the better performance.     

基于LUT 的SRAM2FPGA 结构研究

作为微电子工业中发展最迅速的一个领域,现场可编程门阵列(FPGA) 的内部结构设计越来越受到业内人士 的关注。为此针对目前普遍采用的基于查找表(LUT) 的SRAM2FPGA ,着重研究了其逻辑模块设计、布线结构设计和 输入输出模块设计,同时也对此类FPGA 基本结构进行了优化设计。     

LUT尺寸对FPGA面积和延迟影响的理论分析

在分析隔离岛式FPGA结构的基础上,提出了基于LUT的面积和延迟模型,用于分析LUT尺寸对FPGA面积和性能的影响.结果表明利用计算模型得到的最佳LUT尺寸与实验结论一致:4-LUT获得最好的面积有效性,5-LUT获得较好的延迟.     

65nm Virtex-5 FPGA取得性能与密度突破

Virtex-5系列FPGA是Xilinx公司Virtex产品线的第五代产品,该系列基于业界最先进的65 nm三极栅氧化层技术、突破性的新型ExpressFabric技术和经过验证的ASMBL(高级硅模组块)架构。Xilinx公司亚太区市场营销总监郑馨南表示,Xilinx的设计团队在工艺技术、架构和产品开发方法学方面的创新,使Virtex-5 FPGA在性能和密度方面实现了突破,与前一代90nm FPGA相比,速度平均提高30%,容量增加65%,同时动态功耗降低35%,静态功耗保持相同的低水平,使用面积减小45%。     

FPGA LUT delay degradation due to HCI: Experiment and simulation results

Reliability of advanced VLSI circuits becomes more and more important as both product designers and manufactures relentlessly pursue technology advantages and stretch device physical limits to capitalize the consumer electronic market. In this paper, we focus on aging degradation of the Look-Up Table (LUT) on FPGAs. We have characterized the delay degradation of LUT dependent on the duty cycle and the frequency of stress signal. We have identified that the HCI degradation mechanism affects the fall delay more than the rise delay, it is related directly to the frequency stress and independent from the duty cycle. In addition, we built a model of the delay degradation due to HCI depending on switching frequency of stress signal and the aging time. Furthermore, we identified the relation between the effect of each aging transistor and the LUT delay for the HCI aging mechanism. This work is ideal for modelling the LUT aging mechanisms in FPGA.     

一种采用四/五输入可配置查找表结构和优化进位链的新型FPGA

本文提出了一种FPGA可编程逻辑单元中新型的查找表结构和进位链结构。查找表被设计为同时支持四输入和五输入的结构,可根据用户需要进行配置,且不增加使用的互连资源;在新型的进位链中针对关键路径进行了优化。最后在可配置逻辑单元中插入了新设计的可配置扫描链。该可编程逻辑单元电路采用0.13μm 1P8M 1.2/2.5/3.3V Logic CMOS工艺制造。测试结果显示可正确实现四/五输入查找表功能,且进位链传播前级进位的速度在同一工艺下较传统进位链结构提高了约3倍,同时整个可编程逻辑单元的面积较之前增大了72.5%。结果还显示,本文设计的FPGA在仅使用四输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4/Virtex 5/Virtex 6/Virtex 7系列FPGA;在仅使用五输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4系列FPGA。     

FPGA realization of high performance large size computational functions: multipliers and applications

In this paper, efficient design methodologies and systematic approaches for realizing large size signed multipliers based on the use of small-size embedded blocks in FPGAs are presented. Two algorithms, delay table and dynamic programming addition optimizations, are used to efficiently organize the addition of partial products. To demonstrate the effectiveness of our approaches, two large size operand computations are realized using our optimized large size multipliers. These functions are complex multiplication and matrix multiplication. The implementations target Xilinx’ and Altera’s FPGAs. When our approaches are compared to those of traditional techniques, the results show improvements of performance and area usage for both applications.     

Impact of advanced processing modules on the low-frequency noise performance of deep-submicron CMOS technologies

Fundamental studies related to the low-frequency (LF) noise performance in semiconductors started more than 40 years ago. In 1957, McWhorter published the first model for the 1/f noise in semiconductors, which is still in use. Whereas for many decades LF noise studies were mainly of fundamental and theoretical interests, in recent years, LF noise characterisation has become a very valuable diagnostic technique for the development of semiconductor materials and devices. Especially, the use of noise characterisation as a tool for reliability predictions has triggered the semiconductor engineering society. Not only the silicon starting material, but also many of the used process modules have a strong impact on the noise performance. This trend is becoming even more pronounced for the advanced deep-submicron technologies. For analog applications of scaled technologies, LF noise may even act as a showstopper. This review, therefore, focuses on the impact of advanced processing on the low-frequency noise behaviour. Both front- and back-end process modules are discussed.     

Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance

This paper reports that process-induced mechanical stress affects the performance of short-channel MOSFETs, and focuses on the effect of a plasma-enhanced CVD nitride contact-etch-stop layer. The stress in the channel region induced by the nitride layer changes transconductance (G_m), thereby changing the device performance. When the nitride stress varies from +300 MPa (tensile) to −1.4 GPa (compressive), NMOSFET performance degrades by up to 8% and PMOSFET performance improves up to 7%. These changes are caused by the modulation of the electron/hole mobilities, so controlling process-induced stress and considering this mobility change in a precise transistor model are necessary for deep-submicron transistor design.     

基于FPGA的数字信号传输性能分析仪

采用FPGA设计了一种数字信号传输性能分析仪,可实现波特率步进为10Kbps的m序列发生器与曼彻斯特编码分别作为测试仪的测试信号,以及波特率为100Kbps的伪随机序列的噪声信号。将信号通过不同截止频率的滤波器构建出不同传输信道环境,信号通过该信道后在示波器上同步出信号的眼图,通过测量眼图的幅度来分析不同信道环境对信号传输的信号完整性及码间串扰的影响,以判断该该信道是否符合信号的传输要求,该分析仪采用TFT触摸屏,操作方便、显示清晰、人机交互性好。     

Topological size effect in tin-dioxide cluster films produced by reactive sputtering

The optical properties of tin-dioxide nanofilms produced by reactive sputtering are studied by the internal reflection technique and modulation polarimetry. The angular and spectral characteristics of the reflection coefficients R _s ² and R _p ² are studied for linear-polarized radiations, for which the wave electric field is, correspondingly, orthogonal and parallel to the plane of incidence. The characteristics of the physical difference between the reflection coefficients, ρ = R _s ² -R _p ² , are studied as well. From the experimental results, it follows that (i) the doping-induced finite conductivity of the film brings about the appearance of surface plasmon resonance; (ii) the shape of the spectral and angular characteristics of the parameter ρ is indicative of the cluster structure of the film, which is in agreement with the phase topology data obtained by atomic force microscopy; and (iii) the nonspherical shape of the clusters is responsible for the splitting of resonances and for the dependence of their parameters on the angle of incidence, which defines the topological size effect.     

拆分粒度对FPGA可拆分逻辑结构性能的影响

可编程逻辑块是现场可编程门阵列(FPGA)的核心组成部分(主要由查找表(LUT)和寄存器构成),它的内部结构设计一直是研究的重要方向。可拆分逻辑结构给电路实现带来了灵活性。本文以6-LUT作为研究对象,从拆分粒度的角度出发,研究不同的可拆分因子(N=1,2,3,4)对电路性能带来的影响。仿真实验基于开源的FPGA CAD工具(ABC和VPR)和VPR测试电路集,实验结果表明：a) 不同可拆分因子对电路关键路径延时影响不大;b) 可拆分因子为2时,电路使用资源的面积和面积-延时积均最小,呈现更好的性能。     

基于FPGA及LVDS的大尺寸测量系统设计

目前CCD成像物体尺寸测量系统中存在大物体尺寸测量精度低、抗干扰能力弱、控制复杂且成本高等问题;因此,设计了一种基于FPGA及 LVDS的具有抗干扰能力的大物体尺寸测量系统。该系统通过自扫描光电二极管列阵(SSPD)完成数据采集,经过A/D量化后经由LVDS芯片传输,完成信号噪声的滤除,然后由FPGA调用内部IP核对数据进行缓存,最后将数据传送到上位机进行实时显示。实验结果表明,该系统具有较强抗干扰能力、高速处理能力并且操作简单、成本低,同时实现了对大物体尺寸测量且具有较高精度。     

数据包大小对TCP流性能的影响

在互联网时代,如何提高网络通信质量一直是研究热点,当前网络通信大部分数据流都采用TCP流。对于TCP流性能的影响因素如丢包、时延已有大量研究,但是数据包大小对其的影响却罕有涉及。另一方面,网络通信的质量很大程度上取决于路由器的性能,而路由器的性能又很大程度上取决于路由器的缓存设置。因此本文从数据包大小这一新的切入点入手,研究在不同的路由器缓存下,其对TCP流性能的影响。论文介绍了TCP协议、路由器缓存、数据包等相关概念,提出了实验方案的网络拓扑模型,选择了NS2平台进行网络仿真。在实验中,我们通过改变数据包大小和路由器缓存容量,得到了对应的实验数据并进行了分析整理,总结出了TCP流吞吐量和丢包率在数据包大小改变时的变化规律,即丢包率随数据包大小的增加呈线性增长,路由器缓存越小丢包率越大;TCP流的吞吐量随数据包大小的增加缓慢变大,路由器缓存达到一定值后不再成为瓶颈因素。     

The effects of matrix organization size and number of projectassignments on performance

Peters, Waterman, and a number of popular management authors have recently offered numerous criticisms of matrix structures. This investigation empirically tests two of these critical assertions in the areas of matrix organization size and number of project assignments. The findings based on a sample of 64 high-technology firms suggest that Peters' and Waterman's conclusions are incorrect     

Modeling technology impact on cluster microprocessor performance

The growing speed gap between transistors and wire interconnects is forcing the development of distributed, or clustered, architectures. These designs partition the chip into small regions with fast intracluster communication. Longer latency is required to communicate between clusters. The hardware and/or software are responsible for scheduling instructions to clusters such that critical path communication occurs within a cluster. This paper presents GENEric SYstems Simulator (GENESYS), a technology modeling tool that captures a broad range of materials, device, circuit, and interconnect parameters across current and future semiconductor technology. This tool is used to explore the relationship between key technology parameters (intercluster wire delay and transistor switching delay) and key architecture parameters (superscalar versus multithreaded instruction dispatch, and value prediction support). GENESYS is used to predict intercluster latencies as VLSI technology advances. The study provides quantitative data showing how conventional superscalar performance is degraded with increasing wire latency. Threaded designs are more tolerant to wire delay. Optimal thread size changes with advancing VLSI technology, suggesting a highly adaptive architecture. Value prediction is shown to be useful in all cases, but provides more benefit to the multithreaded design.     

A note on density model size testing

Let (F/sub k/)/sub k/spl ges/1/ be a nested family of parametric classes of densities with finite Vapnik-Chervonenkis dimension. Let f be a probability density belonging to F/sub k//sup */, where k/sup */ is the unknown smallest integer such that f/spl isin/F/sub k/. Given a random sample X/sub 1/,...,X/sub n/ drawn from f, an integer k/sub 0//spl ges/1 and a real number /spl alpha//spl isin/(0,1), we introduce a new, simple, explicit /spl alpha/-level consistent testing procedure of the hypothesis {H/sub 0/:k/sup */=k/sub 0/} versus the alternative {H/sub 1/:k/sup *//spl ne/k/sub 0/}. Our method is inspired by the combinatorial tools developed in Devroye and Lugosi and it includes a wide range of density models, such as mixture models, neural networks, or exponential families.     

放大器估计器的查表法自适应预失真器设计

非线性功放特性随温度,供电电压等因素的变化而改变,为保证其稳定工作,预失真系统的自适应性能就显得非常重要.当前的自适应预失真算法每次都对其参数进行更新,计算量很大.针对这个问题提出了一种放大估计器的查表法自适应预失真算法,将查表法和放大器估计器法结合在一起,以误码率为指标在系统允许的误差范围内可以大大减少参数的迭代次数...