A 100-Gb/s throughput ATM switch MCM with a 320-channel paralleloptical I/O interface

For an ATM switch system, we have developed a 100-Gb/s input/output (I/O) throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25-μm complementary metal oxide semiconductors (CMOS) ATM switch large scale integrations (LSIs) and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using eight optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from dc to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface     

A 1.5 Gb/s 8×8 cross-connect switch using a time reservationalgorithm

An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8×8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s     

A 10-Gb/s optical transmitter module with a monolithicallyintegrated electroabsorption modulator with a DFB laser

A compact 10-Gb/s optical transmitter module with small-chirp output was developed by using a monolithically integrated electroabsorption modulator with a distributed-feedback laser. This module can be operated at a bit rate of more than 10 Gb/s at 1.55 μm, and shows a high modulated output power of ~1 dBm with a low optical coupling loss of 3.2 dB between chip and fiber. A multifunctional and compact optical isolator with a monitor photodiode was also developed to decrease noise     

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS

This paper describes the design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. The transmitter is fully compatible (DC coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the voltage-switching principle in order to allow different termination schemes besides the canonical ECL termination, i.e., 50-Ω toward (V_DD-2) V. The addition of some circuit techniques such as dynamic biasing and strobed current switching boosts the dynamic performance of the basic voltage-switching scheme and relaxes the requirements for a high bias current and large-size output devices at the same time. Moreover, thanks to the developed reference circuit, using both feedforward and feedback controls, the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming. The receiver cell is based on a complementary-differential architecture providing high speed and low error on the duty cycle of the CMOS output signal. The integrated receiver-transmitter chain exhibits a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission link using the developed I/O interface was tested up to 1.2 Gb/s     

Crosspoint switch equipped with an interface for serial opticalinterconnection

A crosspoint switch was developed that has an interface for serial optical interconnection. By using optoelectronic devices, cascaded switching was achieved through serial optical interconnection up to a bit rate of 10 Gb/s     

High-performance and low-consumption 10 Gb/s GaAs PHEMT driver for external modulation transmitter

This letter describes the realization of a high-performance GaAs PHEMT driver for 10 Gb/s transmitter with external coding in long haul optical transmission systems. It is shown that with an appropriate design for both IC and packaging, gain up to 14 dB, 2.5 Vp-p output drive-voltage and 1.5 W power consumption can be achieved, with adequate switching times for bit rates up to 12.5 Gb/s. The module has been successfully tested with a 18 GHz bandwidth polarization-independant pigtailed MQW electroabsorption modulator.     

A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI

This paper describes the design and implementation of a high-speed GaAs asynchronous transfer mode (ATM) mux-demux ASIC (AMDA) which is the core LSI circuit in a high-speed ATM add-drop unit (ADU). This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The ADU provides a cell-based interface between systems operating at different data rates (the high-speed interface being 2.5 Gb/s and the low-speed interface being 155/622 Mb/s), or can be used for building local high-speed switches and LANs. Self-timed first-in-first-out (FIFO) buffers are used for handling the speed gaps between domains operating at different clock rates, and a self-timed at receiver's input (STARI) interface is used at all high-speed chip-to-chip links to eliminate timing skews. A printed circuit board (PCB) with two ADUs in a distributed multiplexing-demultiplexing architecture has been developed, and the AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W in a standard 0.8 μm E/D MESFET process     

A fully implemented 12 /spl times/ 12 data vortex optical packet switching interconnection network

A fully functional optical packet switching (OPS) interconnection network based on the data vortex architecture is presented. The photonic switching fabric uniquely capitalizes on the enormous bandwidth advantage of wavelength division multiplexing (WDM) wavelength parallelism while delivering minimal packet transit latency. Utilizing semiconductor optical amplifier (SOA)-based switching nodes and conventional fiber-optic technology, the 12-port system exhibits a capacity of nearly 1 Tb/s. Optical packets containing an eight-wavelength WDM payload with 10 Gb/s per wavelength are routed successfully to all 12 ports while maintaining a bit error rate (BER) of 10/sup -12/ or better. Median port-to-port latencies of 110 ns are achieved with a distributed deflection routing network that resolves packet contention on-the-fly without the use of optical buffers and maintains the entire payload path in the optical domain.     

Optical Interconnection Platform Composed of Fiber-Embedded Board, 90$^{circ}$-Bent Fiber Block, and 10-Gb/s Optical Module

An architecture of a passively assembled optical platform is suggested for a chip-to-chip optical interconnection system. The platform is constructed using all-fiber media for the optical paths: a fiber-embedded optical printed-circuit board (OPCB) and 90-bent fiber connector. The passive assembling was achieved by employing the guide pins/holes of commercialized ferrules in the optical link between the OPCB, 90-bent fiber connector, and the transmitter/receiver (Tx/Rx) module. From this interconnection scheme, a low total optical loss of was obtained. From an assembled platform with 10 Gb/s/ch 4 ch Tx/Rx modules, a 7-Gb/s/ch data transmission was demonstrated with a bit error rate below , involving the optical and electrical crosstalk arisen in the whole channel operation.     

A photonic front-end processor in a WDM ATM multicast switch

Dense wavelength-division multiplexing (DWDM) technology has provided tremendous transmission capacity in optical fiber communications. However, switching and routing capacity is still far behind transmission capacity. This is because most of today's packet switches and routers are implemented using electronic technologies. Optical packet switches are the potential candidate to boost switching capacity to be comparable with transmission capacity. In this paper, we present a photonic asynchronous transfer mode (ATM) front-end processor that has been implemented and is to be used in an optically transparent WDM ATM multicast (3M) switch. We have successfully demonstrate the front-end processor in two different experiments. One performs cell delineation based on ITU standards and overwrites VCI/VPI optically at 2.5 Gb/s. The other performs cell synchronization, where cells from different input ports running at 2.5 Gb/s are phase-aligned in the optical domain before they are routed in the switch fabric. The resolution of alignment is achieved to the extent of 100 ps (or 1/4 bit). An integrated 1×2 Y-junction semiconductor optical amplifier (SOA) switch has been developed to facilitate the cell synchronizer     

Si-analog IC's for 20 Gb/s optical receiver

Two Si-Analog IC's, a preamplifier IC and a decision IC, for a 20 Gb/s optical receiver have been developed using SiGe-base bipolar transistors having a 60 GHz maximum cutoff frequency. The preamplifier employing a dual feedback loop increases the -3 dB bandwidth up to 19 GHz. A decision IC, composed of a gain controllable amplifier with a bias stabilization circuit and D-F/F, operated at up to 20 Gb/s with a 200-mVp-p input sensitivity     

An expandable time-division circuit switching LSI and networkarchitecture for broadband ISDN

A broadband network architecture is proposed that integrates multimedia services, such as data, video, and telephony information, using 52-Mb/s based STM-paths at the user network interface (UNI). The user can access any new service via the STM-based access network via either synchronous transfer mode (STM) switching or asynchronous transfer mode (ATM) switching. STM circuit switching supports long duration, constant bandwidth data transfer services such as video and high-definition television (HDTV) distribution and will also be used for the crossconnect system. Circuit switching can provide transparent transmission during long connection periods. This paper also proposes an expandable time-division switch architecture, an expandable time-division switching LSI, and an expandable switching module for small to large size system applications. The proposed time-division switching LSI, module, and system handle 52-Mb/s bearer signals and have throughputs of 2.4 Gb/s, 10 Gb/s, and 40 Gb/s, respectively. The time-division switch realizes video distribution with 1:n connections. Finally, a local switching node that features an expandable 52-Mb/s time-division circuit switching network is shown for multimedia access networking     

80 Gbit/s ATM switch MCM based on multilayer ceramic technology

An 80 Gbit/s asynchronous transfer mode (ATM) switch multichip module (MCM) of dimensions 114×160×6.5 mm has been fabricated. This MCM can support high-density mounting and high-speed interconnection among large-scale-integrated (LSI) chips. Using LSI, ceramic-substrate, high-speed/high-power connector, and compact liquid-cooling technologies, an 80 Gbit/s ATM switching module has been built     

Direct current to 34.1-Gb/s, 19-Gb/s/cm/sup 3/ low-jitter parallel optical interconnecting module for high-speed memory test systems

A protocol-free parallel optical interconnecting module is introduced as a solution to solve memory test system transmission bottlenecks. The optical transmission system flexibly suited for a memory test system is reviewed and discussed. A parallel optical module capable of transmitting from dc to 34.1Gb/s (4.267 Gb/s /spl times/8 ch) has been developed. A data transmission throughput density per unit volume of 19 Gb/s/cm/sup 3/ is achieved. A random jitter of less than 3-ps root-mean-square is also achieved. Furthermore, high-density optical connector, high-density optical fiber cable, fiber guides, and cable management/reinforcement members suited for mechanical requirements of the memory test system have been developed.     

An optical packet switch based on WDM technologies

Dense wavelength-division multiplexing (DWDM) technology offers tremendous transmission capacity in optical fiber communications. However, switching and routing capacity lags behind the transmission capacity, since most of today's packet switches and routers are implemented using slower electronic components. Optical packet switches are one of the potential candidates to improve switching capacity to be comparable with optical transmission capacity. In this paper, we present an optically transparent asynchronous transfer mode (OPATM) switch that consists of a photonic front-end processor and a WDM switching fabric. A WDM loop memory is deployed as a multiported shared memory in the switching fabric. The photonic front-end processor performs the cell delineation, VPI/VCI overwriting, and cell synchronization functions in the optical domain under the control of electronic signals. The WDM switching fabric stores and forwards cells from each input port to one or more specific output ports determined by the electronic route controller. We have demonstrated with experiments the functions and capabilities of the front-end processor and the switching fabric at the header-processing rate of 2.5 Gb/s. Other than ATM, the switching architecture can be easily modified to apply to other types of fixed-length payload formats with different bit rates. Using this kind of photonic switch to route information, an optical network has the advantages of bit rate, wavelength, and signal-format transparencies. Within the transparency distance, the network is capable of handling a widely heterogeneous mix of traffic, including even analog signals.     

2.5Gb/s 16:1MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for optical fiber communication based on TSMC 0.25 μm CMOS technology is presented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8 mm2.     

Deep-submicron HEMT technology

The current status of HEMT technology and its impact on computers and communications are presented, focusing on the advantages of the device in the deep-submicrometre dimensional range, self-aligned HEMT processing, and the HEMT LSI implemented in supercomputer and communication systems.

Ultra-low-noise HEMTs are already commercially available in satellite communications, and have made a great impact in expanding the broadcasting satellite market. For ultra-high-speed digital LSI applications the 1 k gate bus-driver logic LSI has been developed to demonstrate high-speed data transfer in a high-speed parallel processing supercomputer system at room temperature, operating at 10·92 Gflops. The 7 k gate asynchronous transfer mode (ATM) switch LSI has alsi been developed to evaluate high-speed data switching for Broadband Integrated Service Digital Network (B-ISDN). The maximum operation frequency was 1·2 GHz at room temperature. The single-chip throughput was 9·6 Gb/s and a throughput of 38·4 Gb/s was achieved in a 4 × 4 ATM switching module.     

A 4 Gb/s 2-level to 2 Gsymbol/s 4-level converter GaAs IC forsemiconductor optical amplifier QPSK modulators

The design of a 50 Ω impedance matched two-to-four level converter GaAs IC for two-electrode semiconductor optical amplifier (SOA) modulators is presented. The designed IC exhibits eye diagrams with eye openings of better than 0.30 V and a spacing between adjacent output signal levels of 0.33 V for output symbol rates of up to 2 Gsymbol/s corresponding to input bit rates of up to 4 Gb/s. A novel differential super buffer output driver is applied, for which output reflection coefficients |S₂₂| of less than -12 dB for frequencies up to 10 GHz are obtained. A 1 Gb/s optical QPSK microwave link transmission experiment using a packaged sample of the designed IC and a two-electrode semiconductor optical amplifier phase modulator has been conducted     

LSI Processor for Digital Signal Processing and Its Application to 4800 Bit/s Modem

This paper describes a fast data processing LSI unit tailored to the digital signal processing (DSP) applications in the field of electrical communications. The results of successful application to the 4800 bit/s modem are also given. The LSI processor discussed here adopts a firmware control scheme to enhance the flexibility and freedom of application and extensively utilizes the pipeline processing technique to attain high speed data handling capability. The various operations encountered in DSP systems are unified into one operation of the typeA times B + C rightarrow Dand the LSI processor is designed to continuously perform this operation, while the data to be operated are transferred sequentially into the processor controlled by exterior firmware. The developed LSI handles 8 bit data at the clock frequency of 1.152 MHz and manages 144 K operations per second (6.9 μs cycle time). The LSI is an N-MOS chip containing 1500 gates and packaged in a 40 pin DIP. The automatic equalizer for 4800 bit/s modem was implemented using two of the developed LSI processors and about 4 K ROM and 1 K RAM memory chips. The measurement on this modem gave the error rate of 10^-5atS/N = 17.6dB and error free phase jitter allowance of 55° p-p. Application of the LSI processor to digital filters for roll-off spectrum shaping and timing signal extraction is also described.