700V VDMOS终端结构优化设计

基于垂直双扩散金属氧化物(VDMOS)场效应晶体管终端场限环(FLR)与场板(FP)理论,在场限环上依次添加金属场板与多晶硅场板,并通过软件仿真对其进行参数优化,最终实现了一款700 V VDMOS终端结构的优化设计。对比场限环终端结构,金属场板与多晶硅复合场板的终端结构,能够更加有效地降低表面电场峰值,增强环间耐压能力,从而减少场限环个数并增大终端击穿电压。终端有效长度仅为145μm,击穿电压能够达到855.0 V,表面电场最大值为2.0×105V/cm,且分布比较均匀,终端稳定性和可靠性高。此外,没有增加额外掩膜和其他工艺步骤,工艺兼容性好,易于实现。     

6500 V SiC场限环终端设计与实现

针对6 500 V SiC器件的阻断电压要求,采用有限元仿真软件对场限环终端结构进行了设计优化。相比于通常的恒定环间距增量场限环终端设计,本项研究采用三段不同的环间距增量终端环结构。该结构场限环终端的优势在于SiC器件表面的峰值电场强度控制在1MV/cm以下,体内的峰值电场强度在2.4MV/cm以下,有效减小了实际工艺中环注入窗口的工艺偏差引起的环间距拉偏对峰值电场强度的影响。环间距拉偏结果显示,在-0.2~+0.2μm的偏差范围内,器件表面(SiO_2/SiC交界处)的峰值电场强度并没有升高,只是峰值的位置发生了改变。最后利用了所设计的场限环终端进行了实际流片。测试结果显示,当施加6 500V的反向电压,漏电流小于10μA。     

高压IGBT线性变窄场限环终端设计

为使3300 V及以上电压等级绝缘栅双极型晶体管(IGBT)的工作结温达到150℃以上,设计了一种具有高结终端效率、结构简单且工艺可实现的线性变窄场限环(LNFLR)终端结构。采用TCAD软件对这种终端结构的击穿电压、电场分布和击穿电流等进行了仿真,调整环宽、环间距及线性变窄的公差值等结构参数以获得最优的电场分布,重点对比了高环掺杂浓度和低环掺杂浓度两种情况下LNFLR终端的阻断特性。仿真结果表明,低环掺杂浓度的LNFLR终端具有更高的击穿电压。进一步通过折中击穿电压和终端宽度,采用LNFLR终端的3300 V IGBT器件可以实现4500 V以上的终端耐压,而终端宽度只有700μm,相对于标准的场限环场板(FLRFP)终端缩小了50%。     

一种500V终端结构的设计与优化

设计了一个500 V纯场限环终端结构.在保证击穿电压的前提下,为了尽可能减小终端结构所占的芯片面积,适当调整场限环终端的结构参数,添加金属场板,形成场限环-场板联合边端结构,界面态电荷对器件性能的影响也得到改善.采用场限环-场板结构的终端,实现了539 V的击穿电压,并缩短了17.2μm的边端宽度,相应节省了14％的宽度.     

一种新型高压功率器件终端技术

为了改善高压功率器件的击穿电压、节省芯片面积,提出一种P-场限环结合P+补偿结构、同时与金属偏移场板技术相结合的高压终端技术.采用TCAD(ISE)时该技术进行模拟,结果表明,该技术具有比较好的面积优化和击穿电压优化特性.     

PDP扫描驱动芯片中高压VDMOS器件的设计

PDP扫描驱动芯片完成高低压转换和功率输出,要求器件耐压170v.本文基于BCD工艺,提出了高压器件VDMOS的结构,采用了不附加工艺的场板和场限环两种终端结构提高器件耐压,并利用器件模拟软件MEDICI进行了仿真验证,得到了优化的器件结构参数.     

一种沟槽型场限环VDMOSFET终端结构

场限环结构以其简单的工艺和较高的效率,在垂直双扩散金属氧化物场效应晶体管终端结构中得到广泛应用,但其性能的提高也有限制。沟槽型终端结构对刻蚀工艺要求较高,并未在实际生产中得到大量应用。将场限环终端结构与沟槽终端结构相结合,设计了一种沟槽型场限环终端,在149.7 μm的有效终端长度上实现了708 V的仿真击穿电压。此结构可以得到较大的结深,硅体内部高电场区距离表面较远,硅表面电场仅为1.83E5 V/cm,具有较高的可靠性。同时,工艺中只增加了沟槽刻蚀和斜离子里注入,没有增加额外的掩膜。     

一种新型的用浮空场限环实现的可集成在SPIC中的高压电压探测器*

提出一种可以集成在SPIC(智能功率集成电路)内部的高压电压探测器的方法,其理论是基于基本的结终端技术中的浮空场限环系统,把场限环系统作为表面电压分压器.在通常的场限环外侧再增加两个环,对外侧环电压再一次分压,并把最外侧环设计成高压电压探测器.这样当主结电压上升到一个高压时,最外侧的环可以只有几伏到十几伏的变化,这样环(探测器)上的信号既可以表征主结高电压,又可以由低压逻辑电路处理.以一个400V的结构为例,分析并模拟了这个结构.结果证明可以有效探测SPIC的高压并可以集成在SPIC中.同时,该结构可以与CMOS和BCD工艺兼容,且工艺上也不会增加步骤.     

一种高压功率器件场板技术的改进与设计

为了解决功率器件高击穿电压与减小表面最大电场需求之间的矛盾,提出了一种高压功率器件终端场板改进方法。通过调节金属场板和多晶硅场板的长度,使金属场板覆盖住多晶硅场板,最终使得两者的场强相互削弱,从而减小表面最大电场。采用TCAD(ISE)软件对该结构进行仿真验证,结果表明该结构能够在保证高耐压的前提下减小表面最大电场。基于所提方法,设计出了一种七个场限环的VDMOSFET终端结构,其耐压达到了893.4 V,表面最大电场强度只有2.16×10⁵ V/cm,提高了终端的可靠性。     

高压功率FRED结终端保护技术及其组合优化设计

场板与场限环是用来提高功率FRED抗电压击穿能力的常用终端保护技术,本文分别介绍场板与场限环结终端结构原理和耐压敏感参数,然后采取场板和场限环的互补组合,通过Synopsis公司MEDICI4.0仿真工具优化设一款耐压1200V的FERD器件终端结构,最后通过实际流片验证此终端结构具有良好的电压重复性及一致性。     

Low-voltage mercury-alkali metal arc

Measurements of the arc voltage and electron temperature were made on low-pressure arcs utilizing a mercury-pool cathode containing various concentrations of alkali metals. The arc-burning voltage was substantially lower than the pure mercury arc and the minimum arc voltage depended on the concentration of the alkali metal and ambient tube temperature. The measurements suggest that there are three processes which collectively are responsible for the arc behavior. These are a lower anode work function, a Penning two-stage ionization process of alkali metal atoms by mercury metastables and an improved electron emission by reliable anchoring of the cathode spot. With the addition of small amounts of alkali metal the cathode spot emission zone was stable on a molybdenum anchor at currents as high as 200 a. The cathode fall potential was the order of 4 v. It is shown that the voltage reduction is mainly in the cathode fall region and that it is lower for rubidium than cesium, potassium or sodium in the preceding order.     

A 30 V Self-Aligned Metal/Poly-Si Replacement Gate Planar DMOS for DC/DC Converters

In this letter, a novel self-aligned metal/poly-Si gate planar double-diffused MOS (DMOS) is proposed and demonstrated for high-switching-speed and high-efficiency dc/dc converter applications. The self-aligned metal/poly-Si gate is realized by a replacement gate technology. The fabricated metal/poly-Si gate planar DMOS has a breakdown voltage of 36 V and a threshold voltage of 2.1 V. The gate sheet resistance of the metal/poly-Si gate is around 0.2 Omega/square, which is 50 times lower than that of the polysilicon gate. The low sheet resistance reduces the switching time as well as the power loss of the device during switching. For a device with a drain current of 69 A/cm², the turn-on and turn-off times are reduced from 29 to 25 ns and from 36 to 31 ns, respectively. The turn-on and turn-off switching energy losses are reduced by 22% and 15%, respectively     

干法测量电子元件引线的可焊性

针对传统方法检测电子元件引线可焊性的缺点,提出了一种干法测量方法.电子元件引线镀层表面的金属氧化物是影响可焊性的主要因素,金属氧化物具有介于绝缘体和半导体之间的物理特性,它的击穿电压和氧化程度成正相关的关系.实验证明:击穿电压低于3V时,焊接性能很好,随着击穿电压升高,焊接性能恶化,超过40V,完全丧失可焊性.因此可以...     

GIS金属法兰孔处的VFTO测量系统设计

内置式VFTO的测量传感器体积大、安装困难,不适用于在运的特高压GIS。针对以上缺陷,文中设计了一种适用于GIS金属法兰孔处的VFTO测量系统。该系统采用FPC电容分压与二次阻容分压器结合的方案,实现了GIS外置小型化的VFTO测量。根据金属法兰孔的尺寸及测量系统的性能要求,对FPC进行结构、尺寸设计,研制了电容分压探头。为改善测量系统的性能,设计了宽频阻容分压器,并通过实测的方式对匹配电阻与同轴电缆的参数进行优化。试验结果表明,VFTO测量系统的带宽为22.45 Hz~111.45 MHz,分压比为112 790,可以准确溯源波形,满足VFTO测量要求。     

一种有机薄膜器件的制备及电存储特性

研究了一种金属/有机物/金属夹层结构有机薄膜器件的可逆电双稳特性.器件的阳极和阴极分别为真空热蒸发沉积的Ag和Al薄膜,中间介质层为真空热蒸发沉积的2-(hexahydropyrimidin-2-ylidene)-malononitrile(HPYM)有机薄膜.器件起始状态为非导通态,在大气环境下,可用正、反向电场进行信号的写入和擦除,表现为极性记忆特性.通过自然氧化的方法在底电极Al表面形成一层Al2O3薄膜层后,可使器件在不同的正向电压脉冲作用下达到不同的导电态,具有一定的多重态存储特性.同时,研究了不同的电极组合对器件电性能的影响,并通过紫外-可见吸收光谱以及喇曼光谱对器件界面进行表征.     

Improvement of threshold voltage deviation in damascene metal gatetransistors

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (ΔV _th) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, ΔV_th of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (ΔV_th) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta₂O₅ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN     

An advanced MOS-IC process technology using local oxidation ot oxygen-doped polysilicon films

An O-POS (oxygen-doped polysilicon) film, deposited directly on silicon, is oxidized locally to create an active gate area. The electrical properties for the active gate area are the same as conventional p- and n-channel MOS devices, but the field area has an extremely high threshold voltage for both p- and n-type silicon substrates. The electrical properties in metal/oxidized O-POS/silicon and metal/oxide/O-POS/silicon structures have been investigated while varying the O-POS film thickness, oxygen concentration, local oxidation time, and silicon substrate resistivity. According to these basic studies, it is proposed that the high density of trapping centers existing in O-POS film is responsible for the high field threshold voltage. A applications of this process technology, a silicon-gate CMOS integrated circuit, and a high voltage n-channel MOS device are discussed.     

Control of threshold voltage of AlGaAs/GaAs 2DEG FET's through heat treatment

Threshold voltage controls of Ni/Ti/Au gate and Ti/Au gate 2DEG AlGaAs/GaAs FET's through only heat treatment are investigated. Ni/Ti/Au gate FET's vary over quite a wide range from a depletion mode to an enhancement mode without degradation of FET characteristics after heat treatment at 300°C. The same experiment is made for Ti/Au gate FET's, but the threshold voltage change is negligibly small. It is confirmed that Ni/Ti/Au can be used as the gate metal for E-FET and Ti/Au as the gate metal for D-FET under simultaneous heat treatment. In addition, a mechanism for penetrating the barrier metal into the underlying layer is discussed.     

Electrical observation of deep traps in high-/spl kappa//metal gate stack transistors

The instability of threshold voltage in high-/spl kappa//metal gate devices is studied with a focus on the separation of reversible charge trapping from other phenomena that may contribute to time dependence of the threshold voltage during a constant voltage stress. Data on the stress cycles of opposite polarity on both pMOS and nMOS transistor suggests that trapping/detrapping at the deep bandgap states contributes to threshold voltage instability in the pMOS devices. It is found that under the same electric field stress conditions, threshold voltage changes in pMOS and nMOS devices are nearly identical.     

Power distribution techniques for VLSI circuits

The onchip power distribution problem for highly scaled technologies is investigated. Metal migration and line resistance problems as well as ways to optimize multilayer metal technology for low resistance, low current density, and maximum wirability are also investigated. Fundamental lower limits and the limiting factors of the power-line current density and the voltage drop are studied. Tradeoffs between interconnect wirability and power distribution space are examined. Power routing schemes, as well as the optical number of metal layers and the optimal thickness of each layer, are examined. The results indicate that orders of magnitude improvements in current density and resistive voltage drop can be achieved using very few layers of thick metal whose thicknesses increase rapidly in ascending layers. Also, using the upper layers for power distribution and lower layers for signal routing results in the most wire length available for signal routing.