双栅双应变沟道全耗尽SOI MOSFETs的特性分析

提出了一种全新的器件结构--双栅双应变沟道全耗尽SOI MOSFETs,模拟了沟道长度为25nm时器件的电学特性.工作在单栅模式下,应变沟道(Ge=0.3)驱动能力与体Si沟道相比,nMOS提高了43%,pMOS提高了67%;工作在双栅模式下,应变沟道(Ge=0.3)与体Si沟道相比较,驱动电流的提高nMOS为31%,pMOS为60%.仿真结果表明,双栅模式比单栅模式有更为陡直的亚阈值斜率,更高的跨导以及更强的抑制短沟道效应的能力.综合国内外相关报道,该结构可以在现今工艺条件下实现.     

A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs

In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed     

双栅双应变沟道全耗尽SOI MOSFETs的特性分析

提出了一种全新的器件结构--双栅双应变沟道全耗尽SOI MOSFETs,模拟了沟道长度为25nm时器件的电学特性.工作在单栅模式下,应变沟道(Ge=0.3)驱动能力与体Si沟道相比,nMOS提高了43%,pMOS提高了67%;工作在双栅模式下,应变沟道(Ge=0.3)与体Si沟道相比较,驱动电流的提高nMOS为31%,pMOS为60%.仿真结果表明,双栅模式比单栅模式有更为陡直的亚阈值斜率,更高的跨导以及更强的抑制短沟道效应的能力.综合国内外相关报道,该结构可以在现今工艺条件下实现.     

Low-Field Electron Mobility Model for Ultrathin-Body SOI and Double-Gate MOSFETs With Extremely Small Silicon Thicknesses

A number of experiments have recently appeared in the literature that extensively investigate the silicon-thickness dependence of the low-field carrier mobility in ultrathin-body silicon-on-insulator (SOI) MOSFETs. The aim of this paper is to develop a compact model, suited for implementation in device- simulation tools, which accurately predicts the low-field mobility in SOI single- and double-gate MOSFETs with Si thicknesses down to 2.48 nm. Such a model is still missing in the literature, despite its importance to predict the performance of present and future devices based on ultrathin silicon layers.     

Band-Structure Effects on the Performance of III–V Ultrathin-Body SOI MOSFETs

This paper examines the impact of band structure on deeply scaled III-V devices by using a self-consistent 20-band -SO semiempirical atomistic tight-binding model. The density of states and the ballistic transport for both GaAs and InAs ultrathin-body n-MOSFETs are calculated and compared with the commonly used bulk effective mass approximation, including all the valleys (, , and ). Our results show that for III-V semiconductors under strong quantum confinement, the conduction band nonparabolicity affects the confinement effective masses and, therefore, changes the relative importance of different valleys. A parabolic effective mass model with bulk effective masses fails to capture these effects and leads to significant errors, and therefore, a rigorous treatment of the full band structure is required.     

Simulation of the Characteristics of Double-Gate Asymmetrically Doped SOI CMOS Nanotransistors

The problems of modeling the basic electrophysical characteristics of asymmetrically doped double- gate SOI CMOS nanotransistors are discussed. A mathematical model for the distribution of the potential of the working region, which follows from the analytic solution of the 2D Poisson equation is treated. The variant of the asymmetric channel (counting from the source) with highly doped and low-doped regions is analyzed. The results of the model calculations of the potential distribution of sub-50-nm structures are in good agreement with the simulation data obtained using a commercially available ATLAS^TM software package intended for modeling 2D transistor structures. Based on the obtained potential distributions, the current–voltage performances are calculated using the model of current formulated within the charge separation concept, taking into account the modified expression for the saturation rate. For the topological norms chosen, the optimization of the parameters of an asymmetrically doped profile provides an additional opportunity to monitor the key characteristics along with the thicknesses of the working region and the gate oxide, which is important in analyzing the applicability of nanotransistor structures, in particular, for analog applications.     

Numerical and charge sheet models for thin-film SOI MOSFETs

Numerical charge sheet models applicable for all bias conditions are presented for the channel currents of long-channel SOI MOSFETs. From a comparison of the two models it is shown that the charge sheet analytic model accurately predicts the channel currents from weak to strong inversion regions. The results include analytic expressions for the drift and diffusion current components of individual channel currents, the front-gate and back-gate interaction parameter, and an analytic correlation between the surface potentials of the front and back channels when there is coupling between the two gates under nonthermal equilibrium conditions. The effect of SOI (silicon on insulator) film thickness on the drain current was investigated under different bias conditions for the back gate, and it was found that thin films are beneficial from the point of increased drain currents if the back channel is in depletion or inversion. It is also shown that, in addition to the charge coupling effects, dynamic interaction between the channels exists if the static current in one of the channels saturates     

SOI高压MOSFET的电流-电压特性模拟

在不同漂移区浓度分布下 ,通过二维数值模拟充分地研究了薄膜 SOI高压 MOSFET击穿电压的浓度相关性 ,指出了击穿优化对 MOSFET漂移区杂质浓度分布的要求。分析了MOSFET的电场电位分布随漏源电压的变化 ,提出寄生晶体管击穿有使 SOI MOSFET击穿降低的作用。     

An Improvement to the Numerical Robustness of the Surface Potential Approximation for Double-Gate MOSFETs

In developing the drain current model of a symmetric double-gate MOSFET, one encounters a transcendental equation relating the value of an intermediate variable $beta$ to the gate and drain voltages. In this brief, we present an enhancement to an existing approximation for $beta$, which improves its numerical robustness. We also benchmark our suggested enhancement and show that our enhancement is as computationally efficient as the original approximation but is numerically much more robust, with an accuracy that is comparable to the original approximation.      

双栅双应变沟道全耗尽SOI CMOS的瞬态特性分析

在提出双栅双应变沟道全耗尽SOl MOSFET新结构的基础上,模拟了沟道长度为25nm时基于新结构的CMOS瞬态特性.结果表明,单栅工作模式下,传统应变SiGe(或应变Si)器件的CMOS电路只能实现上升(或下降)时间的改善,而基于新结构的CMOS电路能同时实现上升和下降时间的缩短;双栅模式下,CMOS电路的上升和下降时间较单栅模式有了更进一步的改善,电路性能得以显著提高.     

A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETs

The performance of symmetric double-gate MOSFETs with dopant-segregated Schottky (DSS) source/drain (S/D) regions is investigated through a TCAD modeling study and compared to the performance of raised S/D (RSD) MOSFETs. It is shown that, while the doped extension region adjacent to the S/D Schottky barrier (SB) improves drive current by shrinking the SB, it is fundamentally limited by its dual role as a heavily doped S/D contact region to improve drive current and as a more lightly doped S/D extension region to reduce BTBT leakage. This restricts the design space for meeting low-standby-power leakage specifications, and so, the RSD structure ends up prevailing both in terms of leakage design space and on-state performance. For high-performance (HP) design, where the higher leakage specification permits heavier extension doping, the performances of optimized DSS and RSD MOSFETs are shown to be very similar. Thus, the optimal S/D design for HP is more likely to be decided by practical considerations such as process integration.     

双栅双应变沟道全耗尽SOI CMOS的瞬态特性分析

在提出双栅双应变沟道全耗尽SOl MOSFET新结构的基础上,模拟了沟道长度为25nm时基于新结构的CMOS瞬态特性.结果表明,单栅工作模式下,传统应变SiGe(或应变Si)器件的CMOS电路只能实现上升(或下降)时间的改善,而基于新结构的CMOS电路能同时实现上升和下降时间的缩短;双栅模式下,CMOS电路的上升和下降时间较单栅模式有了更进一步的改善,电路性能得以显著提高.     

Explicit Analytical Charge and Capacitance Models of Undoped Double-Gate MOSFETs

An analytical, explicit, and continuous-charge model for undoped symmetrical double-gate (DG) MOSFETs is presented. This charge model allows obtaining analytical expressions of all total capacitances. The model is based on a unified-charge-control model derived from Poisson's equation and is valid from below to well above threshold, showing a smooth transition between the different regimes. The drain current, charge, and capacitances are written as continuous explicit functions of the applied bias. We obtained very good agreement between the calculated capacitance characteristics and 2-D numerical device simulations, for different silicon film thicknesses.     

Measurement of substrate current in SOI MOSFETs

A new “Quasi-SOI” MOSFET structure is shown to allow direct measurement of substrate current in a fully-depleted SOI device. The holes generated by impact ionization near the drain are collected at the substrate terminal after they have traversed the source-body barrier and caused bipolar multiplication. By monitoring this hole current, direct characterization of the impact-ionization multiplication factor, M, and the parasitic bipolar gain, β, was performed. It was found that M-1 increases exponentially with V_DS and decreases with V_GS, exhibiting a drain field dependence. The bipolar gain β was found to be as high as 1000 for V_GS-V_T=0 V and V_DS=-2.5 V, but decreases exponentially as V_DS increases. Finally, it was found that β also decreases as V_GS increases     

Monte Carlo Simulation of Nanoscale SOI MOSFETs

A comparative review is presented of the current research on the quantum-mechanical and classical Monte Carlo simulation of SOI MOSFETs. A quantum-mechanical simulation method is proposed whereby the energy of transverse channel quantization is represented by a correction term. A newly developed simulation program, called BALSOI, is outlined. A comparison is made between the results of a 2D classical Monte Carlo simulation and those obtained by the quantum-mechanical method. It is observed that the differences are much smaller than what one might expect. This finding is explained as due to the considerable effect of the space charge, which is mainly governed by the classical, longitudinal motion of carriers through the channel. An analytical formula is derived for the effect of channel quantization on the gate–channel capacitance. The strength of tunneling current through a short-channel transistor in the off state is considered.     

Comparative analysis of SOI and GOI MOSFETs

In this paper, the authors use a full-band particle-based simulator based on the cellular Monte Carlo method to investigate and compare the performance of silicon-on-insulator (SOI) and germanium-on-insulator (GOI) technologies. To this end, p-type GOI and SOI MOSFETs of effective gate lengths ranging from 30 to 110 nm are simulated, and their static and dynamic characteristics are analyzed through simulations. The transconductance, channel conductance, current-voltage (I-V) characteristics, and cutoff frequencies are extracted from the simulation results. The results indicate that drive currents are enhanced up to 25% by replacing Si with Ge. The enhancement is not as significant with respect to the unity gain frequency, which is only increased by 13% in the case of a 50-nm MOSFET. Additionally, the I-V characteristics indicate that GOI MOSFETs are more sensitive to impact ionization than their SOI counterparts, and that the channel conductance is degraded.     

新型多栅全耗尽SOI器件研究进展

随着器件尺寸的不断缩小,对更大驱动电流和更有效抑制短沟道效应器件的研制成为研究的热点,SOI多栅全耗尽器件由于对沟道更好控制能力能够有效地解决尺寸缩小带来的短沟道效应问题[1].本文主要介绍SOI/MOSFET单栅、平面双栅、FinFET、三栅、环绕栅、G4-FET等新型多栅全耗尽SOI器件的研究进展.     

基于摄动法研究短沟道SOI MOSFET亚阈值特性

提出了一种新的方法对短沟道SOI MOSFETs亚阈区的二维表面势的解析模型进行了改进,即摄动法.由于在短沟道SOI MOSFETs中不仅需要计及不可动的电离杂质,而且需要考虑自由载流子的数量和分布的影响.利用摄动法求解非线性泊松方程可以得到短沟道SOI MOSFETs二维的表面势解析模型.通过与二维数值模拟器MEDICI模拟结果比较,证明了在亚阈区改进模型所得的结果比只计及不可动的电离杂质的SOI MOSFETs模型所得的结果吻合更好.     

Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs[MESFETs read MOSFETs]

A hybrid mode of device operation, in which both bipolar and MOSFET currents flow simultaneously, has been experimentally investigated using quarter-micrometer-channel-length MOSFET's which were fabricated on SIMOX silicon-on-insulator substrates. This mode of device operation is achieved by connecting the gate of a non-fully-depleted SOI MOSFET to the edges of its floating body. Both the maximum G _m and current drive at 1.5× higher than the MOSFET's normal mode. Bipolar-junction-transistor (BJT)-like 60-mV/decade turn-off behavior is also achieved. This mode of operation is very promising for low-voltage, low-power, very-high-speed logic as well as for on-chip analog functions     

Analytical modelling of ultra-thin film depletion-mode SOI MOSFETs

Reliable analytical models for thin and ultra-thin film depletion-mode SOI MOSFETs have been developed. These models are based on the linearly varying potential (LVP) approximation in the Si film. They allow the understanding and optimization of electrical properties of these devices. In particular, the behaviour of the subthreshold swing and the transconductance is discussed and compared successfully with numerical simulation.