Influence of oxidation temperature on the microstructure and electrical properties of Ta2O5 on Si

The effect of the oxidation temperature (673-873 K) on the microstructural and electrical properties of thermal Ta₂O₅ thin films on Si has been studied. Auger electron spectroscopy and X-ray photoelectron spectroscopy results revealed that the films are non-stoichiometric in the depth; an interfacial transition layer between tantalum oxide and Si substrate, containing presumably SiO₂ was detected. It has been found by X-ray diffraction that the amorphous state of Ta₂O₅ depends on both the oxidation temperature and the thickness of the films—the combination of high oxidation temperature (>823 K) and thickness smaller than 50 nm is critical for the appearance of a crystal phase. The Ta₂O₅ layers crystallize to the monoclinic phase and the temperature of the phase transition is between 773 and 823 K for the thinner layers (<50 nm) and very close to 873 K for the thicker ones. The electrical characterization (current/voltage; capacitance/voltage) reveals that the optimal oxidation temperature for achieving the highest dielectric constant (∼32) and the lowest leakage current (10⁻⁸ A/cm² at 1 MV/cm applied field) is 873 K. The results imply that the poor oxidation related defects are rather the dominant factor in the leakage current than the crystallization effects.     

Investigation of Ta2O5/SiO2/4H-SiC MIS capacitors

Tantalum pentoxide (Ta₂O₅) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta₂O₅ of around 4.3 eV, resulting in a small band offset between the 4H-SiC and Ta₂O₅. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta₂O₅ and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta₂O₅ at 900 °C in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta₂O₅/SiO₂/4H-SiC capacitors.     

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

Interaction of Hf_xTa_yN metal gate with SiO₂ and HfO_xN_y gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO₂ gate dielectric and Hf_xTa_yN metal gate shows satisfactory thermal stability. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO₂ gate dielectric than that in HfO_xN_y. Compared to HfO_xN_y gate dielectric, SiO₂ shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flat-band voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO₂ gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.     

Effect of Rapid Thermal Annealing on Sputtered CaCu<Subscript>3</Subscript>Ti<Subscript>4</Subscript>O<Subscript>12</Subscript> Thin Films

Calcium copper titanium oxide (CaCu₃Ti₄O₁₂, abbreviated to CCTO) films were deposited on Pt/Ti/SiO₂/Si substrates at room temperature (RT) by radiofrequency magnetron sputtering. As-deposited CCTO films were treated by rapid thermal annealing (RTA) at various temperatures and in various atmospheres. X-ray diffraction patterns and scanning electron microscope (SEM) images demonstrated that the crystalline structures and surface morphologies of CCTO thin films were sensitive to the annealing temperature and ambient atmosphere. Polycrystalline CCTO films could be obtained when the annealing temperature was 700°C in air, and the grain size increased signifi- cantly with annealing in O₂. The 0.8-μm CCTO thin film that was deposited at RT for 2 h and then annealed at 700°C in O₂ exhibited a high dielectric constant (ε′) of 410, a dielectric loss (tan δ) of 0.17 (at 10 kHz), and a leakage current density (J) of 1.28 × 10⁻⁵ A/cm² (at 25 kV/cm).     

Effect of thermal oxide on the crystallization of the anodic Ta2O5 film

SEM and TEM investigations of the crystallization process have been performed on amorphous Ta₂O₅ films grown by electrochemical oxidation of Ta foils. It was found that kinetics of crystallization and final structure of the anodic Ta₂O₅ film depend strongly on the thickness of the thermal oxide layer on the surface of the original Ta substrate. Two different modes of crystallization were detected for the substrate with native surface oxide and with the thermal oxide grown at elevated temperatures. Aborting of the crystallization was shown to be possible using short heating of the Ta₂O₅/Ta san dwiches which cuts crystalline inclusions grown into the amorphous matrix of the anodic Ta₂O₅ film from the Ta surface.     

Dependence of electrical properties on interfacial layer of Ta2O5 films

The change in the thickness and chemical states of the interfacial layer and the related electrical properties in Ta₂O₅ films with different annealing temperatures were investigated. The high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy analyses revealed that the 700 °C-annealed Ta₂O₅ film remained to be amorphous and had the thinnest interfacial layer which was caused by Ta-silicate decomposition to Ta₂O₅ and SiO₂. In addition, the electrical properties were improved after annealing treatments. Our results suggest that an annealing treatment at 700 °C results in the highest capacitance and the lowest leakage current in Ta₂O₅ films due to the thinnest interfacial layer and non-crystallization.     

Effects of excess Bi concentration, buffered Bi2O3 layer, and Ta doping on the orientation and ferroelectricity of chemical-solution-deposited Bi3.25La0.75Ti3O12 films

Effects of excess Bi concentration, buffered Bi₂O₃ layer, and Ta doping on the orientation and ferroelectricity of chemical-solution-deposited (CSD) Bi_3.25La_0.75Ti₃O₁₂ (BLT) films on Pt/SiO₂/Si(100) were studied. The optimum concentration of excess Bi added to the BLT films to achieve a larger remanent polarization (2Pr) was 10 mol.%. The buffered Bi₂O₃ layers could reduce the temperature for c-axis-oriented growth of BLT films from 850°C to 700°C. However, two-step annealing, i.e., first annealed at 650°C and then annealed at a temperature of 700–850°C, could effectively suppress the c-axis-oriented growth and thus improve the 2Pr of BLT films. The improvement of the 2Pr of BLT films can be explained in terms of the large polarization along the a-axis orientation and buffered Bi₂O₃ layers, which compensate the BLT films for Bi evaporation during annealing. The Ta doping can induce two contrary effects on the 2Pr of BLT films. For the (Bi_3.25La_0.75)(Ti_3−xTa_x)O₁₂ (BLTTx) films with x=0.005, the effect of a decrease of oxygen vacancies would be dominant, resulting in the improvement of 2Pr. Because the Ta concentration (x) in the BLTTx films exceeds 0.01, the effect of a decrease of grain size would become dominant, resulting in the degradation of 2Pr.     

High-k HfO2-Ta2O5 mixed layers: Electrical characteristics and mechanisms of conductivity

Electrical properties of mixed HfO₂-Ta₂O₅ films (10;15 nm) deposited by rf sputtering on Si have been studied from the view point of their applications as high-k layers, by standard capacitance-voltage and temperature dependent current-voltage characteristics. The effect of HfO₂ addition to the Ta₂O₅ is thickness dependent and the thicker layers exhibit advantages over the pure Ta₂O₅ (higher dielectric constant, enhanced charge storage density and improved interface quality). The process of HfO₂ and Ta₂O₅ mixing introduces negative oxide charge, tends to creates shallow bulk traps and modifies the dominant conduction mechanisms in the stack capacitors as compared to the Ta₂O₅-based one (a contribution of tunneling processes through traps located below the conduction band of mixed layers to the leakage current in the HfO₂-Ta₂O₅ stacks is observed). The traps involved in both Poole-Frenkel and tunneling processes are identified.     

Annealing effect on physical and electrical characteristics of thin HfO2, HfSixOy and HfOyNz films on Si

We report the effect of annealing on electrical and physical characteristics of HfO₂, HfSi_xO_y and HfO_yN_z gate oxide films on Si. Having the largest thickness change of 0.3 nm after post deposition annealing (PDA), HfO_yN_z shows the lowest leakage current. It was found for both as-grown and annealed structures that Poole-Frenkel conduction is dominant at low field while Fowler-Nordheim tunneling in high field. Spectroscopic ellipsometry measurement revealed that the PDA process decreases the bandgap of the dielectric layers. We found that a decreasing of peak intensity in the middle HfO_yN_z layer as measured by Tof-SIMS may suggest the movement of N toward the interface region between the HfO_yN_z layer and the Si substrate during the annealing process.     

Structural and electrical properties of radio frequency magnetron sputtered tantalum oxide films: Influence of post-deposition annealing

The as-deposited and annealed radio frequency reactive magnetron sputtered tantalum oxide (Ta₂O₅) films were characterized by studying the chemical binding configuration, structural and electrical properties. X-ray photoelectron spectroscopy and X-ray diffraction analysis of the films elucidate that the film annealed at 673 K was stoichiometric with orthorhombic β-phase Ta₂O₅. The dielectric constant values of the tantalum oxide capacitors with the sandwich structure of Al/Ta₂O₅/Si were in the range from 14 to 26 depending on the post-deposition annealing temperature. The leakage current density was <20 nA cm^?2 at the gate bias voltage of 0.04 MV/cm for the annealed films. The electrical conduction mechanism observed in the films was Poole–Frenkel.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Breakdown fields and conduction mechanisms in thin Ta2O5 layers on Si for high density DRAMs

The conduction mechanisms and the microstructure of rf sputtered Ta₂O₅ on Si, before and after oxygen annealing at high temperatures (873, 1123 K; 30 min) have been investigated. The as-deposited and annealed at 873 K layers are amorphous whereas crystalline Ta₂O₅ (orthorhombic β-Ta₂O₅ phase) was obtained after O₂ treatment at 1123 K. The results (electrical, X-ray diffraction, transmission electron microscopy) reveal the formation of an interfacial ultrathin SiO₂ layer under all technological regimes used. The higher (493 K) substrate temperature during deposition stimulates the formation of amorphous rather than crystalline SiO₂. It is found that the oxygen heating significantly reduces the oxide charge (Q_f<10¹⁰ cm⁻²) and improves the breakdown characteristics (the effect is more pronounced for the higher annealing temperature). It is accompanied by an increase of the effective dielectric constant (up to 37 after 1123 K treatment). It is established that the influence of the oxygen treatment on the leakage current is different depending on the film thickness, namely: a beneficial effect for the thinner and a deterioration of leakage characteristics for thicker (80 nm) films. A leakage current density as low as 10⁻⁷ A/cm² at 1 MV/cm applied field for 26 nm annealed layers has been obtained. The current reduction is considered to be due to a removal by annealing of certain structural nonperfections present in the initial layers. Generally, the results are discussed in terms of simultaneous action of two opposite and competing processes taking place at high temperatures––a real annealing of defects and an appearance of a crystal phase and/or a neutral traps generation. The contribution of the neutral traps also is involved to explain the observed weaker charge trapping in the as-fabricated films compared to the annealed ones.The conduction mechanism of the as-deposited films is found to be of Poole–Frenkel (PF) type for a wide range of applied fields. A change of the conduction mechanism for the annealed films at medium fields (0.8–1.3 MV/cm) is established. This transition from PF process to the Schottky emission limited current is explained with an annealing of bulk traps (oxygen vacancies and nonperfect bonds). It is concluded that the dominant conduction mechanism in the intermediate fields can be effectively controlled by appropriate technological steps.     

Investigation of strontium tantalate thin films for high-k gate dielectric applications

Strontium tantalate (STO) films were grown by liquid-delivery (LD) metalorganic chemical vapor deposition (MOCVD) using Sr[Ta(OEt)₅(OC₂H₄OMe)]₂ as precursor. The deposition of the films was investigated in dependence on process conditions, such as substrate temperature, pressure, and concentration of the precursor. The growth rate varied from 4 to 300 nm/h and the highest rates were observed at the higher process temperature, pressure, and concentration of the precursor. The films were annealed at temperatures ranging from 600 to 1000 °C. Transmission electron microscopy (TEM), X-ray diffraction (XRD), and ellipsometry indicated that the as-deposited and the annealed films were uniform and amorphous and a thin (>2 nm) SiO₂ interlayer was found. Crystallization took place at temperatures of about 1000 °C. Annealing at moderate temperatures was found to improve the electrical characteristics despite different film thickness (effective dielectric constant up to 40, the leakage current up to 6×10⁻⁸ A/cm², and lowest midgap density value of 8×10¹⁰ eV⁻¹ cm⁻²) and did not change the uniformity of the STO films, while annealing at higher temperatures (1000 °C) created voids in the film and enhanced the SiO₂ interlayer thickness, which made the electrical properties worse. Thus, annealing temperatures of about 800 °C resulted in an optimum of the electrical properties of the STO films for gate dielectric applications.     

Thin RF sputtered and thermal Ta2O5 on Si for high density DRAM application

Tantalum pentoxide thin films on Si prepared by two conventional for modern microelectronics methods (RF sputtering of Ta in Ar + O₂ mixture and thermal oxidation of tantalum layer on Si) have been investigated with respect to their dielectric, structural and electric properties. It has been found that the formation of ultra thin SiO₂ film at the interface with Si, during fabrication implementing the methods used, is unavoidable as both, X-ray photoelectron spectroscopy and electrical measurements, have indicated. The initial films (as-deposited and as-grown) are not perfect and contain suboxides of tantalum and silicon which act as electrical active centers in the form of oxide charges and interface states. Conditions which guarantee obtaining high quality tantalum oxide with dielectric constant of 32–37 and leakage current density less than 10⁻⁷ A/cm² at 1.5 V applied voltage (Ta₂O₅ thickness equivalent to about 3.5 nm of SiO₂) have been established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAM application.     

具有低电压、低“迟滞效应”的C60薄膜晶体管

以C60为激活层,同时以聚合物/高K氧化物双绝缘层结构研制了N型有机场效应晶体管。结果表明,采用这种双层结构的绝缘层能够很好的将Ta2O5和PMMA的优点结合在一起,即既利用了Ta2O5的高介电常数又利用了PMMA与半导体层良好的界面接触特性。与采用单一Ta2O5或这PMMA绝缘层的器件相比,这种具有双层结构的器件性能大幅提升。最终研制了能够在10V低电压下正常工作的C60晶体管,其场效应迁移率、阈值电压和开关电流比分别为0.26 cm2/Vs, 3.2V和8.31×104。同时,利用修饰绝缘层PMMA的疏水性大大降低了这种具有双层结构的N型有机晶体管的“迟滞效应”,从而让器件工作时有较好的稳定性。     

Effects of annealing in O2 and N2 on the electrical properties of tantalum oxide thin films prepared by electron cyclotron resonance plasma enhanced chemical vapor deposition

The tantalum oxide thin films with a thickness of 14 nm were deposited at 95°C by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECRPECVD), and annealed at various temperatures (700∼850°C) in O₂ and N₂ ambients. The microstructure and composition of the tantalum oxide thin films and the growth of interfacial silicon oxide layer were investigated and were related to the electrical characteristics of the film. Annealing in an O₂ ambient led to a high dielectric constant (ε_r(Ta₂O₅) = 24) as well as a small leakage current (E_bd = 2.3 MV/cm), which were due to the improved stoichiometry and the decreased impurity carbon content. Annealing in an N₂ ambient resulted in poor and nonuniform leakage current characteristics. The as-deposited tantalum oxide films were crystallized into δ-Ta₂O₅ after annealing at above 750°C regardless of the ambient. The leakage current of the film abruptly increased after annealing at 850°C probably because of the stress caused by thermal expansion or contraction.     

Properties of thin oxide-nitride-oxide stacked films

Electronic conduction, charge trapping and dielectric breakdown were studied on thin stacked layers of SiO₂-Si₃N₄-SiO₂ with Al or poly-Si gate on Si. Conductivity and breakdown strength are roughly the same as observed on single SiO₂ films but the average dielectric constant is higher than that for SiO₂. Stacks with plasma CVD SiO₂ layers show somewhat poorer breakdown strengths than those with thermally grown SiO₂ films. The charging behavior of the stacks is more pronounced than that of single films. Moreover, they break down at a lower total injected charge.     

Time-dependent-dielectric-breakdown characteristics of Hf-doped Ta2O5/SiO2 stack

The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta₂O₅ films (8 nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta₂O₅ were compared. The doped Ta₂O₅ exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10 years lifetime at room temperature is −2.4 V. The presence of Hf into the matrix of Ta₂O₅ modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.     

Fabrication and electrical characteristics of ultrathin (HfO2)x(SiO2)1−x films by surface sol-gel method and reaction-anneal treatment

Hafnium oxide (HfO₂) films were deposited on Si substrates with a pre-grown oxide layer using hafnium chloride (HfCl₄) source by surface sol-gel process, then ultrathin (HfO₂)_x(SiO₂)_1−x films were fabricated due to the reaction of SiO₂ layer with HfO₂ under the appropriate reaction-anneal treatment. The observation of high-resolution transmission electron microscopy indicates that the ultrathin films show amorphous nature. X-ray photoelectron spectroscopy analyses reveal that surface sol-gel derived ultrathin films are Hf-Si-O alloy instead of HfO₂ and pre-grown SiO₂ layer, and the composition was Hf_0.52Si_0.48O₂ under 500 °C reaction-anneal. The lowest equivalent oxide thickness (EOT) value of 0.9 nm of film annealed at 500 °C has been obtained with small flatband voltage of −0.31 V. The experimental results indicate that a simple and feasible solution route to fabricate (HfO₂)_x(SiO₂)_1−x composite films has been developed by means of combination of surface sol-gel and reaction-anneal treatment.     

掺氮氧化铪的光学特性研究

掺氮氧化铪是半导体工业非常重要的材料。在本论文中,我们利用Hf[N(C₂H₅)(CH₃)]₄ 和 H₂O₂作为原子层淀积的前驱体,制备了二氧化铪材料。然后,我们使用快速热退火的办法,在不同温度下,对二氧化铪进行了氮掺杂工艺。我们对掺氮二氧化铪的组分,跟硅界面的稳定性以及薄膜材料的光学特性随退火温度的变化进行了细致的研究。研究发现,随着退火温度的提高,二氧化铪薄膜材料的氮组分从1.41% 上升至 7.45%,相应的,薄膜材料的禁带宽度从5.82 eV 降低为 4.94 eV。