Discrete-time simulation model for 1/f noise

This paper proposes a simulation model based on the fact that 1/f processes belong to the class of statistically self-similar random processes. Unlike most of the earlier modeling approaches, which were confined to the spectral domain, the model generates 1/f noise in the time domain with a simple white noise input and is parameterized by a quantity whose value can be adjusted to reflect the desired slope of the 1/f spectrum. To verify the fit between the model and actual 1/f noise measurements, experiments were conducted with a p-i-n photodiode at various bias conditions and sampling frequencies.     

Statistical BSIM model for MOSFET 1/f noise

A statistical model for MOSFET 1/f noise implemented as an extension to BSIM and integrated into a process design kit is presented. Excellent model to hardware correlation is shown on measured noise statistics from over 200 devices. The statistical model enables circuit designers to run Monte Carlo and corner noise simulations, and captures the device area and bias dependence of noise variance.     

A Sub-1-V Low-Noise Bandgap Voltage Reference

A new sub-1-V bandgap voltage reference is presented in this paper, which has advantages over the prior arts in terms of output noise and compatibility with several fabrication processes. The topology allows the reference to operate with a supply voltage as low as 1 V by employing the reverse bandgap voltage principle (RBVP). It also has an attractive low-noise output without the use of a large external filtering capacitor. The design was fabricated with a 0.5-mum BiCMOS process, but it is compatible with most CMOS and BiCMOS fabrication processes. The entire die area is approximately 0.4 mm², including all test pads and dummy devices. Theoretical analysis and experimental results show that the output noise spectral density is 40 nV/radicHz with a bias current of 20 muA. Moreover, the peak-to-peak output noise in the 0.1-10 Hz band is only 4 muV. The untrimmed reference has a mean output voltage of 190.9 mV at room temperature, and it has a temperature coefficient in the -40degC to +125degC range of 11 ppm/degC (mean) with a standard deviation of 5 ppm/degC.     

Optimal current for minimum thermal noise operation ofsubmicrometer MOS transistors

The wide band noise voltage (equivalent thermal noise voltage at the gate) of a submicron MOSFET, working in saturation, exhibits a minimum value at a certain drain current. This is supported by measurements and theoretical analysis based on a suitable thermal noise model. This macroscopic noise model attributes the thermal noise of the drain current to the superposition of two noise sources originating from two separate regions of the transistor's channel (a gradual channel approximation region and a saturation region). The existence of a minimum of the noise spectral density at an optimum drain current (I_opt), is well proved by measurements and is contradictory to the predictions of the current simulation program with integrated circuit emphasis (SPICE) models. An empirical way for evaluating analytically I_opt is given. The fact of the existence of a noise minimum for a submicron MOSFET, brings a phenomenological equivalence to the bipolar transistor and GaAs MESFET when they are employed at the first stage of an amplifier     

A New Look at Noise in Transferred Electron Oscillators

Low-frequency current and voltage fluctuations have been measured, and it has been confirmed that noise in packaged transferred electron devices (TED's) is due to three distinct noise mechanisms: flicker, generation-recombination, antd thermal noise. For transferred electron oscillators (TEO's), this low-frequency noise is upconverted into the microwave frequency range and adds to the intrinsic RF noise. We have found that between 1 kHz and 1 MHz off the carrier, temperature-dependent generation-recombination noise is the main contributor to the total noise. A model of a noisy TEO is presented. This model permits the calculation of AM and FM noise spectra from device and circuit parameters for measured low-frequency noise or the derivation of device characteristics from noise and circuit parameter measurements.     

A Suitable Method for Ecovehicles to Control Surge Voltage Occurring at Motor Terminals Connected to PWM Inverters and to Control Induced EMI Noise

A method that is suitable for ecovehicles, which controls the surge voltage appearing at motor terminals that are connected to a pulsewidth modulation inverter with short leads that are less than the critical cable length (i.e., the shortest length at which full reflection may occur), is described here. Also, a method to control electromagnetic interference (EMI) noise, which is induced by the surge voltage, is discussed. Ecovehicles have the problem where insulation degradation of motors occurs due to the surge voltage being repeatedly applied to motor terminals during long lifecycles. EMI noise such as the shaft current and the radiated noise, which are induced by the generated surge voltage, easily diffuse into other electric devices due to the high-density packaging structure. The diffused EMI noise may cause a malfunction of the vehicle controller. An EMI noise controller is studied, which can meet the high-density packaging requirements for ecovehicles like electric vehicles. The EMI noise controller is attached on the motor terminals and simultaneously suppresses the surge voltage and the noise. After clarifying surge voltage characteristics and a circuit model for expressing the surge phenomenon through experiments and simulations, an EMI noise controller is proposed, which uses a multilayer printed power circuit technique. It is verified through simulations and experiments that the proposed controller has the ability to simultaneously control the surge voltage and the EMI noise, such as the radiated noise and the shaft current (the bearing current), which are induced by the surge voltage.     

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

Unified 1/f noise SOI MOSFET modelling for circuit simulation

The authors address the modelling of 1/f noise in SOI MOS devices for circuit simulation. A simple and unified model is presented which is valid for all operating regimes; it is verified by comparison with noise measurements. It is shown that this model is especially useful for low-power SOI MOS circuit design     

Low-frequency noise of ion-implanted double-drift IMPATT diodes

The low-frequency open circuit noise spectral density S(f) of an ion-implanted 60-GHz double-drift-region IMPATT diode was measured as a function of the dc avalanche current I0. Over an intermediate current range the noise follows an S(f)=a²VB0²/I0relationship where VB0is the reverse breakdown voltage and a²≃4.5 × 10^-20A/Hz.     

GaInP/GaAs HBTs for high-speed integrated circuit applications

The use of GaInP/GaAs heterojunction bipolar transistors (HBTs) for integrated circuit applications is demonstrated. The discrete devices fabricated showed excellent DC characteristics with low V_ce offset voltage and very low temperature sensitivity of the current gain. For a non-self-aligned device with a 3-μm×1.4-μm emitter area, f_T was extrapolated to 45 GHz and f_max was extrapolated to 70 GHz. The measured 1/f noise level was 20 dB better than that of AlGaAs HBTs and comparable to that of low-noise silicon bipolar junction transistors, and the noise bump (Lorentzian component) was not observed. The fabricated gain block circuits showed 8.5 dB gain with a 3-dB bandwidth of 12 GHz, and static frequency dividers (divide by 4) were operable up to 8 GHz     

Phase noise in LC oscillators

Analytical methods for the phase-noise analysis of LC-tuned oscillators are presented. The fundamental assumption used in the theoretical model is that an oscillator acts as a large-signal LC-tuned amplifier for purposes of noise analysis. This approach allows us to derive closed-form expressions for the close-to-carrier spectral density of the output noise, and to estimate the phase-noise performance of an oscillator from circuit parameters using hand analysis. The emphasis is on an engineering approach intended to facilitate rapid estimation of oscillator phase noise. Theoretical predictions are compared with results of circuit simulations using a nonlinear phase-noise simulator. The analytical results are in good agreement with simulations for weakly nonlinear oscillators. Complete nonlinear simulations are necessary to accurately predict phase noise in oscillators operating in a strongly nonlinear regime. To confirm the validity of the nonlinear phase-noise models implemented in the simulator, simulation results are compared with measurements of phase noise in a practical Colpitts oscillator, where we find good agreement between simulations and measurements     

Temperature dependence of 1/f noise in Hg1-xCdxTe MIS infrared detectors

We measured 1/f noise on Hg_0.71Cd_0.29Te Metal-Insulator-Semiconductor (MIS) infrared detectors operated over the temperature range of 40 K to 90 K under 300 K Infrared (IR) radiation. The purpose of the study was to identify the sources of 1/f noise, especially in relation to the dark current. The devices were operated in the correlated double sampling mode where the voltage across the MIS capacitor was sampled at empty potential well and right after the accumulation of minority carriers in the well due to IR radiation generation. The noise power spectral density for the charge integrated in the MIS well was investigated in relation to the dominant component of dark current. At lower temperatures T⩽65 K, the charge noise power spectral density was found to depend quadratically on the dark current. At higher temperatures, this quadratic dependence did not exist. We attribute the dark current to a mixture of tunneling and depletion-region-originated minority carrier generation which seems to be responsible for 1/f fluctuations in these structures for temperatures below 65 K     

低偏置电流下大功率半导体激光器低频电噪声特性

测量了大功率InGaAsP/GaAs量子阱半导体激光器在五十分之一阈值电流下的电压低频噪声功率谱密度.实验结果显示,激光器的低频电噪声呈现1/f噪声,在不同的偏置电流范围内,1/f噪声幅度随电流的变化关系不同,整体上随偏置电流的增大而减小,实验中并未发现g-r噪声.结合低偏置电流时激光器动态电阻的大小,给出了1/f噪声的模型,分析了在低偏置电流下的1/f噪声主要来自有源区和漏电电阻,其幅度的大小及其随偏置电流的变化趋势与激光器的可靠性有密切的关系.     

Measurement and comparison of 1/f noise and g-r noise in siliconhomojunction and III-V heterojunction bipolar transistors

This paper experimentally determines and compares the 1/f noise and the g-r noise, as components of the base noise current spectral density, in Si homojunction and III-V heterojunction bipolar transistors (HBTs) in common-emitter configuration. The noise spectra for each of these devices are obtained as functions of the base bias current (I_B), and the 1/f noise has been found to depend on I_B as I_B^γ, where γ~1.8 for the silicon BJT's and InP/InGaAs HBT's with high current gains (β~50), and γ~1.1 for the AlGaAs/GaAs HBTs with low current gains (4<β<12). The nearly constant current gain and the near square-law and inverse-square emitter area dependence of 1/f noise in silicon devices are indicative of the dominant base bulk recombination nature of this noise. The 1/f noise in the InP based HBTs has been found to be lowest among all the devices we have tested, and its origin is suggested to be the base bulk recombination as in the Si devices. For the AlGaAs/GaAs HBTs, the low current gain and the near unity value of γ, arise most likely due to the combined effects of surface, bulk, and depletion region recombinations and the base-to-emitter injection. The dependence of the 1/f noise on the base current density in the devices tested in this work, and those tested by others are compared to find out which HBT's have achieved the lowest level of 1/f noise     

MOSFET 1/f noise measurement under switched bias conditions

A new measurement setup is presented that allows the observation of 1/f noise spectra in MOSFET's under switched bias conditions in a wide frequency band (10 Hz-100 kHz). When switching between inversion and accumulation, MOSFET's of different manufacturers invariably show reduced 1/f noise power density for frequencies below the switching frequency. At low frequencies (10 Hz), a 5-8 dB reduction in intrinsic 1/f noise power density is found for different devices, largely independent of the switching frequency (up to 1 MHz). The switched bias measurements render detailed wideband 1/f noise spectra of switched MOSFET's, which is useful for 1/f noise model validation and analog circuit design     

An investigation of low-frequency noise in complementary SiGe HBTs

We present a comprehensive investigation of low-frequency noise behavior in complementary (n-p-n + p-n-p) SiGe heterojunction bipolar transistors (HBTs). The low-frequency noise of p-n-p devices is higher than that of n-p-n devices. Noise data from different geometry devices show that n-p-n transistors have an increased size dependence when compared with p-n-p transistors. The 1/f noise of p-n-p SiGe HBTs was found to have an exponential dependence on the (intentionally introduced) interfacial oxide (IFO) thickness at the polysilicon-to-monosilicon interface. Temperature measurements as well as ionizing radiation were used to probe the physics of 1/f noise in n-p-n and p-n-p SiGe HBTs. A weak temperature dependence (nearly a 1/T dependence) of 1/f noise is found in both n-p-n and p-n-p devices with cooling. In most cases, the magnitude of 1/f noise is proportional to I/sub B//sup 2/. The only exception in our study is for noise in the post-radiation n-p-n transistor biased at a low base current, which exhibits a near-linear dependence on I/sub B/. In addition, in proton radiation experiments, the 1/f noise of p-n-p devices was found to have higher radiation tolerance than that of n-p-n devices. A two-step tunneling model and a carrier random-walk model are both used to explain the observed behavior. The first model suggests that 1/f noise may be caused by a trapping-detrapping process occurring at traps located inside IFO, while the second one indicates that noise may be originating from the emitting-recapturing process occurring in states located at the monosilicon-IFO interface.     

Impact of collector-base junction traps on low-frequency noise in high breakdown Voltage SiGe HBTs

This work investigates the impact of collector-base (CB) junction traps on low-frequency noise in high breakdown voltage (HBV) SiGe HBTs. By comparing the base current and 1/f noise at the same internal emitter-base (EB) voltage of the standard breakdown voltage (SBV) and HBV devices, we show that the CB junction traps not only increase base current, but also contribute base current 1/f noise when high injection occurs. The individual 1/f noise contributions from the emitter-base junction traps and from the collector-base junction traps are separated. The dependence of the 1/f noise component on the corresponding base current component is determined, and shown to be different for the EB and CB junction traps. The dependence of the total 1/f noise on the total base current, however, remains the same before and after high injection occurs in the HBV device, which is approximately the same as that for the SBV device. The I/sub B/ contribution from the CB junction recombination current needs to be modeled for accurate I-V and 1/f noise modeling.     

Material and device characterization using a correlation spectrum analyzer

The paper presents the possibilities offered by the Correlation Spectrum Analyzer in the characterisation of semiconductor materials and microelectronic devices. The instrument performs noise analysis in a frequency range from a few mHz to 1 MHz with an extraordinary sensitivity of 1fA/√Hz in current noise measurements and of 20 pV/√Hz in voltage noise measurements. Noise spectra taken in these conditions can be used as a non-destructive-sensitive probe to investigate physical properties of semiconductor materials as well as quantify the noise produced by new devices. As an example of these applications, the text reports on the extraction of noise parameters from a MOSFET operated in strong sub-threshold regime to be inserted in noise models for circuit simulation and on the determination of carrier mobility in single-crystal cadmium telluride (CdTe) samples.     

1/f noise in CMOS transistors for analog applications

Noise measurements of the 1/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two “low noise” CMOS processes of 2 μm and 0.5 μm technologies are compared and it is found that the more advanced process, with 0.5 μm technology, exhibits significantly reduced 1/f noise, due to optimized processing. The input referred noise and the power spectral density (PSD) of the drain current 1/f noise are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits