CMOS Power-Efficient Buffers and Amplifiers

In this paper, some topologies of novel power-efficient single-ended and fully differential amplifiers and buffers are presented. The reduction of the power dissipation has been ensured through the application of an adaptive biasing architecture which gives a current dependent on the input differential voltage. This allows the minimization of the stand-by power consumption without affecting the transient characteristics. The proposed topology, implemented in a standard CMOS technology, has been applied in the design of input and output stages of low-power amplifiers and voltage buffers, considering them also in the fully differential version. Simulation and measurement results showing good general performance will be also presented.     

Low-power high-speed rail-to-rail LCD output buffer with dual-path push–pull operation and quiescent current control

The present paper addresses a new compact low-power high-speed output buffer amplifier topology for large-size liquid crystal display applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by simultaneously exploiting the push–pull output sections of two basic complementary-type input amplifiers to realize a dual-path push–pull operation of the output stage. An auxiliary biasing network integrated in the input differential stage allows the quiescent bias conditions of the class-AB output stage to be inherently controlled without additional current dissipation. Post-layout simulation results confirm that the proposed amplifier can drive a 1-nF column line load within a 0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current. Monte Carlo simulations are finally carried out, showing a good degree of robustness of the proposed output buffer against process and mismatch variations.     

一种带自适应斜坡补偿的PCM控制Boost变换器

设计了一种带自适应斜坡补偿的峰值电流模式(PCM)控制Boost变换器。采用一种低功耗自适应斜坡补偿电路,使得升压(Boost)变换器能够实现宽输出范围和高带载能力。在此基础上,提出了一种应用于Boost变换器的电感电流采样电路,该电路实现了高采样速度和高采样精度,且具备全周期的电感电流采样特点。变换器基于SMIC 180 nm BCD CMOS工艺设计。仿真结果表明,该带自适应斜坡补偿的PCM控制Boost变换器输入电压转换范围为2.8 V～5.5 V,输出电压转换范围为4.96 V～36.1 V,最大输出负载电流高达5 A。     

A Novel Resistor-Free Electronically Adjustable Current-Mode Instrumentation Amplifier

In this paper, a novel topology for implementing resistor-free current-mode instrumentation amplifier (CMIA) is presented. Unlike the other previously reported instrumentation amplifiers (IAs), in which input and/or output signals are in voltage domain, the input and output signals in the proposed structure are current signals and signal processing is also completely done in current domain benefiting from the full advantages of current-mode signal processing. Interestingly the CMRR of the proposed topology is wholly determined by only five transistors. Compared to the most of the previously reported IAs in which at least two active elements are used to attain high common-mode rejection ratio (CMRR) resulting in a complicated circuit, the proposed structure enjoys from an extremely simple circuit. It also exhibits low input impedance employing negative feedback principal. Of more interest is that, using simple degenerate current mirrors, the differential-mode gain of the proposed CMIA can be electronically varied by control voltage. This property makes it completely free of resistors. The very low number of transistors used in the structure of the proposed CMIA grants it such desirable properties as low-voltage low-power operation, suitability for integration, wide bandwidth etc. SPICE simulation results using the TSMC 0.18-μm CMOS process model under supply voltage of ±0.8 V show a high CMRR of 91 dB and a low input impedance of 291.5 Ω for the proposed CMIA. Temperature simulation results are also provided, which prove low temperature sensitivity of the proposed CMIA.     

Super Class-AB OTAs With Adaptive Biasing and Dynamic Output Current Scaling

A new family of single-stage super Class-AB operational transconductance amplifiers (OTAs) suitable for low-voltage operation and low power consumption is presented. Three novel topologies are proposed featuring simplicity and compactness. They are based on the combination of adaptive biasing techniques for the differential input stage and nonlinear current mirrors for the active load that provide additional dynamic current boosting. The OTAs have been fabricated in a standard 0.5-mum CMOS process. Experimental results show a greatly improved slew rate by factors 30-60 and gain-bandwidth product by factors 11.5-17 when compared to a classical Class-A OTA. The circuits are operated at plusmn1-V supply voltage with only 10 muA of bias current     

The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

This paper provides evidence that, as a result of constant-field scaling, the peak$f_T$(approx. 0.3$hbox mA/muhbox m$), peak$f_ MAX$(approx. 0.2$hbox mA/muhbox m$), and optimum noise figure$ NF_ MIN$(approx. 0.15$hbox mA/muhbox m$) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40–80 Gb/s wireline transceivers.     

一种新型的高性能CMOS电流比较器电路

分析了目前几种高性能连续时间CMOS电流比较器的优缺点,提出了一种新型CMOS电流比较器电路．它包含一组具有负反馈电阻的CMOS互补放大器、两组电阻负载放大器和两组CMOS反相器．由于CMOS互补放大器的负反馈电阻降低了它的输入、输出阻抗,从而使电压的变化幅度减小,所以该电流比较器具有较短的瞬态响应时间和较快的速度．电阻负载放大器的使用减小了电路的功耗．利用1.2μm CMOS工艺HSPICE模型参数对该电流比较器的性能进行了模拟,结果表明该电路的瞬态响应时间达到目前最快的CMOS电流比较器的水平,而功耗则低于这些比较器,具有最大的速度/功耗比．此外,该CMOS电流比较器结构简单,性能受工艺偏差的影响小,适合应用于高速/低功耗电流型集成电路中．     

A Compact and Low-Power CMOS Circuit for Fully Integrated NEMS Resonators

This brief presents a fully integrated nanoelectromechanical system (NEMS) resonator, operable at frequencies in the megahertz range, together with a compact built-in CMOS interfacing circuitry. The proposed low-power second-generation current conveyor circuit allows detailed read-out of the nanocantilever structure for either extraction of equivalent circuit models or comparative studies at different pressure and dc biasing conditions. In this sense, extensive experimental results are presented for a real mixed electromechanical system integrated through a combination of in-house standard CMOS technology and nanodevice post-processing by nanostencil lithography. The proposed read-out scheme can be easily adapted to operate the nanocantilever in closed loop operation as a stand-alone NEMS oscillator     

Push-pull current circuit for biasing CMOS amplifiers with rail-to-rail input common-mode range

A push-pull current circuit for biasing CMOS amplifiers with rail-to-rail input common-mode range is presented. By means of a feedback action, the circuit avoids the large magnitude deviations inherent to this type of amplifier and thus facilitates their optimisation and compensation. Simulated and experimental results obtained from a fabricated 2 mu m CMOS test chip are reported.<>     

Feedback Biasing in Nanoscale CMOS Technologies

This work rediscovers the attractiveness of feedback biasing when applied to circuits designed in nanoscale CMOS technologies. It is shown that very compact amplifiers can be obtained by utilizing a type of biasing that imposes minimal area overhead. We discuss how the undesired features of the nanoscale CMOS technologies actually help in the revival of this simple biasing method in newer technology generations. The measurement results of prototyped common-source (CS) amplifiers utilizing feedback biasing for application in medical ultrasound imaging systems are presented in this brief. The proposed feedback biasing is also suitable for amplifying signals from high-impedance sources that pose challenges on maintaining high input impedance for the voltage amplifiers while maintaining a very low input capacitance value. Measurements show that the proposed amplifier achieves a voltage gain of 28 dB, an output noise power spectral density of 0.11 $(muhbox{V})^{2}/ hbox{Hz}$ at center-frequency, and a total harmonic distortion of $-$30 dB, with the full-scale output at 30 MHz, while drawing 120 $muhbox{A}$ from a 1-V power supply. The amplifiers were fabricated in 90-nm CMOS technology and measured to be just $20 muhbox{m} times 10 muhbox{m}$.      

A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique

This paper describes the circuit design and measurement results of a new CMOS frequency doubler proposed for 5-GHz-band wireless applications. The doubler, which can operate at 1.8 V, was fabricated in a standard 0.18-/spl mu/m bulk CMOS technology which has no extra processing steps to enhance RF performance. A current-reuse circuit-design technique is successfully incorporated into the doubler so as to realize both on-chip input/output matching and adequate conversion gain with low input power drive despite the utilization of the standard bulk CMOS technology. The doubler with a single input/output interface features a bypass resistor placed between common ground and a source node of the second stage FET in the current-reuse topology, thereby improving both input power level and conversion gain while saving waste current. Measurement results under the condition of 5.2 GHz and 1.8 V reveal the following good performance: a 2.7-dB maximum conversion gain, a 0.3-dBm high output power, and a 9-mA low current dissipation are achieved with a 2.6-GHz, -3-dBm input power. With a 7-mA low current dissipation and a -7-dBm low input power, the doubler can deliver conversion gain as high as 0 dB. These measurement results are good agreement with the simulated ones.     

A differential-input,differential-output current mode operational amplifier

A current operational amplifier with differential input and differential output is described. The amplifier is based on the parallel connection of a CCII+ current conveyor and a CCII? current conveyor followed by a differential output transconductance gain stage. The performance of the amplifier is analysed and experimental results obtained from an implementation using standard operational amplifiers and current mirrors realized using transistor arrays are presented and compared to the theoretical analysis. It is concluded that the static small signal open loop gain and the frequency response matches the performance of conventional voltage operational amplifiers. The input offset and bias errors and the common mode rejection are shown to be strongly dependent on the matching accuracy of the current mirrors used in the conveyors. The proposed configuration can easily be integrated into a monolithic amplifier in either CMOS or bipolar technology.     

An adaptive biasing one-stage CMOS operational amplifier fordriving high capacitive loads

An adaptive biasing one-stage CMOS operational amplifier for driving high capacitive loads has been developed. The amplifier has been designed to drive liquid-crystal-displays (LCDs) in battery-supplied devices. Contradictory features like low power dissipation and high driving capability at low supply voltage are required. Complementary differential input stages provide rail-to-rail common-mode input range. With a special cross-coupled double-to-single-end conversion, a full supply output range is achieved. These improvements solve a functional problem of some existing adaptive biasing amplifiers. Simulation and measurements demonstrate good correlation and show the expected results, especially in the critical operating area     

A high speed low input impedance current pulse amplifier cell

A high speed CMOS current pulse amplifier cell with low input impedance, devoted to nuclear multichannel detectors where crosstalk is a serious problem, is presented. The symmetry of the circuit achieved with complementary transistors yields both an input and an output with low offset voltage, opening a large field of applications such as transimpedance amplifiers and therefore transimpedance operational amplifiers.     

High Accuracy Class AB CCII-

New CMOS realization of the negative-type second-generation current conveyor (CCII-) suitable for low power applications is presented. A dynamic biasing circuit is used to control the bias currents of the output stage and to provide class AB mode of operation. The proposed CCII- features high voltage tracking accuracy and low input impedance as a consequence of negative feedback. The compensation of the current tracking error between the X and the Z terminals is also introduced.     

A low-voltage low-power instrumentation amplifier based on supply current sensing technique

In this paper a new low-voltage low-power instrumentation amplifier (IA) is presented. The proposed IA is based on supply current sensing technique where Op-Amps in traditional IA based on this technique are replaced with voltage buffers (VBs). This modification results in a very simplified circuit, robust performance against mismatches and high frequency performance. To reduce the required supply voltage, a low-voltage resistor-based current mirror is used to transfer the input current to the load. The input and output signals are of voltage kind and the proposed IA shows ideal infinite input impedance and a very low output one. PSPICE simulation results, using 0.18 μm TSMC CMOS technology and supply voltage of ±0.9 V, show a 71 dB CMRR and a 85 MHz constant −3 dB bandwidth for differential-mode gain (ranging from 0 dB to 18 dB). The output impedance of the proposed circuit is 1.7 Ω and its power consumption is 770 µW. The method introduced in this paper can also be applied to traditional circuits based on Op-Amp supply current sensing technique.     

Differential Difference Current Conveyor Using Bulk-Driven Technique for Ultra-Low-Voltage Applications

Nowadays the necessity of having low-voltage operation and low-power consumption is essential for electronic devices, particularly for portable electronics. Therefore, this paper presents a new ultra-low-voltage CMOS topology for a differential difference current conveyor (DDCC) based on the bulk-driven (BD) principle. Due to the use of the BD technique, the proposed circuit is capable of working with a low supply voltage of ±0.3 V and consumes about 18.6 μW with a wide input common-mode range. The proposed BD-DDCC is suitable for ultra-low-voltage low-power applications. As application examples, a voltage-mode multifunction biquadratic filter based on two BD-DDCCs and four grounded passive elements, and a fourth-order band-pass filter are presented. All passive elements of both applications are grounded, which is advantageous for monolithic integration. Also, the input voltage signals are applied directly to the high input impedance terminals, which is a desirable feature for voltage-mode operation. The simulations were performed with PSPICE using the TSMC 0.18 μm n-well CMOS technology to prove the functionality and attractive results of the proposed circuit.     

Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input and output resistances, the delay time of the current comparator is shortened. Its power consumption can be reduced rapidly with the increase of input current. Simulation results based on 1.2 m CMOS process model show the speed of the novel current comparator is comparable with those of the existing fastest CMOS current comparators, and its power consumption is the lowest, so it has the smallest power-delay product. Furthermore, the new current comparator occupies small area and is process-robust, so it is very suitable to high-speed and low-power applications.     

A 10-b 20-Msample/s low-power CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 μm CMOS technology exhibits a DNL of ±0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm²     

A New CMOS Buffer Amplifier Design Used in Low Voltage MEMS Interface Circuits

To achieve low voltage high drivingcapability with quiescent current control, a class-AB CMOS buffer amplifier usingimproved quasi-complementary output stage and error amplifiers with adaptive loadsis developed. Improved quasi-complementary output stage enables it more suitablefor low voltage applications, while adaptive load in error amplifier is used toincrease the driving capability and reduce the sensitivity of the quiescentcurrent to fabrication process variation. The circuit has been fabricated in 0.8μm CMOS process. With 300 Ω load in a ±1.5 V supply, its outputswing is 2.42 V. The mean value of quiescent current for eight samples is 204μA, with the worst deviation of 17%.