Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications

Timing recovery in communication systems with linear modulations is usually performed with a non-data-aided feedback loop based on a fractional interpolator timing corrector and the Gardner’s timing error detector. The contribution of this paper is twofold. First, some design rules are given to predict the behaviour of the loop if pipeline is used. Second, it is shown that pipelining can be used to reduce power consumption in a timing feedback loop. A timing recovery loop has been implemented in an FPGA device and power consumption measures indicates that by including 16 extra registers in the loop the power consumption decreases a 63% and the synchronizer can process up to 66.5 MSPS.

欧洲的宽带电力线通信接入系统

分别从网络体系结构与系统组成、安全性与私密性、传输距离与覆盖范围、小区间干扰、信号耦合方式与安装几方面介绍了欧洲宽带电力线通信(PLC)接入系统的一个实例。现场试验表明．PLC系统室外部分使用低频段、室内部分使用高频段可解决通路损耗与电磁兼容性问题;时分多址和时分双工将成为比较好的候选技术;在无中继器情况下,最大室外传输距离可达250—300m;保证相邻PLC系统之间上行时隙和下行时隙的同步能解决邻室PLC系统间的干扰问题;选择适当的信号耦合方式对获得良好覆盖十分重要。     

宽带数字预失真硬件平台设计与实现

针对第3代移动网络基站射频功率放大器的线性化需求的不断提高和立足于未来第4代移动通信系统基站,设计并实现了一款以FPGA为核心的宽带数字预失真硬件平台。首先,对整体硬件框架进行了阐述并着重分析了LTM9003的带通采样定理和AD9788的数字单边带调制;其次,根据2-D(ADC)和ADC多次采样技术,提出了超宽带矢量信号测试的系统结构和原理实现;最后,对整机进行了ADC和DAC链路的测试,测试结果表明其性能基本达到了数字预失真的需求。     

宽带通信系统数字插值滤波器组设计

针对宽带无线通信要求,提出了一种基于半带滤波器和CIC滤波器级联的上采样滤波器组实现方案.在半带滤波器浮点到定点量化过程中,提出了一种系数量化优化算法.通过仿真,验证了在相同的量化位数下,相对于传统的系数量化方法,增加了整个滤波器组的阻带衰减.     

Efficient Architectures for Multiuser FMT Systems and Application to Power Line Communications

In this letter we study filtered multitone modulation (FMT) for broadband multiuser power line communications. We address the implementation problem, and we derive a novel efficient digital implementation of both the synthesis and the analysis filter bank. A simple fractionally spaced multiuser receiver is also proposed.     

软件无线电数字中频处理的优化设计

软件无线电是目前通信领域研究的热点,其关键技术之一数字中频技术是多速率信号处理理论的典型应用。本文研究了窄带信号条件下,高倍抽取的数字下变频设计,重点分析了基于CIC滤波器和HB滤波器的多级抽取算法。经比较,该设计比单级多相抽取设计节省98.8％的资源,完全可在单片FPGA内实现,而且,滤波性能优于设计指标要求。     

一种宽带信号数字下变频的实现方法

在宽带、超宽带应用中,单一信号带宽达几百兆赫兹;或者在不同中频同时调制多个信号产生的宽带信号也达数百兆赫兹,用常规的数字下变频方法很难实现。文章提出了一种基于DFT滤波器组的高效数字下变频结构,分析了该解调算法的特点和实现性能。对已知信号带宽和中频的宽带信号,对比了DFT滤波器组和多相分解算法的性能。对信号带宽和中频均在变化的信号,给出了实现思路。最后,给出了该DFT滤波器组的硬件实现方案。     

基于FPGA的高效数字下变频的设计与实现

介绍了一种基于软件无线电思想的高效数字下变频的实现方法,阐述了数字下变频中的数控振荡器、CIC滤波器、半带滤波器和低通滤波器的设计与实现.结合Matlab滤波器算法技术和在Quartus Ⅱ系统下仿真,改进了滤波器组结构和参数.仿真结果表明,基于FPGA设计的数字下变频能够满足多制式短波电台性能指标要求,并且减少硬件资...     

中华人民共和国通信行业标准——通信用不间断电源——UPS

7标志、包装、运输、贮存 7．1标志 7．1．1产品表面应有中文标识,包括产品名称、产品型号、产品编号、制造厂名、制造日期、产品主要参数等。     

An Area Optimization Method for Digital Filter Design

In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip‐flops and full‐adders without additional critical path delay. We also propose a resource sharing method and sharing‐pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.     

An Efficient Power-Delivery Method for the Design of the Power Distribution Networks for High-Speed Digital Systems

In this paper, a new power distribution network (PDN) design method from a power delivery viewpoint is proposed. Two new parameters, the power delivery delay and the $Delta V$ time constant, are introduced to characterize the effects of the lead inductors and decoupling capacitors on the timely power delivery respectively for a high-speed PDN. The decoupling time of a PDN is accurately estimated from the power delivery delay introduced by the inductance of the discontinuities, the charge delivery speed, and the charge supply capacity of the decoupling capacitors are accurately characterized by the $Delta V$ time constant. Based on the two parameters, a complete and systematic power-delivery method for the design of a PDN is developed. The proposed design method is verified by SPICE, full-wave simulations, and measurements. For completion, some specific design considerations are also discussed in detail.      

一种宽带高效率J类功率放大器的设计

针对未来无线通信系统中的宽带和效率问题,设计了一种宽带高效率的J类功率放大器。为了减少谐波阻抗对效率的影响,该J类功率放大器在输出匹配网络中采用了谐波控制单元,并通过对晶体管模型的简化,综合出一种较好的匹配网络。另外,在输入匹配网络中,使用了具有宽带效应的混合集中和分布元件的π形匹配网络。设计中使用10 W GaN HEMT晶体管对理论进行验证,测试结果显示,在2.2 GHz～2.8 GHz之间的频带内,J类功率放大器的漏极效率大于61%,增益大于10.4 dB。该J类功率放大器在下一代无线通信系统中具有良好的应用前景。     

宽带数字下变频器的一种新的实现结构

在软件无线电系统中，由于A／D输出数据流的采样率很高以及信道选择滤波器过渡带宽要求很窄等原因，数字下变频器(DDC)的运算复杂度很高。该文将基于频率响应屏蔽(FRM)方法的FIR滤波器引入到数字下变频器设计中，并详细地研究了此类数字下变频器的高效实现结构和算法复杂度。理论分析与仿真结果表明文中给出的DDC实现结构的计算效率很高。     

简易数字存储示波器电子综合实验项目设计

设计了一个电子综合实验项目简易存储示波器,让学生利用低频,数字电路、单片机技术、EDA技术等相关专业技能,完成方案设计,电路制作、直到最后的调试验收整个项目开发过程。培养学生应用已学的专业基础知识,进行项目设计和开发的能力。     

一种高速低功耗直接数字频率合成器的设计与实现

根据直接数字频率综合(DDS)的原理，采用各种优化技术，设计了一种高速低功耗直接数字频率合成器。详细介绍了电路结构及优化方法。电路采用Xilinx公司的Virtex器件实现，取得了较好的整体性能。     

一种高效宽带数字下变频器的设计与实现

针对雷达系统小型化和低功耗的应用需求,提出一种宽带雷达数字接收机中数字下变频器的设计方法.通过采用系统采样频率等于输入信号中心频率4倍的采样技术,结合混频器的特殊实现结构以及半带FIR滤波器抽头系数的特点,经过详细的理论推导后,给出该方法具体的硬件实现结构,能够显著降低数字下变频信号处理的复杂程度,有效减少对硬件逻辑资源,尤其是硬件乘法器的消耗.该方法在FPGA中实现时,与使用传统方法设计的数字下变频器相比,硬件逻辑资源消耗减少83.65%,功耗降低约110 mW.最后,设计实例结果验证了设计方法的正确性以及很好的工程实用性.     

Hardware Architecture of Polyphase Filter Banks Performing Embedded Resampling for SoftwareDefined Radio FrontEnds

In this paper, we describe resource-efficient hardware architectures for software-defined radio (SDR) front-ends. These architectures are made efficient by using a polyphase channelizer that performs arbitrary sample rate changes, frequency selection, and bandwidth control. We discuss area, time, and power optimization for field programmable gate array (FPGA) based architectures in an M -path polyphase filter bank with modified N -path polyphase filter. Such systems allow resampling by arbitrary ratios while simultaneously performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. A non-maximally decimated polyphase filter bank, where the number of data loads is not equal to the number of M subfilters, processes M subfilters in a time period that is either less than or greater than the M data-load’s time period. We present a load-process architecture (LPA) and a runtime architecture (RA) (based on serial polyphase structure) which have different scheduling. In LPA, N subfilters are loaded, and then M subfilters are processed at a clock rate that is a multiple of the input data rate. This is necessary to meet the output time constraint of the down-sampled data. In RA, M subfilters processes are efficiently scheduled within N data-load time while simultaneously loading N subfilters. This requires reduced clock rates compared with LPA, and potentially less power is consumed. A polyphase filter bank that uses different resampling factors for maximally decimated, under-decimated, over-decimated, and combined up- and down-sampled scenarios is used as a case study, and an analysis of area, time, and power for their FPGA architectures is given. For resource-optimized SDR front-ends, RA is superior for reducing operating clock rates and dynamic power consumption. RA is also superior for reducing area resources, except when indices are pre-stored in LUTs.     

一种高效实用的直接数字频率合成器的设计和实现

在介绍DDS原理和特点的基础上，充分利用正弦函数的对称性，给出了DDS的一种实现方案，详细阐述了用FPGA实现该方案的方法，文章的最后给出了仿真结果。     

一种基于FPGA与DSP的数字射频发射机的设计与实现

射频发射机是通信系统中的一种必不可少的设备。本文设计了一种包括数字基带电路和发射电路的数字射频发射机。数字基带电路主要是使用DSP芯片来实现,通过对DSP的编程来实现数据信号的封装与编码;数字基带电路能提供方便的用户接口以实现与上位机的通信,以及组网等功能。发射电路是采用射频测试平台技术来实现,使用模块化的结构设计。在ADS软件环境下对数字射频发射机的电路进行了仿真,仿真结果说明本文的数字射频发射机的设计是有效和可行的。