Fabrication of Flexible Transducer Arrays With Through-Wafer Electrical Interconnects Based on Trench Refilling With PDMS

Flexible transducer arrays are desired to wrap around catheter tips for side-looking intravascular ultrasound imaging. We present a technique for constructing flexible capacitive micromachined ultrasonic transducer (CMUT) arrays by forming polymer-filled deep trenches in a silicon substrate. First, we etch deep trenches between the bottom electrodes of CMUT elements on a prime silicon wafer using deep reactive ion etching. Second, we fusion-bond a silicon-on-insulator (SOI) wafer to the prime silicon wafer. Once the silicon handle and buried oxide layers are removed from the back side of the SOI wafer, the remaining thin silicon device layer acts as a movable membrane and top electrode. Third, we fill the deep trenches with polydimethylsiloxane, and thin the wafer down from the back side. The 16 by 16 flexible 2-D arrays presented in this paper have a trench width that varies between 6 and 20 ; the trench depth is 150 ; the membrane thickness is 1.83 ; and the final substrate thickness is 150 . We demonstrate the flexibility of the substrate by wrapping it around a needle tip with a radius of 450 (less than catheter size of 3 French). Measurements in air validate the functionality of the arrays. The 250- by 250- transducer elements have a capacitance of 2.29 to 2.67 pF, and a resonant frequency of 5.0 to 4.3 MHz, for dc bias voltages ranging from 70 to 100 V.     

Sacrificial wafer bonding for planarization after very deep etching

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of polymer bonding followed by dry etching and anodic bonding combined with KOH etching are discussed. The polymer bonding has been applied in a strain based membrane pressure sensor to pattern the strain gauges and to provide electrical connections across a deep corrugation in a thin silicon nitride membrane by metal bridges     

Fabrication of silicon and oxide membranes over cavities usingion-cut layer transfer

Silicon and oxide membranes were fabricated using an ion-cut layer transfer process, which is suitable for sub-micron-thick membrane fabrication with good thickness uniformity and surface micro-roughness. After hydrogen ions were implanted into a silicon wafer, the implanted wafer was bonded to another wafer that has patterned cavities of various shapes and sizes. The bonded pair was then heated until hydrogen-induced silicon layer cleavage occurred along the implanted hydrogen peak concentration, resulting in the transfer of the silicon layer from one wafer to the other. Using this technique, we have been able to form sealed cavities and channels of various shapes and sizes up to 50-μm wide, with a 1.6-μm-thick silicon membrane. As a process variation, we have also fabricated silicon dioxide membranes for optically transparent applications     

Towards a versatile DRIE: silicon pit structures combined with electrochemical etch stop

A novel approach for fabricating low-pitch arrays of silicon membranes on standard CMOS wafers by combining deep-reactive ion etching (DRIE) and electrochemical etching (ECE) techniques is presented. These techniques have been used to fabricate membrane-based sensors and sensor arrays featuring different membrane sizes on a single wafer with a well defined etch stop. The described procedure is particularly useful in cases when the usage of SOI wafers is not an option. The combination of a grid-like mask pattern featuring uniform-size etch openings for the DRIE process with a reliable ECE technique allowed to fabricate silicon membranes with sizes ranging from 0.01 mm/sup 2/ to 2.2 mm/sup 2/. The development of this new method has been motivated by the need to design a compact n-well-based calorimetric sensor array, where the use of a standard ECE technique would have significantly increased the overall size of the device.     

Deflection and maximum load of microfiltration membrane sieves madewith silicon micromachining

With the use of silicon micromachining, an inorganic membrane sieve for microfiltration has been constructed having a silicon nitride membrane layer with thickness typically 1 μm and perforations typically between 0.5 μm and 10 μm in diameter. As a support a 〈100〉-silicon wafer with openings of 1000 μm in diameter has been used. The thin silicon nitride layer is deposited on an initially dense support by means of a suitable chemical vapor deposition method (LPCVD). Perforations in the membrane layer are obtained with use of standard photo lithography and reactive ion etching (RIE). The deflection and maximum load of the membrane sieves are calculated in a first approximation. Experiments to measure the maximum load of silicon-rich silicon nitride membranes have confirmed this approximation     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

Static and dynamic test methods for thin mono- and polycrystalline Si-films

We present nondestructive optical methods for the characterization of thin (<30 m) mono-and polycrystalline Si-films. The thickness and homogeneity will be measured with reflectance interferometry. This method is suitable for the end point detection during the etching process of monocrystalline Si. The application of laser absorption for the measurement of the thickness is also discussed. Michelson interferometry is applied for the characterization of the dynamic behavior of thin Si-films. We have analyzed the amplitude and the function of the oscillatory motion after acoustic and electrical excitation.     

基于金硅腐蚀自停止技术的亚微米梁制作研究

提出了利用无电极电化学腐蚀自停止技术制作亚微米梁结构的新工艺方法。根据金硅腐蚀自停止现象发生的条件,结合硅材料的各向异性腐蚀特性,设计器件结构,利用腐蚀暴露面积变化实现了硅的选择性自停止腐蚀。在(111)型硅片上利用原电池钝化效应一次性腐蚀出与衬底绝缘,由约4μm厚的金电极支撑,厚度约为235 nm的亚微米梁结构,具有制作简单、成品率高、成本低等特点,应用前景广阔。     

Membrane microcantilever arrays fabrication with PZT thin films for nanorange movement

Lead zirconate titanate (PZT) piezoelectric thin films have been prepared by sol-gel method to fabricate microcantilever arrays for nano-actuation with potential applications in the hard disk drives. In order to solve the silicon over-etching problem, which leads to a low production yield in the microcantilever fabrication process, a new fabrication process using DRIE etching of silicon from the front side of the silicon wafer has been developed. Silicon free membrane microcantilevers with PZT thin films of 1 μm in thickness have been successfully fabricated with almost 100% yield by this new process. Annealing temperature and time are critical to the preparation of the sol-gel PZT thin film. The fabrication process of microcantilever arrays in planar structure will be presented. Key issues on the fabrication of the cantilever are the compatible etching process of PZT thin film and the compensation of thin film stress in all layers to obtain a flat multi-layer structure.     

Polymer microstructure generated by laser stereo-lithography and its transfer to silicon substrate using reactive ion etching

Micro-fabrication combining stereo-lithography with reactive ion etching is proposed. Three-dimensional polymer structures smaller than 1 mm are fabricated on silicon wafer by He-Cd (325.0 nm) laser stereo-lithography. Using the polymer structure having a high-aspect ratio as resist for deep reactive ion etching, the microstructure is transferred to the silicon substrate with an etching ratio of 0.5. The proposed technique has been demonstrated by the fabrication of lens-like structures.     

MEMS Vertical Probe Cards With Ultra Densely Arrayed Metal Probes for Wafer-Level IC Testing

We have developed a MEMS probe-card technology for wafer-level testing ICs with 1-D line-arrayed or 2-D area-arrayed dense pads layouts. With a novel metal MEMS fabrication technique, an area-arrayed tip matrix is realized with an ultradense tip pitch of $90 muhbox{m} times 196 mu hbox{m}$ for testing 2-D pad layout, and a 50-$muhbox{m}$ minimum pitch is also achieved in line-arrayed probe cards for testing line-on-center or line-on-perimeter wafers. By using the anisotropic etching properties of single-crystalline silicon, novel oblique concave cavities are formed as electroplating moulds for the area-arrayed microprobes. With the micromachined cavity moulds, the probes are firstly electroplated in a silicon wafer and further flip-chip packaged onto a low-temperature cofired ceramic board for signal feeding to an automatic testing equipment. The microprobes can be efficiently released using a silicon-loss technique with a lateral underneath etching. The measured material properties of the electroplated nickel and the Sn–Ag solder bump are promising for IC testing applications. Mechanical tests have verified that the microprobes can withstand a 65-mN probing force, while the tip displacement is 25 $muhbox{m}$, and can reliably work for more than 100 000 touchdowns. The electric test shows that the probe array can provide a low contact resistance of below 1 $Omega$, while the current leakage is only 150 pA at 3.3 V for adjacent probes.$hfill$[2008-0273]      

Diagnostic techniques for the dynamics of a thin liquid film under forced flow and evaporating conditions

Motivated by quantification of micro-hydrodynamics of a thin liquid film which is present in industrial processes, such as spray cooling, heating (e.g., boiling with the macrolayer and the microlayer), coating, cleaning, and lubrication, we use micro-conductive probes and confocal optical sensors to measure the thickness and dynamic characteristics of a liquid film on a silicon wafer surface with or without heating. The simultaneous measurement on the same liquid film shows that the two techniques are in a good agreement with respect to accuracy, but the optical sensors have a much higher acquisition rate up to 30 kHz which is more suitable for rapid process. The optical sensors are therefore used to measure the instantaneous film thickness in an isothermal flow over a silicon wafer, obtaining the film thickness profile and the interfacial wave. The dynamic thickness of an evaporating film on a horizontal silicon wafer surface is also recorded by the optical sensor for the first time. The results indicate that the critical thickness initiating film instability on the silicon wafer is around 84 μm at heat flux of ~56 kW/m². In general, the tests performed show that the confocal optical sensor is capable of measuring liquid film dynamics at various conditions, while the micro-conductive probe can be used to calibrate the optical sensor by simultaneous measurement of a film under quasi-steady state. The micro-experimental methods provide the solid platform for further investigation of the liquid film dynamics affected by physicochemical properties of the liquid and surfaces as well as thermal-hydraulic conditions.     

Hydrogenation-Assisted Lateral Micromachining of (111) Silicon Wafers

Micromachining of (111) silicon wafers by means of a plasma hydrogenation and chemical etching sequence is achieved. Vertical etching is used to define the depth of the craters as well as the thickness of the final suspended silicon body. After protecting the 3-D structure by a thermally grown oxide, a hydrogenation step is used to remove the oxide layer from the bottom of the crater, allowing a lateral underetching. Final exposure of the processed silicon to a KOH solution, etches silicon in a lateral fashion and in the exposed places. A lateral aspect ratio of four to six has been achieved. The evolution of suspended structures on (111) wafers, suitable for sensor fabrication, is feasible without a need to a 3-D lithography. Using this technique suspended interdigital structures have been realized with a depth up to 70 $mu hbox{m}$. In addition, ultrathin fully suspended structures have been successfully fabricated. A preliminary capacitive accelerometer has been realized and tested on (111) substrate.$hfill$ [2008-0070]      

A combinative technique to fabricate hot embossing master for PMMA tunneling sensors

A combinative approach of anisotropic bulk etching and modified plasma etching has been successfully employed in a single wafer to fabricate silicon masters for the hot embossing process. The masters hold both pyramid pits and positive profile sidewalls with smooth surfaces and steep angles. The SiO₂ layer is utilized as a etching mask with the aid of photoresist in three steps of photolithography patterning. The first polymethyl-methacrylate (PMMA)-based tunneling transducer with polymer membrane structures is fabricated by hot embossing replication with the silicon master. Consequently, the exponential relations between tunneling currents and applied deflection voltages are also reported.This work is partially supported by grants NSF/LEQSF (2001–04)-RII-02, DARPA DAAD19–02–1-0338, and NASA (2002)-Stennis-22.     

A two-step etching method to fabricate nanopores in silicon

A cost effective method to fabricate nanopores in silicon by only using the conventional wet-etching technique is developed in this research. The main concept of the proposed method is a two-step etching process, including a premier double-sided wet etching and a succeeding track-etching. A special fixture is designed to hold the pre-etched silicon wafer inside it such that the track-etching can be effectively carried out. An electrochemical system is employed to detect and record the ion diffusion current once the pre-etched cavities are etched into a through nanopore. Experimental results indicate that the proposed method can cost effectively fabricate nanopores in silicon. A through pore with pore size being around 14 nm can be fabricated.     

Synchrotron radiation analysis of microstructures

 The outstanding spectral and spatial characteristics of synchrotron radiation make it a powerful analytical tool in microstructure technology. We apply absorption spectroscopy to study foils of electroplated Permalloy (NiFe), and of nickel phosphorus, because they are of interest to microfabrication for their soft magnetic properties and their selective etching behaviour, respectively. In particular, we show that in the electroplated Permalloy foils Ni keeps the structure of pure Ni while Fe changes from b.c.c. to f.c.c. NiP foils become increasingly amorphous with growing P content. In this way, radial elemental distributions which determine magnetic or other properties can be monitored sensitively to improve electroplating process control, even in situ. We also measure the radial thickness profile of a gold layer sputtered on top of a chromium coated silicon wafer. This technique might be extended to measure a given layer in a multilayer structure selectively and non-destructively even when hidden or opaque. Received: 30 October 1995/Accepted: 18 December 1995     

Nanoscale Pattern Definition on Nonplanar Surfaces Using Ion Beam Proximity Lithography and Conformal Plasma-Deposited Resist

Ion beam proximity lithography (IBL) is a technique where a broad beam of energetic light ions floods a stencil mask and transmitted beamlets transfer the mask pattern to resist on a substrate. With a depth-of-field up to 20000 times larger than the minimum feature size and the high-throughput potential of a parallel exposure tool, IBL is very attractive for prototyping and manufacturing nanoelectromechanical systems over the steep topography of micromachined silicon wafers. This paper reports a conformal resist coating process that unlocks this potential. This negative-tone resist, plasma-polymerized methyl methacry- late, has a sensitivity of 27 muC/cm² and a contrast of 1.3 for 30-keV He⁺ ion exposures and amyl acetate developer. Sub-100-nm features have been printed down the sidewall and across a membrane at the bottom of a 500-mum-deep anisotropically etched pit in a silicon wafer. Pattern fidelity is near 2 nm for 10-nm features. Lines have also been formed on unpolished substrates, including rolled titanium foils and coarse-ground silicon wafers. Patterns on ground silicon have been etched into the surface using a nickel hard mask and SF₆/O₂ reactive ion etching.     

Synchrotron radiation analysis of microstructures

The outstanding spectral and spatial characteristics of synchrotron radiation make it a powerful analytical tool in microstructure technology. We apply absorption spectroscopy to study foils of electroplated Permalloy (NiFe), and of nickel phosphorus, because they are of interest to microfabrication for their soft magnetic properties and their selective etching behaviour, respectively. In particular, we show that in the electroplated Permalloy foils Ni keeps the structure of pure Ni while Fe changes from b.c.c. to f.c.c. NiP foils become increasingly amorphous with growing P content. In this way, radial elemental distributions which determine magnetic or other properties can be monitored sensitively to improve electroplating process control, even in situ. We also measure the radial thickness profile of a gold layer sputtered on top of a chromium coated silicon wafer. This technique might be extended to measure a given layer in a multilayer structure selectively and non-destructively even when hidden or opaque.     

基于BOE硅腐蚀现象的硅纳米线制作

介绍一种硅纳米线制作方法.在SOI顶层硅上制作硅纳米梁,通过离子注入形成pnp结构,利用新发现的没有特殊光照时BOE溶液腐蚀pn结n型区域现象,结合BOE溶液氧化硅腐蚀,实现硅纳米线制作.制作完全采用传统MEMS工艺,具有工艺简单,成本低,可控,可靠性好,可批量制作等优点.利用该方法制作出了厚50 nm,宽100 nm的单晶硅纳米线,制作的纳米线可用于一维纳米结构电学性能研究、谐振器研究等.     

Three-dimensional thin-film shape memory alloy microactuator withtwo-way effect

A novel thin film (micrometer thickness) shape memory alloy (SMA) micro actuator is presented in this paper. The thin film SMA with composition of approximately 50:50 nickel titanium (NiTi) is sputter-deposited onto a silicon wafer in an ultra high vacuum system. Transformation temperatures of the NiTi film are determined by measuring the residual stress as a function of temperature. The transformation temperature is independent of the presence of chromium (Cr) used as an adhesion layer, or being exposed to air before annealing. A mixture of hydrofluoric acid (HF), nitric acid (HNO₃) and deionized (DI) water is used to etch the film. Different etch masks are evaluated to protect the NiTi film during the etching. Among the masks tested, a thick photoresist (AZ-4620) produces the best result. The NiTi membrane is hot-shaped into a three-dimensional (3-D) dome shape using a stainless-steel jig. Results indicate the membrane exhibits two-way effect. The performance of the SMA micro actuator is characterized with a laser measurement system for deflection versus input power and frequency response