The effects of NH3 plasma passivation on polysiliconthin-film transistors

The NH₃ plasma passivation has been performed for the first time on the polycrystalline silicon (poly-Si) thin-film transistors (TFT's). It is found that the TFT's after the NH₃ plasma passivation achieve better device performances, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability as well as thermal stability than the H₂-plasma devices. These improvements were attributed to not only the hydrogen passivation of the grain-boundary dangling bonds, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films     

Characteristics of polysilicon thin-film transistor with thin-gatedielectric grown by electron cyclotron resonance nitrous oxide plasma

Polysilicon thin-film transistors (poly-Si TFT's) with thin-gate oxide grown by electron cyclotron resonance (ECR) nitrous oxide (N₂ O)-plasma oxidation is presented. ECR N₂O-plasma oxidation successfully incorporates nitrogen atoms at the SiO₂/poly-Si interface, consequently forms a nitrogen-rich layer with Si≡N bonds at a binding energy of 397.8 eV. ECR N₂ O-plasma oxide grown on poly-Si films shows higher breakdown fields than thermal oxide. The fabricated poly-Si TFT's with N₂ O-plasma oxide show better performance than those with ECR O₂ -plasma oxide, which results not only from the smooth interface but also oxygen- and nitrogen-plasma passivation     

The combined effects of low pressure NH3-annealing and H2 plasma hydrogenation on polysilicon thin-film transistors

The low pressure NH₃-annealing and the H₂ plasma hydrogenation were jointly used to improve the characteristics of polysilicon thin-film transistors (TFT's). It was found that the TFT's after applying the above treatments achieved better subthreshold swings, threshold voltages, field effect mobilities, off currents, and reliability. It is believed that the improvement was due to the gate oxynitride formation and the H₂-plasma had a better passivation effect on the oxynitride     

The effects of fluorine passivation on polysilicon thin-filmtransistors

The fluorine implantation on polysilicon was found to improve the characteristics of polysilicon thin-film transistors (TFT's). The fluorine passivates the trap states within the polysilicon channel, as compared with the H₂-plasma passivation. The fluorine implantation passivates more uniformly both the band tail-states and midgap deep-state, while the H₂-plasma treatment is more effective to passivate deep states than tail states. A fluorine-implanted device can be further improved its performance if an H₂-plasma treatment is applied. In contrast to the H₂ -plasma passivation, the fluorine passivation improves the device hot-carrier immunity. Combining the fluorine passivation and H₂ -plasma passivation, a high performance TFT with a high hot-carrier immunity can be obtained     

Enhanced H2-plasma effects on polysilicon thin-filmtransistors with thin ONO gate-dielectrics

This letter reports that passivation effects of the H₂-plasma on the polysilicon thin-film transistors (TFT's) were greatly enhanced if the TFT's have a thin Si₃N₄ film on their gate-dielectrics. Compared to the conventional devices with only the SiO₂ gate dielectric, the TFT's with Si ₃N₄ have much more improvement on their subthreshold swing and field-effect mobility after H₂-plasma treatment     

Characteristics of top-gate thin-film transistors fabricated onnitrogen-implanted polysilicon films

The electrical characteristics of top-gate thin-film transistors (TFT's) fabricated on the nitrogen-implanted polysilicon of the doses ranging from 2×10¹²-2×10¹⁴ ions/cm² were investigated in this work. The experimental results showed that nitrogen implanted into polysilicon followed by an 850°C 1 h annealing step had some passivation effect and this effect was much enhanced by a following H₂-plasma treatment. The threshold voltages, subthreshold swings, ON-OFF current ratios, and field effect mobilities of both n-channel and p-channel TFT's were all improved. Moreover, the hot-carrier reliability was also improved. A donor effect of the nitrogen in polysilicon was also found which affected the overall passivation effect on the p-channel TFT's     

A comparison of hydrogen and deuterium plasma treatment effects onpolysilicon TFT performance and dc reliability

We compare the performance and dc reliability of conventional top-gate, self-aligned polysilicon (poly-Si) thin-film transistors (TFT's) after passivation by plasma deuteration and conventional plasma hydrogenation. An optimum deuteration temperature of 300°C is found, as compared to 350°C for hydrogenation. Deuteration yields comparable TFT performance as hydrogenation, while deuterated TFT's exhibit increased resistance to threshold voltage degradation under dc stress. These results indicate that deuteration is a promising alternative to hydrogenation for achieving high-performance, high-reliability poly-Si TFT's for applications such as flat-panel displays     

Novel gate dielectric films formed by ion plating forlow-temperature-processed polysilicon TFTs

A novel SiO₂ film formed by ion plating (IP) at room temperature was developed for low-temperature-processed (LTP) (<625°C) polysilicon thin-film transistors (poly-Si TFT's). The IP SiO₂ film is a high-density dielectric with strained bonds, and also a high-performance insulator with low-leakage current and high-breakdown voltage. Poly-Si TFT with IP SiO₂ as a gate insulator shows satisfactory performance     

A high-performance polysilicon thin-film transistor using XeClexcimer laser crystallization of pre-patterned amorphous Si films

A high-performance polysilicon thin-film transistor (TFT) fabricated using XeCl excimer laser crystallization of pre-patterned amorphous Si films is presented. The enhanced TFT performance over previous reported results is attributed to pre-patterning before laser crystallization leading to enhanced lateral grain growth. Device performance has been systematically investigated as a function of the laser energy density, the repetition rate, and the number of laser shots. Under the optimal laser energy density, poly-Si TFT's fabricated using a simple low- temperature (⩽600°C) process have field-effect mobilities of 91 cm²/V·s (electrons) and 55 cm²/V·s (holes), and ON/OFF current ratios over 10 ⁷ at V_Ds=10 V. The excellent overall TFT performance is achieved without substrate heating during laser crystallization and without hydrogenation. The results also show that poly-Si TFT performance is not sensitive to the laser repetition rate and the number of laser shots above 10     

Study on hydrogenation of polysilicon thin film transistors by ionimplantation

Hydrogenation of polysilicon (poly-Si) thin film transistors (TFT's) by ion implantation has been systematically studied. Poly-Si TFT performance was dramatically improved by hydrogen ion implantation followed by a forming gas anneal (FGA). The threshold voltage, channel mobility, subthreshold swing, leakage current, and ON/OFF current ratio have been studied as functions of ion implantation dose and FGA temperature. Under the optimized conditions (H⁺ dose of 5×10¹⁵ cm^-2 and FGA temperature at 375°C), NMOS poly-Si TFT's fabricated by a low temperature 600°C process have a mobility of ~27 cm ²/V·s, a threshold voltage of ~2 V, a subthreshold swing of ~0.9 V/decade, and an OFF-state leakage current of ~7 pA/μm at V_DS=10 V. The avalanche induced kink effect was found to be reduced after hydrogenation     

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

Plasma ion implantation hydrogenation of poly-Si CMOS thin-filmtransistors at low energy and high dose rate using aninductively-coupled plasma source

Defect passivation in polycrystalline silicon (poly-Si) CMOS thin-film transistors (TFT's) has been performed by plasma ion implantation (PII) hydrogenation process. Implantation at low energy (2 keV) and high dose rate(~10¹⁶/cm² S) was achieved by an inductively-coupled plasma source. The device parameter improvements are saturated in 3-4 min, which is much shorter than other hydrogenation methods reported in the literature. The stress measurements indicate that the devices hydrogenated by this new technique have much better long-term reliability than that hydrogenated by other techniques     

Inverse staggered poly-Si and amorphous Si double structure TFT'sfor LCD panels with peripheral driver circuits integration

Inverse staggered polycrystalline silicon (poly-Si) and hydrogenated amorphous silicon (a-Si:H) double structure thin-film transistors (TFT's) are fabricated based on the conventional a-Si:H TFT process on a single glass substrate. After depositing a thin (20 nm) a-Si:H using the plasma CVD technique at 300°C, Ar⁺ and XeCl (300 mJ/cm²) lasers are irradiated successively, and then a thick a-Si:H (200 nm) and n⁺ Si layers are deposited again. The field effect mobilities of 10 and 0.5 cm ²/V·s are obtained for the laser annealed poly-Si and the a-Si:H (without annealing) TFT's, respectively     

Thinner liquid phase deposited oxide for polysilicon thin-filmtransistors

To scale down the gate insulator thickness of polysilicon thin-film transistors (poly-Si TFT's), a thinner oxide is developed by liquid-phase deposition with a small quantity of H₂O added, producing a rather high-quality oxide. Poly-Si TFT with such a thin oxide reveals good performances in electric characteristics. Thus, the novel thinner oxide is a good candidate as a poly-Si TFT gate insulator in the near future     

Effects of Oxynitride Buffer Layer on the Electrical Characteristics of Poly-Silicon TFTs Using $hbox{Pr}_{2}hbox{O}_{3}$ Gate Dielectric

In this paper, we have developed high-k Pr₂O₃ poly-Si thin-film transistors (TFTs) using different N₂O plasma power treatments. High-k Pr₂O₃ poly-Si TFT devices using a 200-W plasma power exhibited better electrical characteristics in terms of high effective carrier mobility, high driving current, small subthreshold slope, and high I_ON/I_OFF current ratio. This result is attributed to the smooth Pr₂O₃/poly-Si interface and low interface trap density. Pr₂O₃ poly-Si TFT with a 200-W N₂O plasma power also enhanced electrical reliabilities such as hot carrier and positive bias temperature instability. All of these results suggest that a high-k Pr₂O₃ gate dielectric with the oxynitride buffer layer is a good candidate for high-performance low-temperature poly-Si TFTs.     

High-performance poly-Si TFTs with ECR-plasma hydrogen passivation

High-performance thin-film transistors (TFTs) with electron-cyclotron resonance (ECR) plasma hydrogen passivation fabricated by the use of laser-recrystallized multiple-strip-structure poly-Si film are discussed. These TFTs have n-channel enhancement-mode characteristics with a large transconductance, a high switching ratio, and a threshold voltage as low as 0.4 v. The ECR-plasma hydrogen passivation of laser-recrystallized poly-Si, reduces the trap density of poly-Si and increases the carrier mobility thus, desirable TFT characteristics are obtained. This passivation increased the transconductance (g_m) of a TFT and decreased the leakage current between the source and the drain. As a result, a switching ratio as high as 2.5×10⁹ and very low leakage current of the order of 10¹⁴ A can be achieved by these high-performance TFTs     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

A novel polysilicon thin-film transistor with a p-n-p structuredgate electrode

We propose and fabricate a novel polycrystalline silicon thin-film transistor (poly-Si TFT) which exhibits the properties of an offset gated structure in the OFF state, while acting as a nonoffset structure in the ON state. The fabrication process is compatible with the conventional nonoffset poly-Si TFT's process and does not require any additional mask. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device. It is observed that the ON/OFF current ratio of the proposed poly-Si TFT is improved remarkably     

Stable polycrystalline silicon TFT with MICC

We studied the bias-induced changes in the performance of the poly-Si thin-film transistor (TFT) by metal-induced crystallization of amorphous silicon through a cap layer (MICC) poly-Si. The p-channel poly-Si TFT exhibited a field-effect mobility of 101 cm/sup 2//V/spl middot/s and a minimum leakage current of <1.0/spl times/10/sup -12/ A//spl mu/m at V/sub ds/=-10 V. The MICC poly-Si TFT performance changes little by either gate or hot-carrier bias stress. The better stability appears to be due to the smooth surface of MICC poly-Si, which is /spl sim/2 nm that is much smaller than that (13 nm) of a laser-annealed poly-Si.     

Characterizing Fluorine-Ion Implant Effects on Poly-Si Thin-Film Transistors With ${hbox{Pr}}_{2}{hbox{O}}_{3}$ Gate Dielectric

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k Pr₂O₃ as gate dielectric is investigated for the first time. Using the Pr₂O₃ gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr₂O₃/poly-Si interface to improve the device electrical properties. The Pr₂O₃ TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr₂O₃ TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr₂O₃ TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr₂O₃ TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.