Investigation of flip chip under bump metallization systems of Cupads

In this study, UBM material systems for flip chip solder bumps on Cu pads were investigated using the electroless copper (E-Cu) and electroless nickel (E-Ni) plating methods; and the effects of the interfacial reaction between UBMs and Sn-36Pb-2Ag solders on the solder bump joint reliability were also investigated to optimize UBM materials for flip chip on Cu pads. For the E-Cu UBM, scallop-like Cu₆Sn₅, intermetallic compound (IMC) forms at the solder/E-Cu interface, and bump fracture occurred along this interface under a relatively small load. In contrast, at the E-Ni/E-Cu UBM, E-Ni serves as a good diffusion-barrier layer. The E-Ni effectively limited the growth of the IMC at the interface, and the polygonal-shape Ni₃ Sn₄ IMC resulted in a relatively higher adhesion strength compared with the E-Cu UBM. As a result, electroless deposited UBM systems were successfully demonstrated as low cost UBM alternatives on Cu pads. It was found that the E-Ni/E-Cu UBM material system was a better choice for solder flip chip interconnection on Cu pads than the E-Cu UBM     

Developing an analytic methodology to accurately predict probing depth in integrated circuit structures

This work designs an analytic methodology for applying the probe-before-bump procedure to predict probing depth and proposes feasible probing design parameters to avoid excessive probing of the bump pad. Two kinds of multi-level wafers were used to implement the probing experiment, with a single touch down, and an overdrive of 70 μm, 100 μm, 130 μm, and 150 μm by using a vertical probe card. The Young’s modulus and hardness of the two multilevel structures are measured on which the first bump pads are produced by sputtering aluminum onto the SiO₂, while the second bump pads are produced by sputtering aluminum onto the copper, creating a pad metal of approximately 1-μm thickness by using the nanoindenter. The test results indicate that the Young’s modulus of the thin film material exceeds that of bulk material by 20–30 GPa. The difference between analytic and experimental probing depth ranges from 2.3% to 8.9%, revealing that the proposed novel analytic model is extremely accurate. Engineers or researchers can use the analytic methodology to accurately predict probing depth and acquire probing parameters that are accurate, cost effective, and efficient, thus eliminating the need to use focused ion beam (FIB) or other measurement instruments to determine the probing depth.     

Growth prediction of tin/copper intermetallics formed between 63/37 Sn/Pb and OSP coated copper solder pads for a flip chip application

This study quantifies the effect of temperature and time on the growth of Cu-Sn intermetallics, specifically for flip chip/ball grid array packaging technology. The activation energy and the growth rates were determined for solid state diffusion, after the initial assembly reflow(s). Three different types of solder joints were investigated. 1) BGA 63/37 solder joints which were formed by a standard convection oven attach of 30 mil (760 /spl mu/m)diameter solder spheres to OSP protected, Cu plated ball pads of an organic flip chip substrate. The ball pads are solder mask defined and of 0.635 mm nominal diameter. 2) Flip chip bump pad solder joint consisting of 63/37 eutectic solder bumped die attached to a nonsolder mask defined, OSP protected, Cu plated pad of the flip chip substrate. The flip chip bumps on the die are created by screen printing solder paste on the die pads and subsequent reflow attach, by a standard convection oven to the die under bump metallurgy (UBM). The nominal die UBM pad diameter is 0.085 mm. 3) Solder joint formed on a coupon which involved the reflow of the balls randomly placed on a Cu plated layer with no solder mask coating. The investigation was performed by first establishing the intermetallic growth rate at six different temperatures, ranging from 85/spl deg/C to 150/spl deg/C. The relationship between intermetallic growth and time was shown to essentially follow the common parabolic diffusion relationship to temperature especially above 100/spl deg/C. The activation energy (E/sub a/) and the growth constant (k/sub 0/) were then calculated from this data. The results showed that the E. for the total intermetallic thickness was essentially similar for the three solder joint configurations of the ball, bump and the coupon described above. E. varied from 0.31 eV to 0.32 eV, while the k/sub 0/ varied from 18.0 /spl mu/m/s/sup 1/2 / to 24.2 /spl mu/m/s/sup 1/2 /.     

Interfacial reaction and joint reliability of fine-pitch flip-chip solder bump using stencil printing method

This study was focused on the formation and reliability evaluation of solder joints with different diameters and pitches for flip chip applications. We investigated the interfacial reaction and shear strength between two different solders (Sn-37Pb and Sn-3.0Ag-0.5Cu, in wt.%) and ENIG (Electroless Nickel Immersion Gold) UBM (Under Bump Metallurgy) during multiple reflow. Firstly, we formed the flip chip solder bumps on the Ti/Cu/ENIG metallized Si wafer using a stencil printing method. After reflow, the average solder bump diameters were about 130, 160 and 190 μm, respectively. After multiple reflows, Ni₃Sn₄ intermetallic compound (IMC) layer formed at the Sn-37Pb solder/ENIG UBM interface. On the other hand, in the case of Sn-3.0Ag-0.5Cu solder, (Cu,Ni)₆Sn₅ and (Ni,Cu)₃Sn₄ IMCs were formed at the interface. The shear force of the Pb-free Sn-3.0Ag-0.5Cu flip chip solder bump was higher than that of the conventional Sn-37Pb flip chip solder bump.     

Electroless Ni/Au Bump on a Copper Patterned Wafer for the CMOS Image Sensor Package in Mobile Phones

Wafer bumping technology using an electroless Ni/Au bump on a Cu patterned wafer is studied for the flip chip type CMOS image sensor (CIS) package for the camera module in mobile phones. The effect of different pretreatment steps on surface roughness and etching of Cu pads is investigated to improve the adherence between the Cu pad and the Ni/Au bump. This study measures the shear forces on Ni/Au bumps prepared in different ways, showing that the suitable pretreatment protocol for electroless Ni plating on Cu pads is “acid dip followed by Pd activation” rather than the conventional progression of “acid-dip, microetching, and Pd activation.” The interface between the Cu pad and the Ni/Au bump is studied using various surface analysis methods. The homogeneous distribution of catalytic Pd on the Cu pad is first validated. The flip chip package structure is designed, assembled, and tested for reliability. The successful flip chip bonding in the CIS package is characterized in terms of the cross-sectional structure in which the anisotropic conductive film (ACF) particles are deformed to about 1.5 μm in diameter. The experimental results suggest that electroless Ni/Au can be applied to the flip chip type CIS package using Cu patterned wafers for high mega pixel applications.     

Experimental characterization and mechanical behavior analysis of intermetallic compounds of Sn–3.5Ag lead-free solder bump with Ti/Cu/Ni UBM on copper chip

Due to today’s trend towards ‘green’ products, the environmentally conscious manufacturers are moving toward lead-free schemes for electronic devices and components. Nowadays the bumping process has become a branch of the infrastructure of flip chip bonding technology. However, the formation of excessively brittle intermetallic compound (IMC) between under bump metallurgy (UBM)/solder bump interface influences the strength of solder bumps within flip chips, and may create a package reliability issue. Based on the above reason, this study investigated the mechanical behavior of lead-free solder bumps affected by the solder/UBM IMC formation in the duration of isothermal aging. To attain the objective, the test vehicles of Sn–Ag (lead-free) and Sn–Pb solder bump systems designed in different solder volumes as well as UBM diameters were used to experimentally characterize their mechanical behavior. It is worth to mention that, to study the IMC growth mechanism and the mechanical behavior of a electroplated solder bump on a Ti/Cu/Ni UBM layer fabricated on a copper chip, the test vehicles are composed of, from bottom to top, a copper metal pad on silicon substrate, a Ti/Cu/Ni UBM layer and electroplated solder bumps. By way of metallurgical microscope and scanning-electron-microscope (SEM) observation, the interfacial microstructure of test vehicles was measured and analyzed. In addition, a bump shear test was utilized to determine the strength of solder bumps. Different shear displacement rates were selected to study the time-dependent failure mechanism of the solder bumps. The results indicated that after isothermal aging treatment at 150 °C for over 1000 h, the Sn–Ag solder revealed a better maintenance of bump strength than that of the Sn–Pb solder, and the Sn–Pb solder showed a higher IMC growth rate than that of Sn–Ag solder. In addition, it was concluded that the test vehicles of copper chip with the selected Ti/Cu/Ni UBMs showed good bump strength in both the Sn–Ag and Sn–Pb systems as the IMC grows. Furthermore, the study of shear displacement rate effect on the solder bump strength indicates that the analysis of bump strength versus thermal aging time should be identified as a qualitative analysis for solder bump strength determination rather than a quantitative one. In terms of the solder bump volume and the UBM size effects, neither the Sn–Ag nor the Sn–Pb solders showed any significant effect on the IMC growth rate.     

Wafer level and flip chip design through solder prediction modelsand validation

In flip chip package applications, bumped dies are flip-chip assembled to substrate metal pads creating joints that serve electrically and mechanically. Resulting solder joint profiles are defined by the solder bump volume, the under bump metallurgy (LTBM) area, and the substrate metal pad size and shape. Solder bump height and diameter was predicted by the geometrical truncated sphere model and surface evolver model at the wafer level, using the known solder volume deposited by stencil printing method. The surface evolver model was used to predict the assembled solder joint height, gap height, collapse height, and maximum bump diameter of flip chip assemblies. In turn, substrate pads were fine-tuned to achieve required gap heights. Collapse heights provided the means to develop assembly tolerances and relative risk of bridging was determined from knowledge of resulting bump diameters. Through validated design of the stencil printing technology and prediction of realistic bump and assembly solder geometries, the results are improved processes and die level design and assembly. Optimized design parameters are incorporated and accurately represented in simulation and experimentally validated with assemblies     

The influence of Sn–Cu–Ni(Au) and Sn–Au intermetallic compounds on the solder joint reliability of flip chips on low temperature co-fired ceramic substrates

The formation of intermetallic compounds in the solder joint of a flip chip or chip scale package depends on the under bump metallurgy (UBM), the substrate top surface metallisation, the solder alloy and the application conditions. To evaluate the influence of intermetallic compounds on the solder joint reliability, a detailed study on the influence of the UBM, the gold finish thickness of the substrate top surface metallisation, the solder alloy and the aging conditions has been conducted. Flip chips bumped with different solder alloys were reflow-mounted on low temperature co-fired ceramic substrates. The flip chip package was then aged at high temperature and a bump shear test followed to examine the shear strength of the solder joint at certain aging intervals. It was found that the type of UBM has a great impact on the solder joint reliability. With Ni(P)/Au as the UBM, well-documented gold embrittlement was observed when the gold concentration in the eutectic SnPb solder was about 3 wt%. When Al/Ni(V)/Cu was used as the UBM, the solder joint reliability was substantially improved. Copper dissolution from the UBM into the solder gives different intermetallic formations compared to Ni(P)/Au as UBM. The addition of a small amount of copper in the solder alloy changed the mechanical property of the intermetallic compound, which is attributed to the formation of Sn–Cu–Ni(Au) intermetallic compounds. This could be used in solving the problem of the AuSn₄ embrittlement. The formation and the influence of this Sn–Cu–Ni(Au) intermetallic phase are discussed. The gold concentration in the solder joint plays a role in the formation of intermetallic compounds and consequently the solder joint reliability, especially for the Sn–Ag–Cu soldered flip chip package.     

Conversion of the under bump metallurgy into intermetallics: the impact on flip chip reliability

In high temperature applications, the conversion of the under bump metallurgy (UBM) into UBM-Sn intermetallics can ultimately limit the reliability of flip chip components. Here, an intermetallic growth model characterizing the rate of electrical failure to the rate of UBM consumption is developed which derives a relationship between field reliability and accelerated temperature tests. For a flip chip structure employing eutectic Sn/Pb solder joined to Ni(V), bump shear and temperature storage were then used in concert with temperature cycling or high temperature operating life tests to evaluate the interaction of UBM loss with respect to electromigration and solder fatigue. In this way, field life was estimated for a given set of conditions: mechanical loading, temperature, temperature gradients, and applied current. While shear testing proved a poor indicator of bump reliability, a modified bump shear technique allowed a simple visual method for monitoring the amount of UBM consumption following accelerated testing. A seemingly unimportant variable, the surface finish of the substrate, was found to play a significant role in determining the rate of intermetallic growth, and hence, impacted the overall reliability. In particular, the incorporation of small amounts of gold into the solder joint during assembly reflow of gold finished substrates influenced the reaction of Ni into SnNi intermetallics. The role of gold, the impact on reliability, and potential corrective actions are discussed.     

Application of Al/PI composite bumps to COG bonding process

This work demonstrates the probing, testability and applicability of Al/PI (aluminum/polyimide) composite bumps to the chip on-glass (COG) bonding process for liquid crystal display (LCD) driver chip packaging. The experimental results showed that the thickness of Al overlayer on PI core of the bump, the location of pin contact, and the bump configuration affect bump probing testability. The bump with type IV configuration prepared in this work exhibited excellent probing testability when its Al overlayer thickness exceeded 0.8 μm. We further employed Taguchi method to identify the optimum COG bonding parameters for the Al/PI composite bump. The four bonding parameters, bonding temperature, bonding time, bonding pressure and thickness of Al overlayer are identified as 180° C, 10 s, 800 kgf/cm² and 1.4 μm, respectively. The optimum bonding condition was applied to subsequent COG bonding experiments on glass substrates containing Al pads or indium tin oxide (ITO) pads. From the results of resistance measurement along with a series of reliability tests, Al pad is found to be a good substrate bonding pad for Al/PI bump to COG process. Excellent contact quality was observed when the bumps had Al overlayer thickness over 1.1 μm. As to the COG specimens with substrate containing ITO pads, high joint resistance suggested that further contact quality refinement is necessary to realize their application to COG process     

Al surface morphology effect on flip-chip solder bump shear strength

This paper reports the result of a study on the effect of aluminum pad surface morphology on the flip-chip solder bump reliability. The influence of the Al surface morphology on the electroless zinc/nickel/gold UBM is presented. The reliability of the solder bump as measured by ball shear force is reported. Al pad were produced using two RF sputtering systems: CVC-601 and Varian-3180. The Al targets used in CVC and Varian system were 99%Al–1%Si and 98.95%Al–1%Si–0.05%Ti respectively. The surface of the CVC sputtered Al samples were smooth while the surface of the Varian sputtered Al samples were rough. All the samples were subjected to the electroless zinc/nickel/gold plating. The results suggest that after plating, the smooth Al surface resulted in a fine nickel UBM surface while the rough Al surface formed a coarse nickel UBM surface. Ball shear test was conducted after the solder balls were bumped on the UBM. Result shows that the fine UBM surface samples have twice the shear strength compared to the samples with coarse UBM surface samples. The analysis of the results indicates that shear surface occurred at the UBM and the solder interface for samples with rough UBM surface leading to the lower shear strength. Nickel bump shear test result shows that pretreatment of Al pad surface by sodium hydroxide and nitric acid created more zinc seeds this led to better electroless nickel plating. Nickel bump shear tests also shows that double zincated bumps had higher shear strength than single zincated bumps. To obtain reliable flip-chip solder bumps, it is essential to maintain good Al pad surface morphology, pretreatment of the Al pad and undergo second zincation.     

An RDL UBM Structural Design for Solving Ultralow-K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging

Copper (Cu) pillar bumps tend to induce high thermal–mechanical stress during environmental tests and fabrication processes due to the high hardness of Cu, especially when applied with an ultralow-K (ULK) chip. A previous experiment showed that interfacial delamination was often observed in the ULK layers of conventional Cu pillar bump-type flip chip ball grid array (FCBGA) packages under thermal cycling, where under bump metallurgy (UBM) layers directly sit on the metal pads of silicon chips (herein termed ‘‘direct UBM structure’’). In this study, a UBM pad relocation scheme through redistribution layer (RDL) technology (herein termed ‘‘RDL UBM structure’’) is proposed to relieve the stress or ULK delamination issue. The proposed technique is tested on Cu pillar bump-type FCBGA packages subjected to thermal loading, the effectiveness of which is demonstrated through finite element stress simulation and experimental reliability tests. Simulation results reveal that the RDL UBM structure can greatly reduce the maximum stress in the ULK layers by as much as about 10% to 44%. Besides, it turns out that the Cu pillar bump-type FCBGA packages with the RDL UBM structure show good interconnect reliability performance in terms of thermal cycling, highly accelerated stress, and high-temperature storage.     

WLCSP中微焊球结构尺寸对其热应力的影响

晶圆级芯片尺寸封装(WLCSP)微焊球结构尺寸对其热机械可靠性有重要的影响。通过二维有限元模拟筛选出对WLCSP微焊球及其凸点下金属层(UBM)中热应力影响显著的参数,采用完全因子实验和多因子方差统计分析定量评估各种因子影响的显著性,最后建立三维模型,用子模型技术研究关键尺寸因子对热应力变化的影响。研究发现,焊球半径是影响焊球热应力的最关键尺寸因子,电镀铜开口和铜焊盘厚度对焊球热应力的影响也较显著;钝化层开口和焊球半径是影响UBM热应力的最关键尺寸因子。随着焊球半径增大,焊球热应力减小。     

Study of the UBM to copper interface robustness of solder bumps in flip chip packages

Shear tests on SnAg solder bumps were performed with a reduced height to the surface for a high shear force on the under bump metallurgy (UBM) to redistribution layer (RDL) copper interface. By this the failure mechanism of UBM–RDL delamination after stress tests simulating several assembly reflows could be reproduced. A design of experiment was done with corner wafers at worst case conditions for topography and interface clean. TEM cross sections confirmed nano scale carbon residues in the interface when reducing the clean efficiency. This results in a mechanically weakened interface with a present electrical contact. The shear test with reduced height is a more severe test beyond the JEDEC test to verify the bump robustness. This is important when existing bump technologies are used for flip chip package solutions with increased solder reflow requirements.     

Effects of pre-bump probing and bumping processes on eutectic solder bump electromigration

This paper investigates the electromigration reliability of flip chip packages with and without pre-bump wafer probing via high temperature operation life test (HTOL) using printed and electroplated bumps. Under bump metallization (UBM) of printed and electroplated bumps is a thin film of Al/Ni(V)/Cu and Ti/Cu/Ni, respectively, while the bump material consists of eutectic Sn/Pb solder. Current densities from 7380 to 20 100 A/cm² and ambient temperatures at 100, 125 and 150 °C are applied in order to study their impact on electromigration. The results reveal that the bump temperature has a higher influence than the current density when it comes to bump failures. The observed interconnect damage is from bumps with electrical current flowing upward into the UBM/bump interface (cathode). Identified failure sites and modes reveal structural damage at the region of the UBM and UBM/bump interface, in the form of solder voiding and cracking. The effects of current polarity, current crowding, and operation temperature are key factors to electromigration failures of flip chip packaging. The maximum allowable current density of the electroplated bumps is superior to the printed bumps by a factor of 3.0–3.7 times. Besides, the median time to failure (MTTF) of without-underfill packaging is preferred to that of with-underfill packaging by 1.5–2.2 times. Furthermore, the differences in MTTF between pre-bump and without pre-bump probing procedures are 2.0–19.4% and 1.6–10.3% for printed and electroplated bumps, respectively.     

Plasma reflow bumping of Sn-3.5 Ag solder for flux-free flip chip package application

A new flux-free reflow process using Ar+10%H/sub 2/ plasma was investigated for application to solder bump flip chip packaging. The 100-/spl mu/m diameter Sn-3.5wt%Ag solder balls were bonded to 250-/spl mu/m pitch Cu/Ni under bump metallurgy (UBM) pattern by laser solder ball bonding method. Then, the Sn-Ag solder balls were reflowed in Ar+H/sub 2/ plasma. Without flux, the wetting between solder and UBM occurred in Ar+H/sub 2/ plasma. During plasma reflow, the solder bump reshaped and the crater on the top of bump disappeared. The bump shear strength increased as the Ni/sub 3/Sn/sub 4/ intermetallic compounds formed in the initial reflow stage but began to decrease as coarse (Cu,Ni)/sub 6/Sn/sub 5/ grew at the solder/UBM interface. As the plasma reflow time increased, the fracture mode changed from ductile fracture within the solder to brittle fracture at the solder/UBM interface. The off-centered bumps self-aligned to patterned UBM pad during plasma reflow. The micro-solder ball defects occurred at high power prolonged plasma reflow.     

一种低成本倒装芯片用印刷凸焊点技术的研究

利用化学镀底部金属化层结合丝网印刷制作凸焊点的技术,通过剪切实验得到了凸焊点的剪切强度,用电子显微镜对失效表面进行了分析研究,应用SEM及EDAX分析了凸焊点的组织结构与成分变化,对热老炼后凸焊点的强度变化进行了研究。结果表明凸焊点内部组织结构的变化是剪切失效的主要原因。经X光及扫描声学显微镜检测,表明组装及填充工艺很成功。对已完成及未进行填充的两种FCOB样品进行热疲劳实验对比,发现未进行填充加固的样品在115周循环后出现失效,而经填充加固后的样品通过了1 000周循环,表明下填料明显延长了倒装焊封装的热疲劳寿命。     

化学镀镍、模版印刷法制备倒扣芯片焊料凸点

回顾了低成本制备芯片上焊料凸点的方法,即化学镀镍制备凸点下金属层、模版印刷焊料,最后回流形成焊料凸点,并综述了该方法的最新研究进展.     

Under bump metallurgy study on copper/low-k dielectrics for fine pitch flip chip packaging

Because the semiconductor speed increases continuously, more usage of low-k dielectric materials to enhance the performance in Cu chips has taken place over the past few years. The implementation of copper (Cu) as an interconnect, in conjunction with the ultra-low-k materials as interlevel dielectrics or intermetal dielectrics in the fabrication of ultra-large-scale integrated circuits, has been used in the semiconductor community worldwide, especially for high-speed devices. The objective of this study is to investigate the under bump metallurgy (UBM) characterization with low-k dielectric material used in damascene Cu-integrated circuits. This paper focuses on electroless Ni/Au, Cu/Ta/Cu, and Ti/ Ni(V)/Cu/Au UBM fabrication on 8-in. damascene Cu wafers and flip chip package reliability with Pb-bearing and Pb-free solders. The interfacial diffusion study and bump shear test were carried out to evaluate the bump bonding, and the failure was analyzed with optical microscopy, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). In order to investigate the thermal stability of the UBM system with Pb-free solder, high-temperature aging (above the melting temperature) was performed and each interface between the solder and UBM was observed with optical microscopy, SEM, and TEM, respectively. The failures observed and the modes are reported in the paper.     

Characterization of lead-free solders and under bump metallurgies for flip-chip package

A variety of Pb-free solders and under bump metallurgies (UBMs) was investigated for flip chip packaging applications. The result shows that the Sn-0.7Cu eutectic alloy has the best fatigue life and it possess the most desirable failure mechanism in both thermal and isothermal mechanical tests regardless of UBM type. Although the electroless Ni-P UBM has a much slower reaction rate with solders than the Cu UBM, room temperature mechanical fatigue is worse than on the Cu UBM when coupled with either Sn-3.8Ag-0.7Cu or Sn-3.5Ag solder. The Sn-37Pb solder consumes less Cu UBM than all other Pb-free solders during reflow. However, Sn-37Pb consumes more Cu after solid state annealing. Studies on aging, tensile, and shear mechanical properties show that the Sn-0.7Cu alloy is the most favorable Pb-free solder for flip chip applications. When coupled with underfill encapsulation in a direct chip attach (DCA) test device, the Sn-0.7Cu bump with Cu UBM exhibits a characteristic life or 5322 cycles under -55/spl deg/C/+150/spl deg/C air-to-air thermal cycling condition.